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Hi Andrew, Thank you for the information, but my problem is that I have 5 different designs and 5 prototypes of each. What you say can be interesting for future designs, but right now I need to have a solution to those expensive OTPROM circuits from Xilinx, and ATMEL was the only company that offered us such alternative. In our next version, we will drop the use of serial proms and will use a central CPU to download the configuration data to these FPGAs. Best regards, Farhad A. On Wed, 18 Nov 1998 21:36:19 +0100, Andrew Cannon <a.cannon@fairlightesp.com.au> wrote: >Farhad, > >I suggest you go to the Xilinx website and fetch application note XAPP079, which >describes using an EPROM and a CPLD to construct a "virtual serial EEPROM". You can >use a Flash instead of the EPROM to make a reprogrammable configuration ROM. > >If you can't find the app note there let me know and I'll email it to you. > >We also looked at using the Atmel parts but decided they were too expensive. > >- ajc *-------------------------------------------------------* * Farhad Abdolian AT_farhad_abdolian@hotmail.com * * homepage: http://www.algonet.se/~farhad * * http://come.to/farhad * * Stockholm/Sweden * * Please remove AT_ from address before replying * *-------------------------------------------------------*Article: 13176
Andrew Cannon wrote in message <36532FC2.DCB72064@fairlightesp.com.au>... >Farhad, > >I suggest you go to the Xilinx website and fetch application note XAPP079, which >describes using an EPROM and a CPLD to construct a "virtual serial EEPROM". You can >use a Flash instead of the EPROM to make a reprogrammable configuration ROM. If you use a flash instead of the EPROM, you have to figure out how to program the flash! -- andy ------------------------------------------ Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters@noao.edu "In the beginning, there was darkness. And it was without form, and void. And there was also me!" -- Bomb #20, John Carpenter's "Dark Star"Article: 13177
I have heard that Xilinx won't support XNF. Is this true? UtkuArticle: 13178
Utku Ozcan wrote: > > I have heard that Xilinx won't support XNF. Is this true? > I've heard the same and I'm also very disappointed. They plan use EDIF exclusively in some future release. XNF is good because it is easy so easy to parse. EDIF is a nightmare to parse. I have on a number of ocassions written small programs (Perl works REALLY well) to modify the XNF netlist before passing it throught the Xilinx compiler. XNF is also human readable which EDIF is not. Erik -- ------------------------------- Erik de Castro Lopo Fairlight ESP Pty Ltd e.de.castro AT fairlightesp.com.auArticle: 13179
do you know if it is possible to test/control a run-time reconfigurable design using VHDL? and how would you go about doing that?Article: 13180
Are there any serial EPROMs for use with Xilinx XC4k chips? The XC170x chips seem not to have an erasable variant but I'd like to avoid the wasted PCB space and adding jumpers etc. to change between a parallel III cable for development and a regular EPROM for the semi-permanent design. Chris -- Chris Eilbeck mailto:chris@yordas.demon.co.ukArticle: 13181
The M1 tools do not use the xnf format. They do currently have the ability to import xnf files, but there is no guarantee this will be supported in future releases. Utku Ozcan wrote: > I have heard that Xilinx won't support XNF. Is this true? > > Utku -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 13182
Atmel has a serial EEPROM which is more or less compatible with the 1701. You need to be careful of the reset polarity. Chris Eilbeck wrote: > Are there any serial EPROMs for use with Xilinx XC4k chips? The XC170x > chips seem not to have an erasable variant but I'd like to avoid the > wasted PCB space and adding jumpers etc. to change between a parallel > III cable for development and a regular EPROM for the semi-permanent > design. > > Chris > -- > Chris Eilbeck > mailto:chris@yordas.demon.co.uk -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 13183
Farhad, I have used both the AT17C010 and the AT17L010 parts and both of them work without any problem. What are the problems that you have seen? What is your reset polarity in your design? You have to make sure that when programming these parts they need to match your design. David - Farhad Abdolian wrote in message <365274e0.533057796@news>... >Hi, >I just received the programmer for AT17C010 Configuration FEPROM together with >some samples from their local repr. in Stockholm. > >I must say that for 400$ it was a very strange programmer, it seems to be the >first or second prototype with lots of patches but the board is marked at REV 7! >But using flash instead of those damn OTPROM from xilinx is the only alternative >for us right now, so I had to try it! > >Anyway, my problem is that I can not use AT17C010 instead of Xilinx 010 PROM! >and wonder if any of you have mannaged to use Atmel's proms without any >modification on the board level? > >Appreciate your help, > >Best regards, >Farhad A. >Article: 13184
"Kalyan Gokhale" <kgokhale@execpc.com> writes: >> >>I'm not totally convinced. Why do Intel designers choose an Endianness that >>is, well, counter-intutive? > >>--Shail Bains >The reasons are given in an IEEE-Micro Magazine (first issue of first year) >by Intel designers of 8008. As I don't have that issue, I don't know the reasons it says. Personally, the time it matters to me is reading hex dumps, and big-endian is much more convenient. I have heard it said that little-endian is convenient in mixing sizes. If you want the low 16 bits of a 32 bit number, the address is the same. I don't agree with this at all. It makes it easy to believe a program is right when it is really wrong. The 2 usually comes out in the constant part of the address, and doesn't cost anything. Here again I prefer big-endian. IBM chose big-endian for the 360, maybe the beginning of byte addressable machines, or at least popularizing them. DEC chose little-endian for VAX, though DEC has some very unusual formats, including the middle-endian floating point formats. Some history from PDP-11 is still left in there. Anyone know what the 4004 did? The 8008 was the beginning of 8 bit microprocessors. -- glenArticle: 13185
In article <72tetm$eki$1@news.seed.net.tw>, "John Huang" <hungi@tpts4.seed.net.tw> wrote: > Hi: > I have problem with WorkView Office 7.3 > when I use IntelliFlow, I got an Error Message > > vdesman-W-1601 : Unable to setup Altera environment > > Please help me, this is urgent > > John Huang > > John, Have you installed Max+plus II correctly and set the right variables ? Here's the text from on-line help... vdesman-W-1601 Message: Unable to set up Altera environment. Cause: The data directories required by IntelliFlow could not be located. Solution: Set the environment variable ALT_HOME to the directory of the Max+PlusII installation. For example, set ALT_HOME=c:\maxplus2. If this does not work, make sure that a full installation of Max+PlusII was performed. Hope this helps... Balaji. -- -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 13186
Try: http://www.optimagic.com/faq.html In article <36504443.C86FABF7@netas.com.tr>, Utku Ozcan <ozcan@netas.com.tr> wrote: > Steven K. Knapp wrote: > > > > You can find some tutorial information via The Programmable Logic Jump > > Station at http://www.optimagic.com/tutorial.html. > > this link doesn't work > > utku > > > > > Also, you may want to check out The Programmable Logic Bookstore at > > http://www.optimagic.com/books.html#VHDL. > > > > ----------------------------------------------------------- > > Steven K. Knapp > > OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" > > E-mail: sknapp@optimagic.com > > Web: http://www.optimagic.com > > ----------------------------------------------------------- > > > > ovilup wrote in message <01be0d93$78946fa0$4162e2c1@timteh.dnttm.ro>... > > >Dear all, > > > > > >I am looking for a good documentation on programming FPGA's and > > >ASIC's in VHDL. I have good aknowledges of VHDL, and I intend to learn > > >more about FPGA's and ASIC's. > > > > > >Thank you. > > > > -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 13187
Thanks one and all. I received several suggestions and they were enough to get me off dead center. Once you know the answer, it's obvious. I've now got my fifo running in a test bench and am just tweaking it to get the exact operation that I want. Thanks again, -Jim James LaLone wrote: > > Can someone shed light on building a fifo that can be synthesized? > The pointers, and ram, are no problem. What I'm having problems with > are the flags. Of course, the fifo that I want to build have > asynchronous read and write clocks. > I've looked over Xilinx applications XAPP051 and XAPP131, but they still > leave me with some implementation questions. > > Thanks in advance, > -JimArticle: 13188
Ray Andraka wrote in message <3652DA19.BD7F31CE@ids.net>... >Not so smooth there Johnny, > >You don't need storage for N+1 words for an N deep fifo. Read=Write means either >empty or full. The direction this condition was entered from differentiates the >two conditions. This uses an extra flip-flop in the control logic, but has the And what might you clock it with? That little flipflop is the problem. Because the two interfaces are asynchronous AND the flags must be valid AT ALL TIMES, there is really no good safe way to know what the last op was. Have you tried this, or are you just speculating? It's a deceptive problem. I've revisited that extra flipflop several times, and for truly Asynchronous FIFOs, the cleanest approach I've found is just to take the hit on the extra word and flag logic for the guarantee of asynchronicity (wasn't that a Police album? :-) ). For a custom CMOS FIFO I designed, I did come up with a circuit based on SR latches and an EQUAL signal to generate the flags, but that was far from synthesizable. Again, this is for small FIFOs (tens of words); for larger FIFOs, use a synchronous controller for a RAM in the middle, and use small asynchronous FIFOs on the front and back. If you can synchronize one port to the internal sync. FIFO, then bonus! I'll try to get a copy of my code from work and email it to you. If you have a better solution, then I would certainly like to see it (and use it!). Thanks, JohnArticle: 13189
I am looking for a reasonable cost schematic capture programme that is good at capturing VHDL designs. Must be able to generate symbols from VHDL code, push into the source etc. Something like Altera's tool but where one doesn't need to go through a compile stage to extract a netlist for VHDL simulation with Modelsim etc. Generating a structural VHDL netlist form the hierarchical "block" design is thus required. Can ALDEC do this?Article: 13190
That flip flop doesn't have to be set/reset on the transition to the equal state. It can be set/reset based on a gross comparison of the read and write counters. The trick is if the fifo is more than half full, it will be full when the pointers become equal unless it first becomes less than half full and vice-versa. Where I work in schematics, I don't have a synthesizable version of this. Johnny Smooth wrote: > Ray Andraka wrote in message <3652DA19.BD7F31CE@ids.net>... > >Not so smooth there Johnny, > > > >You don't need storage for N+1 words for an N deep fifo. Read=Write means > either > >empty or full. The direction this condition was entered from differentiates > the > >two conditions. This uses an extra flip-flop in the control logic, but has the > > And what might you clock it with? That little flipflop is the problem. Because > the > two interfaces are asynchronous AND the flags must be valid AT ALL TIMES, > there is really no good safe way to know what the last op was. Have you tried > this, > or are you just speculating? It's a deceptive problem. I've revisited that > extra flipflop > several times, and for truly Asynchronous FIFOs, the cleanest approach I've > found is just to take the hit on the extra word and flag logic for the guarantee > of > asynchronicity (wasn't that a Police album? :-) ). For a custom CMOS FIFO I > designed, > I did come up with a circuit based on SR latches and an EQUAL signal to generate > the flags, but that was far from synthesizable. Again, this is for small > FIFOs (tens of words); for larger FIFOs, use a synchronous controller for a > RAM in the middle, and use small asynchronous FIFOs on the front and back. > If you can synchronize one port to the internal sync. FIFO, then bonus! > > I'll try to get a copy of my code from work and email it to you. If you have a > better > solution, then I would certainly like to see it (and use it!). > > Thanks, > John -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 13191
Hello all,
I would like to know a good usenet group for VLSI.
Thank you in advance...
-Sandra-
-----------== Posted via Deja News, The Discussion Network ==----------
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Article: 13192Hi, I am looking for sources of information on Content Addressable Memorys. In particular, I want to find up to date details and specifications of CAM chip suppliers and CAM boards. I would be extremely grateful if anyone was able to offer me advice or give me pointers to information about CAMs and CAM suppliers. Thanks! Alistair -- ________________________________________________ Oxford University Computing Laboratory Alistair.McEwan@comlab.ox.ac.uk +44 1865 273846 http://www.comlab.ox.ac.uk/oucl/people/alistair.mcewan.html ------------------------------------------------Article: 13193
In article <7306ev$qmd$1@nnrp01.iafrica.com>, Anthony Ellis - LogicWorks <aelogic@iafrica.com> writes >I am looking for a reasonable cost schematic capture programme that is good >at capturing VHDL designs. >Must be able to generate symbols from VHDL code, push into the source etc. >Something like Altera's tool but where one doesn't need to go through a >compile stage to extract a netlist for >VHDL simulation with Modelsim etc. > >Generating a structural VHDL netlist form the hierarchical "block" design is >thus required. >Can ALDEC do this? > > You could try GEMA, email me on steveb@vizef.com if you would like more info.Article: 13194
Hi !Have a look at the new APEX 20K family from Altera. It will support CAM - memorys.They don't have any app notes and such yet, since the parts will be available in Q1 99.Best RegardsHåkan -**** Posted from Supernews, Discussions Start Here(tm) ****- http://www.supernews.com/ - Host to the the World's Discussions & UsenetArticle: 13195
Hi, I am looking for information on connecting a Xilinx FPGA to a TMS320C40 or C60 DSP. Are there any publications, papers, websites ... ? Thanks! Stefan stede@sbox.tu-graz.ac.atArticle: 13196
On 19 Nov 1998 08:26:03 +0000, Alistair McEwan <aam@pierrot.comlab> wrote: > > >Hi, > >I am looking for sources of information on Content Addressable >Memorys. In particular, I want to find up to date details and >specifications of CAM chip suppliers and CAM boards. > Search for MUSIC Semiconductors. - BrianArticle: 13197
rolavine@aol.com (Rolavine) wrote: >I just got Xilinx foundation base, and am wondering if I can develop complete >designs just using the built in version of Able? > >I am a one man band electronic design company, and not a full time FPGA >designer. > >I have been using Xilinx with an older Orcad dos interface. > >Thanks for any help. Yes, you can. I've done it many times. The only disappointment about XABEL is that Xilinx has stopped furinshing much documentation for it. I've been using XABEL for years, and also have it with the Synario package, so I can handle it pretty well, but it concerns me that newcomers will have trouble using it. It appears to me that Xilinx furnishing Xabel with the Foundation base system is just a "check in the box" to say that they support low cost design entry, and is not a serious effort at supporting a low cost design entry methodology. (The opinoins are mine). Now, if you want to talk VHDL, and spend lots of bucks, they will support you real well. GACK! Tim Olmstead email : timolmst@cyberramp.net Visit the unofficial CP/M web site. MAIN SITE AT : http://cws86.kyamk.fi/mirrors/cpm PRIMARY US MIRROR AT : http://www.mathcs.emory.edu/~cfs/cpm SECONDARY US MIRROR AT : http://CPM.INTERFUN.NETArticle: 13198
Austin wrote: > Does that work for NT????? For Windows NT, you can get a tool called "Disk Probe" which is part of the NT resource kit. It will allow you to edit low-level disk data including the serial number. This may also work for Win95/98, but I haven't tried it.Article: 13199
Hello,
FPGA to ASIC conversion. I had to work on a two FPGAs to ASIC convecsion.
I know that there's conversion programs. But If you like to do FPGA to ASIC
conversion based on VHDL-synthesis. You can do that. To synplify the
conversion for timing purpose, everything should be made synchronous.
The timing issues FPGA to ASIC conversion:
For hold time: clk to Q delay of FFs should be larger that clock skew.
For setup: there should be no problem since ASIC is faster than FPGA.
input/output: Setup and hold time. This can be synplified by using FFs on
inputs and outputs. And you should compare
setup/hold
on I/Os.
Also You can run functional vectors to verify your system requirement. This
my own testimony about FPGA to ASIC conversions.
Fredj Rouatbi
NSI communications
NOSPAM__frouatbi@nsicomm.com
Bill Pringlemeir wrote in message ...
>This is an excellent example. Currently we have a line of products. Some
>of the logic is very similar between devices; others (the screen drivers)
>are not. We have an ASIC for one and a XILINX hard wire device for
another.
>
>If you had an integrated ASIC/FPGA it may have been more appropriate. This
>would be a cost situation. The reason we went with hard wire was the NRE.
>
>Also, as several people pointed out being able to update FIR, IIR, state
>machine code etc is an advantage.
>
>Bill
>
>>>>>> "null" == null <null@I.Hate.Spam> writes:
>
> null> Considering that many uC applications end up using
> null> programmible logic 'glue' to interface the CPU to whatever
> null> it's supposed to be controlling, a combination CPU/FPGA
> null> would seem ideal for a wide variety of embedded controllers.
>
>--
>Noah's unknown brother - Made arc full of aquariums
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