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suggestion: use JTAG configuration for flex10k device. maxplus2 can build one big file for jtag configuration including chips of other manufactures (which will be put into bypass mode). gs Kamal Patel wrote in message <365AE442.95EFBC17@wam.umd.edu>... >I have a flex10k part on the end of a daisy chain with two xilinx parts. > >I need information that is available on supporting multiple fpga files. >I need to add an Altera programming file to the end of the Xilinx files. >I >can use a file formatter tool for the xilinx config., but not for the >altera. >Therefore, I need to know what information needs to be added to the >programming file. Anyone have any experience here???????? >PLEASE HELP!!! >Article: 13326
Please describe your critical path that needs to be met. i am confused about your description and not familiar with Mot processor specs. surely any 5ns cpld could meet your spec if you need to: clk flop in device, then feed combinatorial logic out of device thru tristate enable.. Check out Max7064AE-5 from Altera. Steve wrote in message <8rH62.954$AG1.871@typhoon.mbnet.mb.ca>... >I'm interfacing to a Motorola MPC 860 @50Mhz. I need to provide an >acknowledge signal in <10ns after the Clock. To do this my PLD/FPGA >needs to have a (Clk-Q + comb delay + tristate enable) < 10ns. > >So far I haven't found a CPLD to do it. What small FPGA's have the best >crack at it??? ... or prove me wrong on the CPLD issue? > >So far my only practical solution is an XCS05XL-4. > > >Comments? > >Steve > >Article: 13327
F1.3 / Student Ed. schematic capture buses are quite adequate for processor datapaths, although perhaps not as nice as Viewlogic. Tips: When you first draw a bus, or when you double-click the middle of a un-named bus, you can label it. In F1.3 this label must be a simple name such as "foo[15:0]". When you double-click a macro's bus pin (e.g. a[16:0]), you get a "bus pin connection" dialog and may enter a complex bus name like "e,f,g,h,foo[7:4],x,y,foo[1:0],z". This ties corresponding bus wires to port wires, e.g.: a[16] <- e; a[15] <- f; ... a[12] <- foo[7]; a[11] <- foo[6]; ... a[0] <- z; If I recall correctly, using F1.5, the bus itself can be labeled with an editable complex bus name. Therefore, one answer for Simon's bus problem could be to create a BUF8 macro from 8 BUFs, with input pin I[7:0] and output pin O[7:0]; then instantiate one; then draw no-name buses on each of I and O; then double-click the I pin and enter the label "A[4:7],B[0:3]" or "B[0:3],A[4:7]", or whatever is desired; then double-click on the O pin and enter "C[0:7]" or what-have-you. As someone mentioned, BUFs are almost always optimized away. Jan GrayArticle: 13328
Hi, I'm considering using one of their DL5000 series of FPGAs in a project that I'm working on. I was just curious to know if anyone had used them and if they had what sort of performance did they get and what was their general experience. As an aside the project I'm working on will need to run at 155Mhz and has mixed ECL / TTL IO. If anyone has suggestions for other devices that meet these speed and IO requirements that would be appreciated too. thanks Peter CobbArticle: 13329
Steve wrote: > > I'm interfacing to a Motorola MPC 860 @50Mhz. I need to provide an > acknowledge signal in <10ns after the Clock. To do this my PLD/FPGA > needs to have a (Clk-Q + comb delay + tristate enable) < 10ns. > > So far I haven't found a CPLD to do it. What small FPGA's have the best > crack at it??? ... or prove me wrong on the CPLD issue? > > So far my only practical solution is an XCS05XL-4. > > Comments? > > Steve I also am not completely sure of the path you are describing. It sounds like : Clk ---> FF ---> Logic ---> Tristate ---> Output where the FF, logic and tristate are all within the CPLD. If so, have you considered trying to put the logic on the other side of the FF? This should reduce your delay considerably. On the other hand you may be describing signals which come out of the CPU which are clock edge referenced. These signals have to be gated together and used for the tristate enable. In this case the only solution would be a faster part. Is any of this correct for your application? -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 13330
Hi, I need help hooking up my parallel cable III to a Spartan XCS10 device. Here is what I haveso far: Parallel Cable Spartan Pin 1. VCC all vcc pins 2. GND all gnd pins 3. CCLK cclk 4. D/P done 5. DIN din 6. PROG program' Is that all I need? Thanks. Jamie MorkenArticle: 13331
With Altera's Max7064AE-5, you can get about 7.5 - 8ns from Clk->Q->tri-state in simulation. I am not sure if how long your comb logic is. Good luck. ----------------------- Louis Zhang lzhang@eecg.toronto.edu > Check out Max7064AE-5 from Altera.Article: 13332
Complaints: 1. If I recall correctly, XACT 5.2 could map 2 FMAPs + 1 (independent 3-input) HMAP driving a FDCE, RLOC constrained, into a single CLB. Today a tech support call confirmed that M1.x does not support this. In my current XC4005E design, I have had to scrap four "free" columns of HMAP 2-1 multiplexor+registers, sharing CLBs with other FMAP logic, and replace them with two expensive columns of FMAP ones. The absence of M1 map support for independent 3-input HMAPs renders my datapath 28% larger than otherwise necessary and reduces remaining area for other stuff by 33%. (I know, I could make four different hard macros using EPIC...no thank you.) 2. EPIC can't print!? Praise: 1. My implementation times now are only a few minutes, ten or twenty times faster than in the "good old days". Thanks Intel, Xilinx, and Microsoft. 2. M1, just as XACT before it, provides convenient, explicit control over technology mapping and placement (FMAPs, RLOCs), and timing driven optimization, and, for now, it still accepts XNF! Count your blessings. Let us give thanks. Jan GrayArticle: 13333
Raanan wrote: > Hello. > I'm a student and learn VHDL. > Does anybody has an idea where to find a VHDL design of a synchronous > SRAM or any other ALTERA MAX+plus 2 compilable design ??? > > thanks in advance > > (-) > Raanan > -- > Surf Usenet at home, on the road, and by email -- always at Talkway. > http://www.talkway.com You can use "genmem" with DOS. It is an Altera tool provide with Maxplux2. Michel Le Mer Gerpi sa Alma city 3, rue Bosphore 35000 Rennes FranceArticle: 13334
Does anyone know if the detailed format of the configuration datastream fo Xilinx 4000 series parts is available freely anywhere? We are looking at new ways of defining configurations from a new kind of high level description and hence can't use existing tools (since they do the bit we are interested in for us!) -- Richard Cant Senior Lecturer Simulation and Modelling Research Group Department of Computing The Nottingham Trent UniversityArticle: 13335
Steve escribió: > > Francisco José Blasco Abril wrote in message > <365BD900.3DA5707E@patan.uv.es>... > >It's not necesary that the FPGA must be so fastest. > >I could do this in a EPF8820A-3 with a delayed clock. You are using a > >20ns clock period. Well, if you insert a 15ns delay, you can use this > >delayed clock for the output registers. > > Thanks for your suggestion, but I always prefer to use delays as a last To you. > resort, > especially with programmable logic. Delays require you to rely on minimum > prop > delays, and most vendors guarantee max's NOT mins. Furthermore if you buy Two things: I based the delays in a simulation after a compilation. I know it's a floating design point, but it's the only alternative when you buyed the device yet. The OUTPUT pins have a min delay. If you put a register into the output pin, you can get a static delay. You must feedback this output with an input pin that you can use as a clock register. Well, I know thar are a lot of "if ...", but it's not the worst solution. > a part in a slower speed bin to "guarantee" a min, you have no guarantee > that slower...yes...it runs up to 50MHz with a 10-12ns output delay...but I want a 7ns output delay... I know this is not a 400MHz Penti*m II... > you aren't getting a faster speed bin part because they all yielded so well. > Also sometimes vendors force you into newer technology parts which are > compatible only faster because they did a die shrink. > > I think I can get what I need without delays. I just want to make sure I > don't miss any options. > > Thanks again, Not at all. It's nothing. > > Steve PacoArticle: 13336
The Xilinx bitstream isn't publicly available- this has been the subject of much debate over the past years. However, you may be interested in something 'released' recently by Xilinx which offers a set of Java classes to reconfigure their devices- there's info on their web-site about it. There was also a talk about it given at SPIE Configurable computing- let me know if you want the details. Craig Slorach (craigs@elec.gla.ac.uk) Richard Cant wrote in message ... >Does anyone know if the detailed format of the configuration datastream >fo Xilinx 4000 series parts is available freely anywhere? > >We are looking at new ways of defining configurations from a new kind of >high level description and hence can't use existing tools (since they do >the bit we are interested in for us!) >-- >Richard Cant >Senior Lecturer >Simulation and Modelling Research Group >Department of Computing >The Nottingham Trent UniversityArticle: 13337
Altera also have a University program which offers a board- check their website for details- it's under 'PhD program' Craig Vito P. Errico wrote in message <73f37c$bhq$1@newsboy.fiber.net>... >I am doing a school project on FPGAs and became aware of a board that you >can add into your computer that contains FPGA technology as a programmable >chip that acts as a secondary processor, letting the CPU do all of the >system management while the FPGA board completes the specialized task. Does >anyone have any information on FPGA add-in boards? > >Vito P. Errico > >Article: 13338
Ref: 623 PRINCIPAL DESIGN ENGINEER Bristol/ South Wales Region An outstanding opportunity for career development & to work at the leading edge of technology £35,000 - £42,000 + Car + Benefits Package Our Client manufactures, delivers and supports a range of telecommunications products. The PDE will play a leading role in the Electronic Product Group which is set to grow significantly. An excellent opportunity to learn, mentor and lead a small team of design engineers and provide specialist advice and support on a wide range of issues. Responsibilities: Be directly responsible to the Senior Engineering Manager for all engineering activities on nominated programmes. Influence and advise on direction of procurement, strategy, use of Cadence or other tools, be proactive on new projects coming online and new challenges, on training courses. Be involved with new projects from start to completion, participate in ideas and evaluation, creating solutions. Head up the application of leading edge communications technology to military fixed and mobile comms, develop the technical interfaces to ensure successful communication between different systems. Full responsibility for selection and implementation of design approach for varied communications equipment requirements & for resolution of all technical problems on these programmes. Formulate engineering strategy on component-level design for the business area Requirements analysis & definition as part of customer programmes and in-company purposes Team lead a small group of design engineers & direct supervision of permanent staff & contractors Undertake hands-on digital & analogue circuit design and development utilising CAE tools for design description synthesis & simulation. Provide EMC design & countermeasure expertise advising other engineers where necessary & guiding subordinate engineering staff Support design reviews of own and others work Maintain close liaison with Industrial Engineering, Manufacturing & Production Test departments Author & edit Technical & Project Documentation for customer use. Experience required: Electronic Engineering Degree (or related subject) or equivalent experience. Chartered Engineer status advantageous - not essential. Six years solid electronic design experience, including analogue & digital circuitry [75% digital, 25% analogue], in a telecommunications or similar environment, achieving Senior Engineer status. Experience of comprehensive use of CAE tools essential, (ideally CADENCE) Experience of military product design and supervisory experience advantageous Familiarity with Field Programmable Gate Array technology (preferably XILINX) is highly desirable Note: This is a hands on circuit design & development role & sound knowledge of digital design & analogue techniques is essential. Clearance required. Start asap. Please respond with interest & full CV FAO: Shena Parthab quoting REF: 623 InterManagement Group Bridgefoot House 159 High Street Huntingdon CAMBRIDGESHIRE United Kingdom PE18 6TF Tel: 01480-377000 Fax: 01480-377003/ 52201 EURONET@dial.pipex.comArticle: 13339
Sorry about the confusion over what I am trying to do. This is my
example for nBi (Burst inhibit), nTa (Transfer acknowledge is similar).
Rules: nBi must not be driven prior to sync signal nTs
but must be driven low in less then 10ns after clk
nBi must be driven high then tristated within 20ns of clk
nBi <= '0' WHEN BiOe='1' ELSE 'Z';
BiOe <= '1' WHEN nBiEn='0' OR (nCpCs='0' AND nBi='0') ELSE '0';
PROCESS(nRst, Clk) BEGIN IF nRst='0' THEN
nBiEn <= '1';
ELSIF Clk'EVENT AND Clk='1' THEN --Clk rising edge
IF (nCpCs='0' AND nTs='0' AND nBurst='0') THEN -- enable for Burst
attempt to this chip
nBiEn <= '0';
ELSE
nBiEn <= '1';
END IF;END IF;END PROCESS;
Steve
PS: according to Max+II 9.01 a 7064AE-5 takes 14.1ns. I tried to download
newer
timing info but I don't think I can get it without paying my support???
PPS: I think I have a solution using 2 I/O pins. One would be open
collector (as
suggested by the Lattice FAE), the other would be tristate (to drive
high at the end).
Article: 13340Steve - You've got a really weird feedback path here. You've got a 3st buffer with nBi as the output, ~BiOe as the input, and BiOe as the OE. This is o.k. except that BiOe is a funtion of nBi. Besides the fact that you can't do this in a PLD, it's not going to give you the behavior you want. If I understand your interface correctly then this might work: Call the nBi output 3st buffer TBUF with ports I, O, and OE. nBi <= '0' WHEN (nCpCs='0' AND nTs='0' AND nBurst='0') ELSE '1'; Then create registered version nBi (call it nBiR). TBUF.I = nBi; TBUF.OE = ~(nBi AND nBiR); The result of this: 1. At the beginning of the cycle nBi is low and the TBUF is enabled as soon as (nCpCs='0' AND nTs='0' AND nBurst='0') is true, which meets your first rule I think. 2. At the end of the cycle nBi is driven high when (nCpCs='0' AND nTs='0' AND nBurst='0') is false, but the TBUF is not turned off until after the next clock edge. This ensures nBi is driven high before tristating it and should meet your second rule. I may have missed something here but the point is that if you can get rid of the register delay in turning nBi on and driving it low then any fast PLD (except maybe Xilinx 9500 which having VERY slow OE times) should be able to meet your timing. Then use a register delay at the end of the cycle to delay turning off the buffer until after nBi has been driven high. Good luck. Bob S. Steve wrote: > > Sorry about the confusion over what I am trying to do. This is my > example for nBi (Burst inhibit), nTa (Transfer acknowledge is similar). > > Rules: nBi must not be driven prior to sync signal nTs > but must be driven low in less then 10ns after clk > nBi must be driven high then tristated within 20ns of clk > > nBi <= '0' WHEN BiOe='1' ELSE 'Z'; > BiOe <= '1' WHEN nBiEn='0' OR (nCpCs='0' AND nBi='0') ELSE '0'; > > PROCESS(nRst, Clk) BEGIN IF nRst='0' THEN > nBiEn <= '1'; > ELSIF Clk'EVENT AND Clk='1' THEN --Clk rising edge > IF (nCpCs='0' AND nTs='0' AND nBurst='0') THEN -- enable for Burst > attempt to this chip > nBiEn <= '0'; > ELSE > nBiEn <= '1'; > END IF;END IF;END PROCESS; > > Steve > > PS: according to Max+II 9.01 a 7064AE-5 takes 14.1ns. I tried to download > newer > timing info but I don't think I can get it without paying my support??? > > PPS: I think I have a solution using 2 I/O pins. One would be open > collector (as > suggested by the Lattice FAE), the other would be tristate (to drive > high at the end). -- --------------------------- real addr: rsefton_@_home.com (remove the underscores) ---------------------------Article: 13341
I think I'm going with the 2 pin solution but FYI
... you were right about the error.
Bob Sefton wrote in message <365D8558.A2072E4C@home.com>...
>Steve -
>
>You've got a really weird feedback path here. You've got a 3st
>buffer with nBi as the output, ~BiOe as the input, and BiOe as the
>OE. This is o.k. except that BiOe is a funtion of nBi. Besides the
>fact that you can't do this in a PLD, it's not going to give you
>the behavior you want.
You're right! In trying to get back to my original configuration for
posting
I made a typo. Sorry about that. It should have read:
nBi <= nBiEn WHEN BiOe='1' ELSE 'Z';
BiOe <= '1' WHEN nBiEn='0' OR (nCpCs='0' AND nBi='0') ELSE '0';
PROCESS(nRst, Clk) BEGIN IF nRst='0' THEN
nBiEn <= '1';
ELSIF Clk'EVENT AND Clk='1' THEN --Clk rising edge
IF (nCpCs='0' AND nTs='0' AND nBurst='0') THEN -- enable for Burst
nBiEn <= '0';
ELSE
nBiEn <= '1';
END IF;END IF;END PROCESS;
>
>If I understand your interface correctly then this might work:
>
>Call the nBi output 3st buffer TBUF with ports I, O, and OE.
>
>nBi <= '0' WHEN (nCpCs='0' AND nTs='0' AND nBurst='0') ELSE '1';
The problem with this is Motorola requires the 3s enable to be sync, ie
I can't enable until after I sample the above condition.
>
>Then create registered version nBi (call it nBiR).
>
>TBUF.I = nBi;
>TBUF.OE = ~(nBi AND nBiR);
I need to be 3state in the same cycle (20 ns) as I drive high. Here I was
trying to cheat a bit by tri-stating after I detected a 1 on the pin.
Alternatively
I could just delay the disable as long as I didn't exceed the 20ns limit.
>
>The result of this:
>
>1. At the beginning of the cycle nBi is low and the TBUF is
>enabled as soon as (nCpCs='0' AND nTs='0' AND nBurst='0') is true,
>which meets your first rule I think.
This may cause contention with previous Slave although this is
probably more of an issue with the other signal .. nTa.
>2. At the end of the cycle nBi is driven high when (nCpCs='0' AND
>nTs='0' AND nBurst='0') is false, but the TBUF is not turned off
>until after the next clock edge. This ensures nBi is driven high
>before tristating it and should meet your second rule.
I think this would turn off too late. Sorry I tried to be as
clear as I could about the requirements, but it's obviously
not the simiple to explain
>
>I may have missed something here but the point is that if you can
>get rid of the register delay in turning nBi on and driving it low
>then any fast PLD (except maybe Xilinx 9500 which having VERY slow
>OE times) should be able to meet your timing. Then use a register
>delay at the end of the cycle to delay turning off the buffer
>until after nBi has been driven high.
>
>Good luck.
>
>Bob S.
Article: 13342I am considering using an FPGA for implementing a PCI target only design, (32 bit, 33MHz). Has anyone used the Actel PCI core together with the SX family of FPGA's for this purpose? Any comments would be most appreciated. Thanks, GraemeArticle: 13343
Have you checked with Actel's new products SX family? The clock-to-output is 4ns(pin-to-pin) and output enable time is less than 2ns. The 54SX08-2 will be the fastest and smallest devices with very attractive price. Thanks Francisco José Blasco Abril ÀÌ(°¡) <365D25C3.4E90131E@patan.uv.es> ¸Þ½ÃÁö¿¡¼ ÀÛ¼ºÇÏ¿´½À´Ï´Ù... >Steve escribió: >> >> Francisco José Blasco Abril wrote in message >> <365BD900.3DA5707E@patan.uv.es>... >> >It's not necesary that the FPGA must be so fastest. >> >I could do this in a EPF8820A-3 with a delayed clock. You are using a >> >20ns clock period. Well, if you insert a 15ns delay, you can use this >> >delayed clock for the output registers. >> >> Thanks for your suggestion, but I always prefer to use delays as a last > >To you. > >> resort, >> especially with programmable logic. Delays require you to rely on minimum >> prop >> delays, and most vendors guarantee max's NOT mins. Furthermore if you buy > >Two things: >I based the delays in a simulation after a compilation. I know it's a >floating design point, but it's the only alternative when you buyed the >device yet. >The OUTPUT pins have a min delay. If you put a register into the output >pin, you can get a static delay. You must feedback this output with an >input pin that you can use as a clock register. >Well, I know thar are a lot of "if ...", but it's not the worst >solution. > >> a part in a slower speed bin to "guarantee" a min, you have no guarantee >> that > >slower...yes...it runs up to 50MHz with a 10-12ns output delay...but I >want a 7ns output delay... >I know this is not a 400MHz Penti*m II... > >> you aren't getting a faster speed bin part because they all yielded so well. >> Also sometimes vendors force you into newer technology parts which are >> compatible only faster because they did a die shrink. >> >> I think I can get what I need without delays. I just want to make sure I >> don't miss any options. >> >> Thanks again, >Not at all. It's nothing. >> >> Steve >PacoArticle: 13344
ear madam/sir, I am a user of the Xilinx's Foundation Series V6.01 with VHDL. I¡¡ have a problem of my designing that I verified my designing to get a warning called Bus Conflict. I tested a dozen cases in which I¡¡ can't get 2 answers and 10 corrected answers. I can't find how to use the debugging to solve the problems. Could you tell me how to do it? I look forward to getting your answer. Regards Wodi MunArticle: 13345
Hi Simon... I have never used XSE, but you can either call the second bus a[4..7],b[0..3] or just AND2 the a and b busses with 1, and let the logic optimizer remove the redundant AND. Eric msimon@tefbbs.com wrote in article <3657cf9d.359868@news.megsinet.net>... > I am working with the Xilinx Student Edition. > > I am using schematic capture. > > I have two input busses A[0..7] and B[0..7] > > I want to take A[4..7] and B[0..3] and make C[0..7]. > > How do I do this? > > Simon > > >Article: 13346
Dynatext documents can be exported to SGML, I have been looking for an SGML to HTML converter but have only found very expensive document management suites or very cryptic command line conversion tools for unix, My temporary (only?) solution is to print the Dynatext documents to a postscript file and use the Ghostscript command line utility ps2pdf to convert to the pdf format, this still beats dynatext SGML, also there are some good PDF utilities at download.com (RTSDuplex 1.04) that you can use to print to both sides of sheet and also extract individual sheets. I use ghostscript on Redhat Linux 5.1, the version with the RH distribution is downlevel and needs to be upgraded to run ps2pdf, you can get all versions at: http://www.cs.wisc.edu/~ghost/aladdin/get550.html In case you are not familiar with Ghostscript, it is a bunch of utilities for manipulating postscript docs along with a viewer (Ghostview), there is more info at: http://www.cs.wisc.edu/~ghost/ You can find the PDF utilities by going to Download.com and searching on "PDF" R. Stirling Wolf Minka Design Inc. -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own performance tradeoff. All Xilinx cores are produced to ensure best overall system speed as opposed to a 'prep benchmark'. As for Altera's Place and Route advantage. Well that is water under the bridge. M1.5i is much faster than MPII, for all timing driven runs, and it does pretty well without 'timing driven'. As for Virtex. Well even I am staggered. 31 Tap 10 Bit Symmetrical Fir - Full precision ie no truncation or rounding. 130MHz sample rate in 10 Mins compile time on a 166MHz Pentium Laptop!!! I hope this helps... Dave Hawke, Xilinx Applications. Ken Coffman wrote in message <759dqv$utd$1@brokaw.wa.com>... >I don't consider Foundation tools to be usable. What is your desired design >entry method? Foundation might be okay for schematics, I wouldn't know >because I've never used a schematic to design an FPGA. The combination of >Synplicity Synplify or Exemplar Leonardo for Verilog or VHDL design with the >Xilinx Design Manager for place and route works very well. Altera has simple >silicon, so their software is correspondingly simple and easy, and works >very well. If you're looking for all-in-one vendor software that works well, >MAXPLUS2 is great. For silicon I'd say Altera works well for datapath type >functions (filters and other pipelined functions) and Xilinx works well for >more random and mixed logic. If you need to lock down your pins and create a >circuit board before the FPGA design is done, then you don't want to use >Altera. >glenn kubota wrote in message <364E13BF.5C4EB701@earthlink.net>... >>i've got a project where i'm looking at using CPLDs from either Altera >>or Xilinx. it looks like they both have chips that will fit the bill. >>my question, however, is what're the relative pros and cons of Xilinx >>Foundation vs. Altera Max Plus? what's easier to learn? what will serve >>me better in the future? >> >>thanks, >>glenn k. >> >> > >Article: 13347
This thought should be worrying not only XILINX shareholders, but also, - XILINX users, who have invested a lot of efforts and money into mastering XILINX tools. Why should we expect XILINX shutdown in the foreseeable future? 1) XILINX has started as successful innovative company and won essential part of the market. But that's in the past ... Recent history of XILINX is a sequence of disastrous failures to deliver satisfactory quality at reasonable price. Remind heart-breaking stories with 8000, 6200, 5200 series! Lacking new ideas, XILINX is trying to sell their old 4000 series wrapped into Spartan envelope. And now Virtex becomes too late answer on Altera designs. 2) XILINX applies tremendous efforts to reduce the price and ... the quality of its development tools. It was reported by many customers in this particular newsgroup that XILINX Foundation is worse than XACT, and each subsequent version of Foundation is worse than previous. Currently the quality of development tools is so bad that XILINX almost gave up any attempts to fix endless stream of bugs. The bugs are just stored until next version of Foundation : 3) XILINX support service became some sort of psychoanalyst to keep users calm and to avoid bodily damage (and chip damage) caused by desperate customers. XILINX is afraid to reveal an obvious thing: there is no support for ALDEC software that constitutes the principal part of Foundation (design flow, schematics and simulation). 4) And now the last news: MARSHALL does not sell XILINX chips any more. Obviously, they are feeling where the things go. Good bye XILINX ... *************Article: 13348
Or is it: http://www.optimagic.com/tutorials.html ? Steven K. Knapp wrote: > You can find some tutorial information via The Programmable Logic Jump > Station at http://www.optimagic.com/tutorial.html. > > Also, you may want to check out The Programmable Logic Bookstore at > http://www.optimagic.com/books.html#VHDL. > > ----------------------------------------------------------- > Steven K. Knapp > OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" > E-mail: sknapp@optimagic.com > Web: http://www.optimagic.com > ----------------------------------------------------------- > > ovilup wrote in message <01be0d93$78946fa0$4162e2c1@timteh.dnttm.ro>... > >Dear all, > > > >I am looking for a good documentation on programming FPGA's and > >ASIC's in VHDL. I have good aknowledges of VHDL, and I intend to learn > >more about FPGA's and ASIC's. > > > >Thank you. > >Article: 13349
--------------89BCC5ED387C450BEB03E686 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit I am sorry. I was very late to the party with the corrected web-site information. I thought I looked at all the response Senders to find the correction from Steven, but I was wrong. Dumb dumb dumb... By the way, many FPGA vendors "sell" training in VHDL as applied to their products, through the distributers. I say "sell" since the $100 price is often up to the sales rep and includes lunch. Cypress (at least) has a nice book on VHDL for Programmable Logic which the sale rep gave to the employees at my current work-place. Of course if cost isn't an obstacle, there are lots of nice choices at Amazon. I'll give a review in a few weeks. John Harrop wrote: > Or is it: > http://www.optimagic.com/tutorials.html > ? > > Steven K. Knapp wrote: > > > You can find some tutorial information via The Programmable Logic Jump > > Station at http://www.optimagic.com/tutorial.html. > > > > Also, you may want to check out The Programmable Logic Bookstore at > > http://www.optimagic.com/books.html#VHDL. > > > > ----------------------------------------------------------- > > Steven K. Knapp > > OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" > > E-mail: sknapp@optimagic.com > > Web: http://www.optimagic.com > > ----------------------------------------------------------- > > > > ovilup wrote in message <01be0d93$78946fa0$4162e2c1@timteh.dnttm.ro>... > > >Dear all, > > > > > >I am looking for a good documentation on programming FPGA's and > > >ASIC's in VHDL. I have good aknowledges of VHDL, and I intend to learn > > >more about FPGA's and ASIC's. > > > > > >Thank you. > > > -- To reply, take out the trash. --------------89BCC5ED387C450BEB03E686 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> I am sorry. I was very late to the party with the corrected web-site information. I thought I looked at all the response Senders to find the correction from Steven, but I was wrong. Dumb dumb dumb... <P>By the way, many FPGA vendors "sell" training in VHDL as applied to their products, through the distributers. I say "sell" since the $100 price is often up to the sales rep and includes lunch. <P>Cypress (at least) has a nice book on <I>VHDL for Programmable Logic</I> which the sale rep gave to the employees at my current work-place. Of course if cost isn't an obstacle, there are lots of nice choices at Amazon. I'll give a review in a few weeks. <P>John Harrop wrote: <BLOCKQUOTE TYPE=CITE>Or is it: <BR><A HREF="http://www.optimagic.com/tutorials.html">http://www.optimagic.com/tutorials.html</A> <BR>? <P>Steven K. Knapp wrote: <P>> You can find some tutorial information via The Programmable Logic Jump <BR>> Station at <A HREF="http://www.optimagic.com/tutorial.html">http://www.optimagic.com/tutorial.html</A>. <BR>> <BR>> Also, you may want to check out The Programmable Logic Bookstore at <BR>> <A HREF="http://www.optimagic.com/books.html#VHDL">http://www.optimagic.com/books.html#VHDL</A>. <BR>> <BR>> ----------------------------------------------------------- <BR>> Steven K. Knapp <BR>> OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" <BR>> E-mail: sknapp@optimagic.com <BR>> Web: <A HREF="http://www.optimagic.com">http://www.optimagic.com</A> <BR>> ----------------------------------------------------------- <BR>> <BR>> ovilup wrote in message <01be0d93$78946fa0$4162e2c1@timteh.dnttm.ro>... <BR>> >Dear all, <BR>> > <BR>> >I am looking for a good documentation on programming FPGA's and <BR>> >ASIC's in VHDL. I have good aknowledges of VHDL, and I intend to learn <BR>> >more about FPGA's and ASIC's. <BR>> > <BR>> >Thank you. <BR>> ></BLOCKQUOTE> <P>-- <BR>To reply, take out the trash. <BR> </HTML> --------------89BCC5ED387C450BEB03E686--
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