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Even you could put an FPGA on your ASIC, what tools would you use for place
& route of the non-standard FPGA?
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 12951I would like to add something to this thread. Has anyone noticed that Eq. 8.7 in Howard Johnson's book on page 273 is wrong? This bothers me since this equation is used for the derivation of the bypass cap value. -ArrigoArticle: 12952
Does anybody know of published benchmarks concerning the results produced by various FPGA HDL compilers? I have downloaded and tried two of the tools but I would like to see additional data before deciding which to purchase. regards Jerry EnglishArticle: 12953
Anybody know if Alrera's PCIT1 PCI target core can be used in a EPF10K100A? Thanks GregArticle: 12954
Check out www.triscend.comArticle: 12955
What is the best way to determine the post optimization CLB count for the macros I am generating in VHDL and the State Machine editor? I realize that these macros are packed with with other logic to share CLBs, but is there a way to estimate the size of the individual macros using Xilinx foundation 1.5 ThanksArticle: 12956
My question is: why do you want to put an FPGA architecture in your ASIC? It definitely is possible (check out www.triscend.com for an FPGA/microcontroller/memory in one device, or http://www.wsipsd.com/ for a different integrated microcontroller device with a CPLD type architecture included). Actually, Siemens reports the capability to integrate Gatefield's FPGA architecture in their ASICs, but I don't know of anyone who has experience with this solution! In article <71t4sl$naf$1@gaia.axis.se>, perz@nero.axis.se (Per Zander) wrote: > We have asked our ASIC vendor (one of the leading ones, not Lucent though) > about the possibility to add a FPGA block embedded in an ASIC. > They investigated it and came back with the answer that this couldn't > be done efficiently in a standard ASIC process. Perhaps we should have > asked more than one vendor ? > > Per Z. > > In article <36407DCE.12198013@lucent.com>, Maxim Golov <mgolov@lucent.com> writes: > > Peter, > > > > I agree with your point, but I was looking at the issue from > > the processor side ;) > > > > (Seriously) I could utilize some built-in flexibility in the processor > > if it was available, e.g. CRC calculation, counters, etc... > > Purely for software use, so processor would be the only > > "client". Sometimes it does not justify adding FPGA to the board, > > and ASIC appears to be difficult to change, especially in the late > > stage of the project. > > > > But maybe we could add FPGA to the ASIC? > > > > BTW, if you know a good overview on FPGA technology, I will appreciate > > a link - my background is mainly in software. > > > > Maxim > -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12957
I don't understand what the big deal is here. If you are looking for small scale configurability in an ASIC one can make a lookup table even using regular DFFs and other standard cells. Or you can even design a new cell which has the capability similar to a macro in any sram based FPGA and instantiate it in your design. Of course this will be more time consuming and starts becoming full custom but it is certainly doable. An ASIC process is a lot more flexible than any FPGA. wluka@hotmail.com wrote: >My question is: why do you want to put an FPGA architecture in your ASIC? > >It definitely is possible (check out www.triscend.com for an >FPGA/microcontroller/memory in one device, or http://www.wsipsd.com/ for a >different integrated microcontroller device with a CPLD type architecture >included). > >Actually, Siemens reports the capability to integrate Gatefield's FPGA >architecture in their ASICs, but I don't know of anyone who has experience >with this solution! muzo WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net>Article: 12958
In article <909179145snz@NOTtile.demon.co.uk>, Simon@NOTtile.demon.co.uk wrote: > Could the person at Xilinx who put their documentation in DynaText > format please be put up against the wall. PDF has many faults, > but at least you can > > read it without fancy installation programs > read it on multiple platforms > copy an important file to floppy > see the pictures in the correct places > ... > > Meanwhile, I have just installed DynaText three times, carefully rebooting > each time, and the darned program still refuses to read books on the CD > or on the hard disk. The contents list is OK, then it puts up a message > box with "cannot open footle". > > Does anyone have any ideas on how to fix this? > > Many thanks, > Simon > I had the same problem on an NT box although mine would read from the CD, oddly enough it works fine on other Win95/98/NT boxes in my lab. I have not finished hacking away at it yet but I understand that the Dynatext docs can be exported as SGML which can then be converted to HTML, there are some pricey tools out there for doing this and also some freeware linux tools. Dynatext is most certainly a pain, many times while documenting my designs it would have been nice to link to certain pages but of course I cannot. Considering that Xilinx uses a proprietary documentation viewer, they plan to drop schematic support and the fact that they have killed two chips out from under me after hyping them as their "latest and greatest" (5215, XC4000EX) I am starting to believe that Xilinx has become the Microsoft of FPGA companies. -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12959
It makes sense that you could do the below. Have you done it? Care to share any examples? What about when you start needing 16-bit Adders and Counters - does the LUTapproach get cumbersome? I suppose it can work since that's all that a XILINX is, but then, when I'm doing a XILINX, I have synthesis - if I do this TODAY in my ASIC, I'll not have that luxury. For more than just a few logic equations and terms, it'd be *nice* to somehow use Synthesis (it'd be neat if you could somehow make these macros into a Synopsys library cell and actually synthesize to it!) and not have to hand-craft every single configuration bit. Lacking good "Place & Route" tools, would it be better to have more complex, coarse macros that would be potentially closer to a more human intuitive level? Maybe the trick is; to pick an appropriate fine vs. coarse grain macro based on your application and tools (or lack thereof). tom coonan Scientific Atlanta tcoonan@mindspring.com >I don't understand what the big deal is here. If you are looking for small scale >configurability in an ASIC one can make a lookup table even using regular DFFs >and other standard cells. Or you can even design a new cell which has the >capability similar to a macro in any sram based FPGA and instantiate it in your >design. Of course this will be more time consuming and starts becoming full >custom but it is certainly doable. An ASIC process is a lot more flexible than >any FPGA. > >wluka@hotmail.com wrote: > >>My question is: why do you want to put an FPGA architecture in your ASIC? >> >>It definitely is possible (check out www.triscend.com for an >>FPGA/microcontroller/memory in one device, or http://www.wsipsd.com/ for a >>different integrated microcontroller device with a CPLD type architecture >>included). >> >>Actually, Siemens reports the capability to integrate Gatefield's FPGA >>architecture in their ASICs, but I don't know of anyone who has experience >>with this solution! > >muzo > >WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net>Article: 12960
Does anyone have any information on interfacing a Xilinx FPGA to a VGA
monitor (what about SVGA?)? I am interested in any schematics, articles, or
code that might be available. I would greatly appreciate any assistance.
Thanks in advance,
-EKC
if responding by e-mail, remove 'XYZ' string from address
Article: 12961tcoonan@mindspring.com (Thomas A. Coonan) wrote: >It makes sense that you could do the below. Have you done it? >Care to share any examples? no I have not done it myself so sorry no examples or benchmarks >TODAY in my ASIC, I'll not have that luxury. For more than just a few >logic equations and terms, it'd be *nice* to somehow use Synthesis >(it'd be neat if you could somehow make these macros into a Synopsys >library cell and actually synthesize to it!) and not have to >hand-craft every single configuration bit. but this beats the purpose, don't you think ? I think you are confusing the initial synthesis where you define a cell and put it into your asic and the Field Programming stage. If you know what features you want when you do the initial asic, you don't need any FP cells. You are right that you need some kind of synthesis and configuration tool to do the Field Programming part but I doubt that will be Synopsys or any asic layout tool. > Lacking good "Place & >Route" tools, would it be better to have more complex, coarse macros >that would be potentially closer to a more human intuitive level? >Maybe the trick is; to pick an appropriate fine vs. coarse grain macro >based on your application and tools (or lack thereof). What I am thinking is minimal programmability from this new cell. So you can define the FP Macro and program it by hand after you manufacture your asic. If you want half standard cell/half FP cells on a 400K gate asic then you need a lot more tool support for a much more complex FP macro and routing resources. At that point you're reaching to the point of designing a new FPGA architecture yourself and there are companies making a lot of money from that business already :-) muzo WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net>Article: 12962
On Fri, 06 Nov 1998 14:16:01 +0100, Le mer Michel <michel.lemer@ago.fr> wrote: >Yves Tchapda wrote: ..<snipped> >Thank you for your help. >In fact, I would like to use a xilinx 4062 device, which has not this >function. >The next generation, the virtex, will have it. But I do not know the >avaibility for the 50 000 gate chip. if you're desperate, you can use an XOR and a delay as a clock doubler, so you won't need a PLL. see p9-7 of xilinx's 1994 databook. you could also look up the "How to Double Clk Freq in the FPGA design" thread with dejanews (date 24/6/98), and check peter alfke's reply. evanArticle: 12963
This question has come a few times on this group & one suggestion someone made was to run some post P&R simulations and ``add up all the transitions''. Is there any simulator that can actually output the relevant data? Effectiively a list of all power consuming signal transitions.Article: 12964
jmccarty@sun1307.spd.dsccc.com (Mike McCarty) wrote: "so negative Moriority, so negative." >So I asked why I should use this particular uController. What is its >supposed forte? I'll put this aside as I'm speaking out of turn. > Why would anyone design a special purpose uController? > Why did this guy design *this* uController? >You have joined the list of such responders. For the later two questions and leaning way back to small C there is one aspect fo the exercise you missed. That it is an exercise. He is not selling the chip or the CPU design. It's available, free, and EDITABLE to something that may just be more useful for a given task. For the author he has the leg up when applyig for a job as FPGA/ASIC designer as he has tried something useless or not. So back to your original question, why should you use it? No reason at all. Take the time if you're interested to understand it. Me, I see it as a strange cpu with some interesting ideas but, then I cut my teeth programming a PDP-8I. At the other end of the spectrum I have a bunch of Xilinx parts and doing my own cpu would be a fun exercise. Would I do that one, no. There are features I'd want to look at. Allison Real address is: Allisonp @ world DOT std DOT com ++++BULK Email severely not wanted+++Article: 12965
>tcoonan@mindspring.com (Thomas A. Coonan) wrote: > >>It makes sense that you could do the below. Have you done it? >>Care to share any examples? > >no I have not done it myself so sorry no examples or benchmarks > >>TODAY in my ASIC, I'll not have that luxury. For more than just a few >>logic equations and terms, it'd be *nice* to somehow use Synthesis >>(it'd be neat if you could somehow make these macros into a Synopsys >>library cell and actually synthesize to it!) and not have to >>hand-craft every single configuration bit. > >but this beats the purpose, don't you think ? I think you are confusing the >initial synthesis where you define a cell and put it into your asic and the Field >Programming stage. If you know what features you want when you do the initial >asic, you don't need any FP cells. You are right that you need some kind of >synthesis and configuration tool to do the Field Programming part but I doubt >that will be Synopsys or any asic layout tool. I think I'm pretty clear about the 2 phases of the "synthesis". Clearly, synthesizing the FP/macros themselves is the traditional synthesis pass. The second "synthesis", "place & route", whatever the right phrase for this is, comes later, in the field, in the lab, via programmable registers/SPI/shift-chains, etc., at run-time. My passing thought was just that if you could define a new set of Synopsys library cells that were the macros, you could actually get Synopsys to "synthesize" the configuration (you would still have to then translate this netlist into the configuration data). Just a passing thought - I don't really expect this is easy or even doable. We can drop the "synthesis" for FP configuration idea, and instead try to come up with the FP Macros that are reasonable to configure by hand... > >> Lacking good "Place & >>Route" tools, would it be better to have more complex, coarse macros >>that would be potentially closer to a more human intuitive level? >>Maybe the trick is; to pick an appropriate fine vs. coarse grain macro >>based on your application and tools (or lack thereof). > >What I am thinking is minimal programmability from this new cell. So you can >define the FP Macro and program it by hand after you manufacture your asic. If >you want half standard cell/half FP cells on a 400K gate asic then you need a lot >more tool support for a much more complex FP macro and routing resources. At that >point you're reaching to the point of designing a new FPGA architecture yourself >and there are companies making a lot of money from that business already :-) I'm interested in devoting a very, very small percentage of my total ASIC to this (1-4%). For example, coming up with an IP (e.g. Internet Protocol not the other IP!) packet filter on a downstream path that is usable by the software people can be a challenging problem. One can come up with all kinds of ad-hoc circuits that, in the end, prove inadequete. A filter that's reconfigurable may have a better chance of begin used. What would the FP look like? Like a XILINX CLB? Coarser? If you're forced to program it by hand, and a little bit of silicon waste is acceptable, would you include ALU type functions? Hasn't anyone done this before? > >muzo > >WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net>Article: 12966
On Fri, 06 Nov 1998 14:18:49 -0500, jerry english <jenglish@planetc.com> wrote: >Does anybody know of published benchmarks concerning the >results produced by various FPGA HDL compilers? >I have downloaded and tried two of the tools but I >would like to see additional data before deciding which >to purchase. The only published benchmarks you are likely to see are "advert-orials" presented by whichever company has marketing budget to blow. Each will present some kind of *spin* on their results to show how they were faster and *better* than anyone else. Your best bet is to check that each tool in your price range produces results appropriate to your expectations. Do P&R on the results, do not believe any estimates from a synthesis tool. They may be reasonably accurate, but some can be wildly optimistic, whereas some can be pessimistic. The best range of estimates I have seen is one tool saying 52ns, the other 17ns, and P&R being 49ns and 50ns critical path respectively after P&R. Strangely enough, the 17ns tool was the one to be purchased until somebody went through the 2 hour P&R run for each netlist. After that it wasn't. However, if you are going to benchmark, then you should ideally use a number of designs that have more than just an adder or counter in them, and decide what criteria you will use to evaluate the results. Build a table of results and take the average of the post P&R results for both area, final speed, and P&R time required. Try to keep the P&R effort constant if you can. Chances are, if you are looking at the two leading tools in the marketplace, you will see an average of results that do not differ by a great deal. This wil be especially true when using a "PHd" synthesis methodology (That's Push *Here* dummy). If the vendor AEs are willing, it may be a good idea to see if they can improve your results with any tricks or other bells and whistles, as you would inevitably find those and use them if you purchased the tool. If each tool is still equal, or good enough for your purpose, at that point then there are other things that may influence your decision. Timing estimation accuracy Constraint inputs and forward annotation etc. Buffering of clocks and other signals (internal & external) Scripting (if you like that sort of thing) Hierarchy management/manipulation Breadth of Language supported Bells & whistles in terms of add-ons to the primary product Technical support available from the vendor/distributor (Important) It may also be a good idea to think about what you might need from a synthesis tool vendor both now, and in the future (say 24 months). If, after all that, you still can't make up your mind, then use a pin on a piece of paper, or make an emotional decision about whether you like/loathe the GUI or pretty CD case it came in. :-) Just a few thoughts Stuart An Exemplar/ModelTech/Renoir distibutor trying to be unbiased. For Email remove "NOSPAM" from the addressArticle: 12967
Hi, Can you be more specific? VGA? it is an analog system, do you want a graphic card system? Or do you want a fully compatible VGA system controller with all of it's registers and parameters? Regards, Farhad A. "alpha" <alpha3.1@ix.netcom.com> wrote: > Does anyone have any information on interfacing a Xilinx FPGA to a VGA >monitor (what about SVGA?)? I am interested in any schematics, articles, or >code that might be available. I would greatly appreciate any assistance. > >Thanks in advance, >-EKC *.........................................* * Farhad Abdolian, Stockholm/Sweden * * Homepage: http://www.algonet.se/~farhad * * ICQ: 10908280 * * Remove all AT_ before replying * *.........................................*Article: 12968
tcoonan@mindspring.com (Thomas A. Coonan) wrote: > My >passing thought was just that if you could define a new set of >Synopsys library cells that were the macros, you could actually get >Synopsys to "synthesize" the configuration (you would still have to >then translate this netlist into the configuration data). Just a >passing thought - I don't really expect this is easy or even doable. >We can drop the "synthesis" for FP configuration idea, and instead >try to come up with the FP Macros that are reasonable to configure >by hand... > I think you can use any one of the OSS synthesis programs to generate output to program your FP macros. Berkeley has nice tools. >ASIC to this (1-4%). For example, coming up with an IP (e.g. Internet >Protocol not the other IP!) packet filter on a downstream path that is >usable by the software people can be a challenging problem. One can >come up with all kinds of ad-hoc circuits that, in the end, prove >inadequete. A filter that's reconfigurable may have a better chance >of begin used. If you have a well defined application, adding programmability or flexibility to it is simpler. You can even create a semi-fixed state machine and let the user decide on where and on what condition the transitions will be. A generic FP macro might be an over kill for your specific app and it also might be too difficult to use. muzo WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net>Article: 12969
Farhad Abdolian wrote in message <36491344.36244649@news.algonet.se>... >Hi, >Can you be more specific? VGA? it is an analog system, do you want a graphic >card system? Or do you want a fully compatible VGA system controller with all of >it's registers and parameters? What I hope to be able to do is generate VGA color signals with a Xilinx FPGA so that I can directly drive a VGA monitor. I also want to be able to add an interface for a mouse so that the Xilinx chip can display the mouse pointer on the monitor. I will probably need some D/A converters in order to generate the analog signals for the VGA monitor, but I'm not quite sure where to start. -EKCArticle: 12970
One component for the ENV1 is the serial port. I don't have
a FPGA descritpion of one, but I thought I would give a software
view of one, and high level code to view it. Also, I will follow
this with hand compiled code for the TE16.
(* mcintosh@vima.austin.tx.us
* Sample UART handler software for Joe Allen's TE16 CPU
*
DEFINITION Serial;
CONST
Uarts = 4;
empty = 1;
full = 2;
rx = 0;
tx = 1;
PROCEDURE Availability (id, dir: INTEGER): INTEGER;
PROCEDURE GetChar (id: INTEGER; VAR ch: CHAR);
PROCEDURE Init;
PROCEDURE Initialize (id, dir: INTEGER);
PROCEDURE SendChar (id: INTEGER; ch: CHAR);
END Serial.
*)
MODULE Serial;
IMPORT SYSTEM;
CONST (* changed on a per design basis *)
Buffsize = 32; (*User specified multiple of 2*)
Uarts* = 4; (*Total number of Uarts supported*)
CONST (* not changed so often *)
unused = 0; empty* = 1; full* = 2;
rx* = 0; tx* = 1;
TYPE
BuffRoot = POINTER TO BuffArray;
Buff = POINTER TO BuffDesc;
BuffArray = ARRAY Uarts OF ARRAY 2 OF Buff;
BuffDesc = RECORD
in, out : INTEGER; (*index of next buff location to be read/written*)
buffer : ARRAY Buffsize OF CHAR;
END;
VAR
buffs : BuffRoot;
uartRAM : ARRAY Uarts OF ARRAY 2 OF BuffDesc;
PROCEDURE Availability*( id : INTEGER; dir : INTEGER ) : INTEGER;
VAR this : Buff; aux : INTEGER;
BEGIN
this := buffs[ id, dir ];
aux := (this.in + Buffsize - this.out ) MOD Buffsize;
IF aux = 0
THEN RETURN empty
ELSIF aux = Buffsize -1
THEN RETURN full
END
END Availability;
(* Only called if Availability # empty *)
PROCEDURE GetChar*( id : INTEGER; VAR ch : CHAR );
VAR this : Buff;
BEGIN
this := buffs[ id, rx ];
ch := this.buffer[ this.out ];
INC( this.out )
END GetChar;
(* Only called if Availability # full *)
PROCEDURE SendChar*( id : INTEGER; ch : CHAR );
VAR this : Buff;
BEGIN
this := buffs[ id, tx ];
this.buffer[ this.in ] := ch;
INC( this.in )
END SendChar;
PROCEDURE Initialize*( id, dir : INTEGER );
VAR this : Buff;
BEGIN
this := buffs[ id, dir ];
this.in := 0;
this.out := 0;
(*set speed, parity, other stuff if it needs doing*)
END Initialize;
PROCEDURE Init*;
VAR
id, dir : INTEGER;
BEGIN
NEW( buffs );
FOR id := 0 TO Uarts-1 DO
FOR dir := 0 TO 1 DO
(* buffs[ id, dir ] := SYSTEM.VAL( Buff, SYSTEM.ADR( uartRAM[ id, dir ] ) ); *)
NEW( buffs[ id, dir ] );
Initialize( id, dir )
END
END
END Init;
BEGIN (*body*)
Init
END Serial.Init
Article: 12971--------------027CD320BB634D2364DD68DC Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit POSITION TITLE: VLSI architect, circuit design and implementation research engineers (Members of Technical Staff) LOCATION: Murray Hill, NJ SHORT-TERM EXPECTATIONS: FIRST 90 DAYS The succesful candidate will be assigned to 1) identify the circuit implement opportunities for optical, wireless, switching and access communicaitons systems, 2) identify the algorithm implementation opportunties for various communicaitons systems, 3) identify the design challenges for implementing Gb/s circuits, or 4) identify the opportunity for circuit realization cycle time reduction in communication systems MEDIUM-TERM EXPECTATIONS: 90 DAYS TO ONE YEAR The successful candidate will, based on the initial studies from the first 3 months, 1) propose feasible architectures for efficient circuit realization of various communications functions, 2) generate mathematical models of the various algorithms to compare peformance and cost of various implementation options 3) provide initial designs of impementing Gb/s circuits on advanced silicon processing technologies 4) suggest methodology for cycle time management LONG-TERM EXPECTATIONS: AFTER THE FIRST YEAR The successful candidate will have completed the design projects, and is expected to continue to identify emerging opportunities of circuit realization for communication systems PLEASE LIST THE FIVE MOST IMPORTANT TASKS THIS PERSON WILL PERFORM ON AN ONGOING BASIS. 1) Identify opportunities for realizing communications functions on integrated circuits 2) VLSI architecture and high speed circuit design for communication systems 3) Realization of signal processing algorithms (layer I) on integrated circuit 4) Realization of communications protocols (layer II and above) on integrated circuits 5) Cycle time management PLEASE LIST THE MOST IMPORTANT TASKS THIS PERSON WILL PERFORM DAY ONE OF JOINING YOUR ORGANIZATION. Identifying and realizing communications functions on integrated circuits WHAT SKILLS MUST THE SUCCESSFUL CANDIDATE POSSESS TO ACCOMPLISH THE GOALS OF THE ORGANIZATION? Skills and Experience · Candidates should possess expert design skills in one or more of the following areas together with the knowledge of the technical challenges facing the industry and, most importantly, a creative ability to lead research projects that address these challenges. Design Skills · custom circuit design · placement, routing and synthesis · VHDL design · signal integrity management · circuit simulation, timing and verification · mixed-signal design · FPGA design · Design Experience · high speed digital circuits · application-specific integrated circuit · co-processor and accelerators · application-specific standard circuit product · digital signal processors · design of peripheral, bus, and I/O · microcontrollers and RISC processors · hardware and software co-design · analog circuits including filters, analog-to-digital converters, digital-to-analog converters, trans-impedance amplifiers, and laser drivers · VSLI Design For Testability (DFT) techniques · memory and DMA Architecture and System Design Experience · integrated circuit for communication systems, including optical network, wireless, switching, and access · realization of communication protocols (layer II and above) on integrated circuits · realization of signal processing algorithms (layer I) on integrated circuits Circuit Production Experience · cycle time management · design process analysis and optimization WHAT TRAITS MUST THIS PERSON NOT POSSESS? The candidate must not expect an elaborate development process surrounding the projects, nor to have complete detailed frozen specification before beginning design. The candidate must not expect or require a large team environment – the project teams are typically small and very focused. The candidate must not expect to concentrate only on circuit design – full stream involvement from opportunity identification, system definition, planning, architecture and development is expected. The person should be very hands-on and not expect a large staff of technicians or other support personnel to be assigned to projects. WHO WILL THIS POSITION REPORT TO? Research department head PLEASE DESCRIBE THE ORGANIZATIONAL STRUCTURE THAT SURROUNDS THIS POSITION. The projects will be in about 3-4 research departments, as part of the Bell Labs Research organization. The Research organization, which has approximately 1000 people, is responsible for creating new technology and systems in support of the Lucent business units. HOW HAS THIS POSITION BEEN HANDLED UP TILL NOW? The design research engineers have been recruited steadily over the years but the present goal is to staff another 20-30 people very quickly. PAGE FOUR HOW MUCH TRAVEL DO YOU ESTIMATE IS ASSOCIATED WITH THIS POSITION? Depending on the specific function, the travel could range from very little to a couple of times a month. The travel could be both domestic and international. HOW MANY YEARS OF PREVIOUS EXPERIENCE WOULD BE PREFERRED? 3-5 years or more of industrial experience would be a plus. WHAT ARE THE EDUCATIONAL REQUIREMENTS OF THE SUCCESSFUL CANDIDATE? PhD degress from EE or CS are strongly preferred. WHAT FUNCTIONAL EXPERIENCE DO YOU SEE THIS PERSON POSSESSING IN PREVIOUS POSITIONS? The same as described above would be strongly preferred. (New PhD graduates are welcome as well.) WHAT PAST INDUSTRY EXPERIENCE WOULD THE SUCCESSFUL CANDIDATE HAVE COME FROM? R&D organizations from telecommunication companies or integrated circuits vendors. WHAT DO YOU SEE AS SOME OF THE KEY "PLUSES" OF THE POSITION AND YOUR ORGANIZATION? The successful candidates will have the opportunity and freedom to define circuit design and implementation projects for making communications systems more efficient and more cost-effective. The working environment will be with many talented and highly motivated researchers at Bell Labs. WHAT IS THE COMPENSATION TARGETED AT AND HOW IS IT STRUCTURED? I.E. BASE, CASH BONUS, STOCK, CAR, CLUB.... The candidate will receive a base salary, plus an annual bonus based on the financial performance of Lucent, plus an additional bonus based on the performance of the individual in the preceding year. PLEASE LIST ANY OTHER CHARACTERISTICS OR INFORMATION YOU FEEL ARE NECESSARY FOR THIS PERSON TO SUCCEED IN YOUR ORGANIZATION’S ENVIRONMENT. Exceptional technical skills, self confidence and the ability to work independently are essential. The candidate will work with other very strong technical contributors who expect outstanding performance from all of their colleagues. PLEASE LIST ANY OTHER REQUIREMENTS THE SUCCESSFUL CANDIDATE MUST POSSESS. Advancement in the Bell Labs environment typically requires taking a lead technical role in an innovative and successful project. Key to advancement is the ability to identify new technology opportunities, developing and clearly articulating a plan for capitalizing on the opportunity, securing management support, leading the effort, and delivering as proposed. PLEASE LIST ANYTHING ELSE I NEED TO KNOW REGARDING THE ORGANIZATION AND POSITION. This organization has already 20-30 experienced researchers in the same area. The laboratory is called “Wireless Research Laboratory” but the projects are more than just for wireless. >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> Visit Lucent on ejob @: http://www.ejob.com/lucent3.htm email: lucent2@ejob.com --------------027CD320BB634D2364DD68DC Content-Type: text/html; charset=iso-8859-1 Content-Transfer-Encoding: 8bit <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML> <B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>POSITION TITLE:</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>VLSI architect, circuit design and implementation research engineers</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>(Members of Technical Staff)</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>LOCATION:</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>Murray Hill, NJ</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>SHORT-TERM EXPECTATIONS: FIRST 90 DAYS</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>The succesful candidate will be assigned to</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>1) identify the circuit implement opportunities for optical, wireless,</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>switching and access communicaitons systems,</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>2) identify the algorithm implementation opportunties for various</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>communicaitons systems,</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>3) identify the design challenges for implementing Gb/s circuits, or</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>4) identify the opportunity for circuit realization cycle time reduction in</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>communication systems</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>MEDIUM-TERM EXPECTATIONS: 90 DAYS TO ONE YEAR</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>The successful candidate will, based on the initial studies from the first 3</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>months,</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>1) propose feasible architectures for efficient circuit realization of</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>various communications functions,</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>2) generate mathematical models of the various algorithms to compare</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>peformance and cost of various implementation options</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>3) provide initial designs of impementing Gb/s circuits on advanced silicon</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>processing technologies</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>4) suggest methodology for cycle time management</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>LONG-TERM EXPECTATIONS: AFTER THE FIRST YEAR</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>The successful candidate will have completed the design projects, and is</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>expected to continue to identify emerging opportunities of circuit</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>realization for communication systems</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>PLEASE LIST THE FIVE MOST IMPORTANT TASKS THIS PERSON WILL PERFORM ON AN</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>ONGOING BASIS.</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>1) Identify opportunities for realizing communications functions on</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>integrated circuits</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>2) VLSI architecture and high speed circuit design for communication systems</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>3) Realization of signal processing algorithms (layer I) on integrated</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>circuit</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>4) Realization of communications protocols (layer II and above) on</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>integrated circuits</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>5) Cycle time management</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>PLEASE LIST THE MOST IMPORTANT TASKS THIS PERSON WILL PERFORM DAY ONE OF</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>JOINING YOUR ORGANIZATION.</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>Identifying and realizing communications functions on integrated circuits</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>WHAT SKILLS MUST THE SUCCESSFUL CANDIDATE POSSESS TO ACCOMPLISH THE GOALS OF</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>THE ORGANIZATION?</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>Skills and Experience</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>· Candidates should possess expert design skills in one or more of the</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>following areas together with the knowledge of the technical challenges</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>facing the industry and, most importantly, a creative ability to lead</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>research projects that address these challenges.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1> Design Skills</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>· custom circuit design · placement, routing and synthesis</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>· VHDL design · signal integrity management</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>· circuit simulation, timing and verification · mixed-signal design</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>· FPGA design ·</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1> Design Experience</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>· high speed digital circuits · application-specific integrated circuit</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>· co-processor and accelerators · application-specific standard circuit</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>product</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>· digital signal processors · design of peripheral, bus, and I/O</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>· microcontrollers and RISC processors · hardware and software co-design</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>· analog circuits including filters, analog-to-digital converters,</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>digital-to-analog converters, trans-impedance amplifiers, and laser drivers</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>· VSLI Design For Testability (DFT) techniques</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>· memory and DMA</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1> Architecture and System Design Experience</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>· integrated circuit for communication systems, including optical network,</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>wireless, switching, and access · realization of communication protocols</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>(layer II and above) on integrated circuits</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>· realization of signal processing algorithms (layer I) on integrated</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>circuits</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1> Circuit Production Experience</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>· cycle time management · design process analysis and optimization</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>WHAT TRAITS MUST THIS PERSON NOT POSSESS?</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>The candidate must not expect an elaborate development process surrounding</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>the projects, nor to have complete detailed frozen specification before</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>beginning design. The candidate must not expect or require a large team</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>environment – the project teams are typically small and very focused. The</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>candidate must not expect to concentrate only on circuit design – full</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>stream involvement from opportunity identification, system definition,</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>planning, architecture and development is expected. The person should be</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>very hands-on and not expect a large staff of technicians or other support</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>personnel to be assigned to projects.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>WHO WILL THIS POSITION REPORT TO?</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>Research department head</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>PLEASE DESCRIBE THE ORGANIZATIONAL STRUCTURE THAT SURROUNDS THIS POSITION.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>The projects will be in about 3-4 research departments, as part of the Bell</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>Labs Research organization. The Research organization, which has</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>approximately 1000 people, is responsible for creating new technology and</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>systems in support of the Lucent business units.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>HOW HAS THIS POSITION BEEN HANDLED UP TILL NOW?</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>The design research engineers have been recruited steadily over the years</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>but the present goal is to staff another 20-30 people very quickly.</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1> PAGE FOUR</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>HOW MUCH TRAVEL DO YOU ESTIMATE IS ASSOCIATED WITH THIS POSITION?</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>Depending on the specific function, the travel could range from very little</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>to a couple of times a month. The travel could be both domestic and</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>international.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>HOW MANY YEARS OF PREVIOUS EXPERIENCE WOULD BE PREFERRED?</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>3-5 years or more of industrial experience would be a plus.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>WHAT ARE THE EDUCATIONAL REQUIREMENTS OF THE SUCCESSFUL CANDIDATE?</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>PhD degress from EE or CS are strongly preferred.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>WHAT FUNCTIONAL EXPERIENCE DO YOU SEE THIS PERSON POSSESSING IN PREVIOUS</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>POSITIONS?</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>The same as described above would be strongly preferred. (New PhD graduates</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>are welcome as well.)</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>WHAT PAST INDUSTRY EXPERIENCE WOULD THE SUCCESSFUL CANDIDATE HAVE COME FROM?</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>R&D organizations from telecommunication companies or integrated circuits</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>vendors.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>WHAT DO YOU SEE AS SOME OF THE KEY "PLUSES" OF THE POSITION AND YOUR</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>ORGANIZATION?</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>The successful candidates will have the opportunity and freedom to define</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>circuit design and implementation projects for making communications systems</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>more efficient and more cost-effective. The working environment will be with</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>many talented and highly motivated researchers at Bell Labs.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>WHAT IS THE COMPENSATION TARGETED AT AND HOW IS IT STRUCTURED? I.E. BASE,</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>CASH BONUS, STOCK, CAR, CLUB....</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>The candidate will receive a base salary, plus an annual bonus based on the</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>financial performance of Lucent, plus an additional bonus based on the</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>performance of the individual in the preceding year.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>PLEASE LIST ANY OTHER CHARACTERISTICS OR INFORMATION YOU FEEL ARE NECESSARY</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>FOR THIS PERSON TO SUCCEED IN YOUR ORGANIZATION’S ENVIRONMENT.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>Exceptional technical skills, self confidence and the ability to work</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>independently are essential. The candidate will work with other very strong</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>technical contributors who expect outstanding performance from all of their</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>colleagues.</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>PLEASE LIST ANY OTHER REQUIREMENTS THE SUCCESSFUL CANDIDATE MUST POSSESS.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>Advancement in the Bell Labs environment typically requires taking a lead</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>technical role in an innovative and successful project. Key to advancement</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>is the ability to identify new technology opportunities, developing and</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>clearly articulating a plan for capitalizing on the opportunity, securing</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>management support, leading the effort, and delivering as proposed.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>PLEASE LIST ANYTHING ELSE I NEED TO KNOW REGARDING THE ORGANIZATION AND</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>POSITION.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>This organization has already 20-30 experienced researchers in the same</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>area. The laboratory is called “Wireless Research Laboratory” but the</FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>projects are more than just for wireless.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>></FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B> <P><B><FONT FACE="Arial,Helvetica"><FONT COLOR="#3333FF">Visit Lucent on ejob @: <A HREF="http://www.ejob.com/lucent3.htm">http://www.ejob.com/lucent3.htm</A></FONT></FONT></B> <BR><B><FONT FACE="Arial,Helvetica"><FONT COLOR="#3333FF">email: lucent2@ejob.com</FONT></FONT></B></HTML> --------------027CD320BB634D2364DD68DC--Article: 12972
Well, it's probably me... but damn it... I'm running Foundation 1.5 here, and getting the schematic capture portion of the package to talk to the simulator is nearly impossible. I'll tell it to simulate a macro, it'll open up the simulator, and then I'll start adding probe points. The simulator COMPLETELY IGNORES the probe points I'm clicking on, when it should be adding them to its own list. I'll click over on the simulator and add some signals, and schematic captures completely ignores what's been added! Better still, sometimes schematic capture won't even let me add any probe points at all, just completely ignoring mouse clicks! You go ahead and step time in the simulator, and the signals listed do reasonable things, but schematic just sits there with its probe points displaying nothing at all. !@$!@#%^^#$ OK, this doesn't happen 100% of the time. On VERY RARE occasion it actually works the way it should. I can't believe this happens to all you other people on a daily basis, or there'd be an angry mob outside of Xilinx HQ threatening to burn the place down. So what am I doing wrong? The concept seems really simple -- add a probe in schematic, and the simulator picks it up, add a signal in simulator, and schematic should pick it up... right? ---Joel KolstadArticle: 12973
I recently purchased a couple of tubes of XC3090 -125 and XC3020 -70 FPGAs $2ea at a electronics swap meet. I realize that these parts have been obsoleted by Xilinx. But I wondering if they have any value as an educational platform for students to learn about FPGAs? I noticed that Foundation 1.5 does not support the old XC3000 series. Can these chips be programed as the XC3000A? Am I wasting my time and students time with these obsolete parts? Or, did I get a bargain that will allow students to use an affordable (free) fpga in their projects? Any information / opinions would be greatly appreciated.Article: 12974
Design entry: Verilog-XL. Synthesis: Synplify 5.0.7 Placement&Routing: Design Manager 1.5 We have just finished our last project. Our aim was to target the chip to XC4062XL/-3, because the resource calculations seemed to fit this device. Synplify gives ca. 600-650 CLB's for logic and black-boxed internal RAM's consume less than 1200 CLB's. We have to use some internal RAM to improve chip performance. However, when we give the chip to Design Manager, it comes out more than 1600 CLB's. The Map expands internal resources to ca. 2500-2600 CLB's, which exceeds XC4062XL. So, we have chosen XC4085XLA/-1, which is pin-to-pin compatible to the smaller device. So, it seems that the core consumes 80% of the XC4085XLA resources. Firstly we meet x4kma errors, which solutions are suggested by Xilinx folks. Two solutions are: 1. map -ir 2. INST XXX USE_RLOC = FALSE; (recently recommended) We have used first solution till now, but we always had unrouted which change from 2 till 2000. So, we have never come to end and Design Manager always aborts. (We don't know how to use RLOC, so would please give us some advice? So, as it seems, we have a core half of which is internal RAM's. As each P&R effort takes at least 2 days on Ultra-10 / 128 MB, we don't have enough time to try perfectionist solutions. Do unrouted regions have a great effect on these results? Does the change of internal RAM organization (such as to organize it with smaller RAM's generated by RAM compilers -LogiBLOX-) have a real positive effect on resource sharing on FPGA? Utku PS: Synplify: Chip has 4 external clocks and 4 generated from one clock. Internal clock generators have been implemented by counters. We don't know how to assign those internal clocks to clock networks on Xilinx XC4085XLA. Synplify warns that we don't use syn_clock. But we haven't found syn_clock in Synplify Manuals. We have defined external clocks and internal clock in *.sdc file but in speed grade of -1 we have never met good delays. We have always got slacks. So we have increased frequency rates of external clocks. Results fit but there are slacks for higher frequences. We have tried constraint commands on *.sdc file to improve the slacks but synthesizer has a big "inertia", but unfortunately no improvements observed. Design Manager: We don't know how to define internal clocks in UCF file. We are told to remove *.NCF, to have better results. Any help will be greatly appreciated.
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