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Take a look at http://www.xess.com/FPGA/homepage.html. They have a board with fpga same ram anf vga connector as well as source for the programming as a vga controler. hope it helps. regards roman alpha wrote: > Farhad Abdolian wrote in message > <36491344.36244649@news.algonet.se>... > >Hi, > >Can you be more specific? VGA? it is an analog system, do you want a > graphic > >card system? Or do you want a fully compatible VGA system controller > with > all of > >it's registers and parameters? > > What I hope to be able to do is generate VGA color signals with a > Xilinx > FPGA so that I can directly drive a VGA monitor. I also want to be > able to > add an interface for a mouse so that the Xilinx chip can display the > mouse > pointer on the monitor. I will probably need some D/A converters in > order to > generate the analog signals for the VGA monitor, but I'm not quite > sure > where to start. > > -EKCArticle: 12976
Hi! Help with a example of operator time in MAX PLUS v9.01 < time declaration >::=time < time ns >; Mail: pp411@dataforce.netArticle: 12977
I like to know how to implement a multiplier in a FPGA (6000 series), because I have to implement one using Lola en C++ or C. If possible I would appreciate also some information about the way I have to address the FPGA through C++ and C. Thank youArticle: 12978
My mistake, sorry. I use the Micrel MIC5201-3.3. -- Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 12979
I designed two processors for my class which can be synthesizable with PARTHENON. ( see http://www.kecl.ntt.co.jp/car/parthe for the PARTHENON ) SP/1 is a simple pipeline processor with interlock, branch prediction, interruptions. It will be about 5000 ASIC gates and will run at 23MHz when compiled with PARTHENON demo library. SP/1C is a processor with small data cache, store buffers, hit under miss, same instructions as SP/1. It will be about 8500 ASIC gates. If you are interested in these processors, see http://shimizu-lab.et.u-tokai.ac.jp/project.html The last update date of sp/1 and sp/1c is 09-Nov-1998.Article: 12980
John Kennedy <johnkennedy@home.com> wrote: >I recently purchased a couple of tubes of XC3090 -125 and XC3020 -70 >FPGAs $2ea at a electronics swap meet. I realize that these parts have >been obsoleted by Xilinx. But I wondering if they have any value as an >educational platform for students to learn about FPGAs? I noticed that >Foundation 1.5 does not support the old XC3000 series. Can these chips >be programed as the XC3000A? Am I wasting my time and students time >with these obsolete parts? Or, did I get a bargain that will allow >students to use an affordable (free) fpga in their projects? Any >information / opinions would be greatly appreciated. I think they are still usable. That's why I still run the Foundation v6.0.1 developement system. You should probably be able to do logic designs for them by specifing the XC3000A, but the simulation will be wrong. If your developement system is current, you might try talking to the Xilinx FAE in your area, and ask for a copy of the older Foundation 6.0.1. This one will definately handle those parts. Tim Olmstead email : timolmst@cyberramp.net Visit the unofficial CP/M web site. MAIN SITE AT : http://cws86.kyamk.fi/mirrors/cpm PRIMARY US MIRROR AT : http://www.mathcs.emory.edu/~cfs/cpm SECONDARY US MIRROR AT : http://CPM.INTERFUN.NETArticle: 12981
In article <72586h$n6l@sjx-ixn8.ix.netcom.com> "alpha" <alpha3.1@ix.netcom.com> writes: >From: "alpha" <alpha3.1@ix.netcom.com> >Subject: Re: FPGA VGA interface >Date: Sun, 8 Nov 1998 18:06:57 -0500 >What I hope to be able to do is generate VGA color signals with a Xilinx >FPGA so that I can directly drive a VGA monitor. I also want to be able to >add an interface for a mouse so that the Xilinx chip can display the mouse >pointer on the monitor. I will probably need some D/A converters in order to >generate the analog signals for the VGA monitor, but I'm not quite sure >where to start. At ftp://137.193.64.130/pup/xproz/ you can find the documentation of a comlete computer built with Xilinx chips only. The graphics card supports only two colors (selectable from 8 colors) and has a resolution of 640x400.Article: 12982
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--------------038EC1E0F7A18C4DB1C9E04E
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Xilinx claims to have fixed their floorplanner in the F1.5
S/W release (I dunno about that, it still crashes Map on me,
waiting for a visit from local fae to find out if I'm doing
something wrong or is it the S/W). But in the documentation,
it states:
Note: ...The Set Floorplan File(s) command is available
for the XC4000 and Spartan device families only.
I find that the larger a design is, the more
useful floorplanning becomes to getting a high-
performance implementation. Does anyone know if
Xilinx intends to drop floorplanning support for Virtex,
or is it just something that was not completed in time
for the 1.5 release?
Just wondering,
- John
--------------038EC1E0F7A18C4DB1C9E04E
Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for John L. Smith
Content-Disposition: attachment; filename="vcard.vcf"
begin: vcard
fn: John L. Smith
n: Smith;John L.
org: Visicom Imaging Products
adr: 1 Burlington Woods;;;Burlington;MA;01803;USA
email;internet: jsmith@visicom.com
title: Principal Engineer
tel;work: 781-221-6700
tel;fax: 781-221-6777
note: http://www.visicom.com/products/Vigra/index.html
x-mozilla-cpt: ;0
x-mozilla-html: TRUE
version: 2.1
end: vcard
--------------038EC1E0F7A18C4DB1C9E04E--
Article: 12983
I have compiled a sample high level program with the
Joe Allen TE16 CPU. This is my first experience with
this CPU :-) and my first response is that it is actually
nice to work with. I probably brought a lot of coding
patterns from other experience that is not appropriate to
this architecture, and I invite others to add to this.
; The Serial Port high level software interface.
; Compiled from Serial.Mod using the Graphite-1 (Yellow) TE16 Compiler.
; November 9, 1998
; mcintosh@vima.austin.tx.us
; ----
; A total of 168H (362D) bytes were used to compile this module.
;The compiler occasionally produces errors when dereferencing pointers.
;Please post bug reports to the newsgoup.
; ----
0000 RunTimeSupport:
0000 RTS_MUL:
0000 14 02 pop p
0002 12 00 00 00 brk #0 ;debug support
0006 RTS_NEW:
0006 14 02 pop p
0008 12 00 00 01 brk #1 ;debug support
000C Var:
000C buffs dfw 0
; ----
; The stack for Availability is
return equ 0C
id equ 0A
ch equ 08
ret_PC equ 06
;The local variables are
this equ 04
aux equ 02
expr equ 00
; ----
000E Availability:
000E 5E FA addsbx #-6 ;allocate space on entry.
;compute address buffs[ id, dir ]
0010 7B 0A lda id
0012 3F 00 sta expr
0014 25 00 lsl 0
0016 25 00 lsl 0 ;mul by 4
0018 58 00 ldab #rx
001A 6D 00 add expr ;add total offsets.
001C 3F 00 sta expr ;
001E 7A 0C 00 00 lda #buffs ;Address of pointer.
0022 6D 00 add expr ;add total offsets.
0024 3F 04 sta this ;
0026 FA 04 lda 04,0 ; this.in
0028 4C 20 addb #32 ; +Buffsize
002A F4 04 sub 04,2 ; -this.out
002C 48 1F bitb #31 ; MOD 32
002E 3F 02 sta aux
0030 58 01 ldab #empty
0032 3F 0C sta return
0034 32 48 00 00 jeq Return:
0038 58 02 ldab #full
003A 3F 0C sta return
003C 58 1F ldab #31
003E 51 02 cmpb aux
0040 32 48 00 00 jeq Return:
0044 58 03 ldab #ok
0046 3F 0C sta return
0048 Return:
0048 5E 06 addsbx #6 ;deallocate parameters
004A 14 02 pop p
004C 12 00 00 02 brk #2 ;debug support
; ----
; The stack for GetChar is
id equ 08
ch equ 06
ret_PC equ 04
;The local variables are
this equ 02
expr equ 00
; ----
0050 GetChar:
0050 5E FC addsbx #-4 ;allocate space on entry.
;compute address buffs[ id, dir ]
0052 7B 08 lda id
0054 3F 00 sta expr
0056 25 00 lsl 0
0058 25 00 lsl 0 ;mul by 4
005A 58 00 ldab #rx
005C 6D 00 add expr ;add total offsets.
005E 3F 00 sta expr ;
0060 7A 0C 00 00 lda #buffs ;Address of pointer.
0064 6D 00 add expr ;add total offsets.
0066 3F 02 sta this ;
0068 FA 02 lda 02,2 ;this.out
006A 25 00 lsl 0
006C 6D 02 add this
006E 3F 00 sta expr ;has adr(this)+2*this.out
0070 FA 00 lda expr,4
0072 3F 02 sta ch ;ch := this.buffer[ this.out ]
0074 B8 02 inc 02,0 ;INC( this.in )
0076 5E 02 addsbx #4 ;deallocate parameters
0078 14 02 pop p
007A 12 00 00 03 brk #3 ;debug support
; ----
; The stack for SendChar is
id equ 08
ch equ 06
ret_PC equ 04
;The local variables are
this equ 02
expr equ 00
; ----
007E SendChar:
007E 5E FC addsbx #-4 ;allocate space on entry.
;compute address buffs[ id, dir ]
0080 7B 08 lda id
0082 3F 00 sta expr
0084 25 00 lsl 0
0086 25 00 lsl 0 ;mul by 4
0088 58 01 ldab #tx
008A 6D 00 add expr ;add total offsets.
008C 3F 00 sta expr ;
008E 7A 0C 00 00 lda #buffs ;Address of pointer.
0092 6D 00 add expr ;add total offsets.
0094 3F 02 sta this ;
0096 FA 02 lda 02,0 ;this.in
0098 25 00 lsl 0
009A 6D 02 add this
009C 3F 00 sta expr ;has adr(this)+2*this.in
009E FA 02 lda ch ;
00A0 BE 00 sta expr,4 ;this.buffer[ this.in ] := ch
00A2 B8 02 inc 02,0 ;INC( this.in )
00A4 5E 02 addsbx #4 ;deallocate parameters
00A6 14 02 pop p
00A8 12 00 00 04 brk #4 ;debug support
; ----
; The stack for Initialize is
id equ 06
dir equ 04
ret_PC equ 02
;The local variables are
this equ 00
; ----
00AC Initialize:
00AC 5E FE addsbx #-2 ;allocate space on entry.
;compute address buffs[ id, dir ]
00AE 7B 06 lda id
00B0 16 01 psh a
00B2 58 04 ldab #4 ;2*TSIZE( Buff ) 2 pointers
00B4 18 00 00 00 jsr RTS_MUL ;
00B8 5E 02 addsbx #2 ;deallocate parameters
00BA 3F 00 sta this ;temp variable 'this'
00BC 7B 06 lda dir
00BE 16 01 psh a
00C0 58 02 ldab #2 ;TSIZE( Buff ) a pointer
00C2 18 00 00 00 jsr RTS_MUL ;
00C6 5E 02 addsbx #2 ;deallocate parameters
00C8 6D 00 add this ;add total offsets.
00CA 3F 00 sta this ;
00CC 7A 0C 00 00 lda #buffs ;Address of pointer.
00D0 6D 00 add this ;add total offsets.
00D2 3F 00 sta this ;
00D4 BC 00 clr 00,0 ;this.in := 0
00D6 BC 00 clr 02,0 ;this.out := 0
00D8 5E 02 addsbx #2 ;deallocate parameters
00DA 14 02 pop p
00DC 12 00 00 05 brk #5 ;debug support
; ----
; The stack for Init is
ret_PC equ 0A
;The local variables are
id equ 08
dir equ 06
tv1 equ 04 ;termination value
tv2 equ 02 ;termination value
off equ 00
; ----
00E0 Init:
00E0 5E F6 addsbx #-10 ;allocate space on entry.
00E2 58 02 ldab #2 ;load TSIZE(buffs)
00E4 16 01 psh a
00E6 7A 0C 00 00 lda #buffs
00EA 16 01 psh a
00EC 1A 06 00 00 jsr RTS_NEW ;call new
00F0 5E 04 addsb #4 ;tidy up after call.
00F2 for1:
00F2 58 00 ldab #0 ;id := 0
00F4 BE 08 sta id
00F6 58 03 ldab #3 ;TO Uart.Uarts -1 (3)
00F8 BE 04 sta tv1
00FA fortop1:
00FA F8 08 lda id
00FC F0 04 cmp tv1
00FE 3C 50 01 00 jgt forend1
0102 forstmt01: ;Execute this each time.
0102 for2:
0102 58 00 ldab #0 ;FOR dir := rx
0104 BE 06 sta dir
0106 58 03 ldab #1 ;TO tx
0108 BE 02 sta tv2
010A fortop2:
010A F8 06 lda dir
010C F0 02 cmp tv2
010E 3C 4C 01 00 jgt forend2
0112 forstmt02: ;Execute this each time.
;compute address buffs[ id, dir ]
0112 7B 08 lda id
0114 16 01 psh a
0116 58 04 ldab #4 ;2*TSIZE( Buff ) 2 pointers
0118 18 00 00 00 jsr RTS_MUL ;
011E 5E 02 addsbx #2 ;deallocate parameters
0120 3F 00 sta off ;temp variable 'off'
0122 7B 06 lda dir
0124 16 01 psh a
0126 58 02 ldab #2 ;TSIZE( Buff ) a pointer
0128 18 00 00 00 jsr RTS_MUL ;
012C 5E 02 addsbx #2 ;deallocate parameters
012E 6D 00 add off ;add total offsets.
0130 3F 00 sta off ;
0132 7A 0C 00 00 lda #buffs ;Address of pointer.
0136 6D 00 add off ;add total offsets.
0138 3F 00 sta off ;
013A 18 06 00 00 jsr RTS_NEW ;update pointer whose addr is on stack.
013E 7B 08 lda id ;for id
0140 16 01 psh a
0142 7B 06 lda dir ;for dir
0144 16 01 push ac
0140 1A AC 00 00 jsr Initialize
0144 5E 04 addsbx #4 ;deallocate parameters
0146 forinc2:
0146 B8 02 inc tv2
0148 18 0A 01 00 jmp #fortop2
014C forend2:
014C forinc1:
014C B8 04 inc tv1
014E 18 FA 00 00 jmp #fortop1
0150 forend1:
; return
0150 5E 0A addsb #10 ;remove local storage and recover the entry stack pointer
0152 14 02 pop p
0154 12 00 00 06 brk #6 ;debug support
0158 body:
;at initialize time, the stack contains the address of the
;heap. The heap grows up.
0158 58 02 ldab #2 ;Reserve 1 global variable.
015A 6D 00 add 02 ;Add TOS-1 to AC
015C 3F 02 sta 02 ;store to TOS-1
015E 1A E0 00 00 jsr Init
0162 14 02 pop p
0164 12 00 00 07 brk #7 ;debug support
0168
Article: 12984Gentlemen, It seems you have a good dialog going on here: I have one question which I am still searching for an answer to: For what application would you like to integrate an FPGA type architecture into an ASIC? Assume that the tools (whether Xilinx, Altera, or another) to support the configuration of the FPGA architecture were available. I know that Lucent offer a hybrid FPGA/Gate Array device, but I am struggling to conceive of an application where it would make sense. In article <364814ae.516490363@news.concentric.net>, muzok@nospam.pacbell.net wrote: > tcoonan@mindspring.com (Thomas A. Coonan) wrote: > > My > >passing thought was just that if you could define a new set of > >Synopsys library cells that were the macros, you could actually get > >Synopsys to "synthesize" the configuration (you would still have to > >then translate this netlist into the configuration data). Just a > >passing thought - I don't really expect this is easy or even doable. > >We can drop the "synthesis" for FP configuration idea, and instead > >try to come up with the FP Macros that are reasonable to configure > >by hand... > > > I think you can use any one of the OSS synthesis programs to generate output to > program your FP macros. Berkeley has nice tools. > > >ASIC to this (1-4%). For example, coming up with an IP (e.g. Internet > >Protocol not the other IP!) packet filter on a downstream path that is > >usable by the software people can be a challenging problem. One can > >come up with all kinds of ad-hoc circuits that, in the end, prove > >inadequete. A filter that's reconfigurable may have a better chance > >of begin used. > > If you have a well defined application, adding programmability or flexibility to > it is simpler. You can even create a semi-fixed state machine and let the user > decide on where and on what condition the transitions will be. A generic FP macro > might be an over kill for your specific app and it also might be too difficult to > use. > > muzo > > WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net> > -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12985
We have successfully used the Linear Tech LT1129IQ-3.3 surface mount parts for regulating 3.3V from 6.5 (and or 5). They are an 8-Pin D-Pack and our application was a Xilinx XC4028XL part.Article: 12986
wluka@hotmail.com wrote: > Gentlemen, > > It seems you have a good dialog going on here: I have one question which I am > still searching for an answer to: For what application would you like to > integrate an FPGA type architecture into an ASIC? > > Assume that the tools (whether Xilinx, Altera, or another) to support the > configuration of the FPGA architecture were available. > > I know that Lucent offer a hybrid FPGA/Gate Array device, but I am struggling > to conceive of an application where it would make sense. > > We have an application right now. The ASIC is a big data engine. We have an FPGA that implements the state machine that controls the data flow to the DSPs depending on several factors, history included. I guess we just didn't have enought guts to put the state machine into the ASIC knowing that as soon as we hard coded the algorithms our chief engineer would "enhance" the product. I have been in another situation where the customer changed his mind so many times I felt that hard coding the control would be a BIG risk so I inserted a ram controlled sequencer. Work out pretty well. Had some limitations but it did work. just my 2 cents regards JerryArticle: 12987
>Gentlemen, > >It seems you have a good dialog going on here: I have one question which I am >still searching for an answer to: For what application would you like to >integrate an FPGA type architecture into an ASIC? A stream of framed packet bytes (e.g. MPEG stream). Pretty high-speed - probably too fast for a completely general purpose processor. Want to filter out some packets based on various fields, etc. Trivial example is filtering out IP packets that don't match various addresses. A more elaborate filtering scenario would go into the IP packet's payload to match and compare against other fields; maybe even state-based. Actual filtering requirements often surface down the road once software people are faced with new unanticipated protocols (and ASIC is already done!) If hardware filters can't handle a particular new scenario, then burden is placed on software and all is not lost, but processor burden increases. A RAM-based microsequencer, 2910-style architecture *can* solve this problem (several folks suggested this approach), but the thought was that reconfigurable logic approach might be a nicer, more streamlined alternative.. Maybe not.Article: 12988
What kind of model do you need?? I have a model for an Atmel 24C164 I would be willing to give you. Note that it is simulation model, not synthesizable. Company rules would prohibit me giving you our synthesis code. The model is test for that. G Henry Yogendran wrote: > Hi: > > Please somebody tell me, where I can get free I2C model? > > -- Henry -- Brian C. Boorman Harris RF Communications Rochester, NY 14610 XYZ.bboorman@harris.com <Remove the XYZ. for valid address>Article: 12989
That's why I use viewlogic. Speaking of foundation, has anyone been able to sucessfully import a viewlogic hierarchical schematic that has elements from more than one library (non-megafile library that is)? I have a customer that wants the design in foundation format. Joel Kolstad wrote: > Well, it's probably me... but damn it... I'm running Foundation 1.5 here, > and getting the schematic capture portion of the package to talk to the > simulator is nearly impossible. I'll tell it to simulate a macro, it'll > open up the simulator, and then I'll start adding probe points. The > simulator COMPLETELY IGNORES the probe points I'm clicking on, when it > should be adding them to its own list. I'll click over on the simulator and > add some signals, and schematic captures completely ignores what's been > added! Better still, sometimes schematic capture won't even let me add any > probe points at all, just completely ignoring mouse clicks! > > You go ahead and step time in the simulator, and the signals listed do > reasonable things, but schematic just sits there with its probe points > displaying nothing at all. > > !@$!@#%^^#$ > > OK, this doesn't happen 100% of the time. On VERY RARE occasion it actually > works the way it should. I can't believe this happens to all you other > people on a daily basis, or there'd be an angry mob outside of Xilinx HQ > threatening to burn the place down. So what am I doing wrong? The concept > seems really simple -- add a probe in schematic, and the simulator picks it > up, add a signal in simulator, and schematic should pick it up... right? > > ---Joel Kolstad -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12990
Use the floorplanner. The RAM should be a regular structure, but the M1 PAR is not smart enough to do it well. The floorplanner is a bit painful to use for synthesized designs, but it is still better than nothing. This is a case where a schematic entry would have been a better entry method, as it would have allowed you to easily build the structure hierarchically, complete with relative placement. Utku Ozcan wrote: > Design entry: Verilog-XL. > Synthesis: Synplify 5.0.7 > Placement&Routing: Design Manager 1.5 > > We have just finished our last project. Our aim was to target > the chip to XC4062XL/-3, because the resource calculations seemed > to fit this device. Synplify gives ca. 600-650 CLB's for logic > and black-boxed internal RAM's consume less than 1200 CLB's. > We have to use some internal RAM to improve chip performance. > > However, when we give the chip to Design Manager, it comes out > more than 1600 CLB's. The Map expands internal resources to ca. > 2500-2600 CLB's, which exceeds XC4062XL. So, we have chosen > XC4085XLA/-1, which is pin-to-pin compatible to the smaller device. > So, it seems that the core consumes 80% of the XC4085XLA resources. > > Firstly we meet x4kma errors, which solutions are suggested by > Xilinx folks. Two solutions are: > > 1. map -ir > 2. INST XXX USE_RLOC = FALSE; (recently recommended) > > We have used first solution till now, but we always had unrouted > which change from 2 till 2000. So, we have never come to end and > Design Manager always aborts. (We don't know how to use RLOC, so > would please give us some advice? > > So, as it seems, we have a core half of which is internal RAM's. > As each P&R effort takes at least 2 days on Ultra-10 / 128 MB, > we don't have enough time to try perfectionist solutions. > > Do unrouted regions have a great effect on these results? Does > the change of internal RAM organization (such as to organize it > with smaller RAM's generated by RAM compilers -LogiBLOX-) have > a real positive effect on resource sharing on FPGA? > > Utku > > PS: > > Synplify: > > Chip has 4 external clocks and 4 generated from one clock. > Internal clock generators have been implemented by counters. > We don't know how to assign those internal clocks to clock networks > on Xilinx XC4085XLA. Synplify warns that we don't use syn_clock. > But we haven't found syn_clock in Synplify Manuals. We have defined > external clocks and internal clock in *.sdc file but in speed grade > of -1 we have never met good delays. We have always got slacks. So > we have increased frequency rates of external clocks. Results fit > but there are slacks for higher frequences. We have tried constraint > commands on *.sdc file to improve the slacks but synthesizer has a > big "inertia", but unfortunately no improvements observed. > > Design Manager: > > We don't know how to define internal clocks in UCF file. We are > told to remove *.NCF, to have better results. > > Any help will be greatly appreciated. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12991
There are many ways to build a multiplier, as you might have already discovered. The specific architecture that is best for your application depends on many factors, not the least of which are the desired performance, size and whether you can pipeline it. I have a brief discussion on multiplication in FPGAs on my website. I invite you to take a look. The 6200 is significantly handicapped for arithmetic functions since it does not possess an optimized carry chain (in fact the cell architecture is also very awkward for adders). Without knowing more about your requirements, I can't make specific recommendations. wpauwels wrote: > I like to know how to implement a multiplier in a FPGA (6000 series), > because I have to implement one using Lola en C++ or C. > If possible I would appreciate also some information about the way I > have to address the FPGA through C++ and C. > > Thank you -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12992
How about reconfigurable computing, providing flexibility for product upgrades, or extending product life (by permitting future circuit changes) for starters? wluka@hotmail.com wrote: > Gentlemen, > > It seems you have a good dialog going on here: I have one question which I am > still searching for an answer to: For what application would you like to > integrate an FPGA type architecture into an ASIC? > > Assume that the tools (whether Xilinx, Altera, or another) to support the > configuration of the FPGA architecture were available. > > I know that Lucent offer a hybrid FPGA/Gate Array device, but I am struggling > to conceive of an application where it would make sense. > > In article <364814ae.516490363@news.concentric.net>, > muzok@nospam.pacbell.net wrote: > > tcoonan@mindspring.com (Thomas A. Coonan) wrote: > > > My > > >passing thought was just that if you could define a new set of > > >Synopsys library cells that were the macros, you could actually get > > >Synopsys to "synthesize" the configuration (you would still have to > > >then translate this netlist into the configuration data). Just a > > >passing thought - I don't really expect this is easy or even doable. > > >We can drop the "synthesis" for FP configuration idea, and instead > > >try to come up with the FP Macros that are reasonable to configure > > >by hand... > > > > > I think you can use any one of the OSS synthesis programs to generate output > to > > program your FP macros. Berkeley has nice tools. > > > > >ASIC to this (1-4%). For example, coming up with an IP (e.g. Internet > > >Protocol not the other IP!) packet filter on a downstream path that is > > >usable by the software people can be a challenging problem. One can > > >come up with all kinds of ad-hoc circuits that, in the end, prove > > >inadequete. A filter that's reconfigurable may have a better chance > > >of begin used. > > > > If you have a well defined application, adding programmability or flexibility > to > > it is simpler. You can even create a semi-fixed state machine and let the user > > decide on where and on what condition the transitions will be. A generic FP > macro > > might be an over kill for your specific app and it also might be too > difficult to > > use. > > > > muzo > > > > WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net> > > > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12993
>Gentlemen, > >It seems you have a good dialog going on here: I have one question which I >am still searching for an answer to: For what application would you like to >integrate an FPGA type architecture into an ASIC? > >Assume that the tools (whether Xilinx, Altera, or another) to support the >configuration of the FPGA architecture were available. > >I know that Lucent offer a hybrid FPGA/Gate Array device, but I am >struggling to conceive of an application where it would make sense. Considering that many uC applications end up using programmible logic 'glue' to interface the CPU to whatever it's supposed to be controlling, a combination CPU/FPGA would seem ideal for a wide variety of embedded controllers.Article: 12994
Maxim Golov <mgolov@lucent.com> wrote in message
news:363F3F98.97AB128B@lucent.com...
>Simon,
>
>what surprises me a bit is that we do not see around processors with
>embedded FPGA (m.b. small one) on the chip. Or did I miss something?
>
Actually, there is something close to your requirements.
The Triscend E5 configurable processor family is based around the
industry-standard 8032 microcontroller and is fully code- and
instruction-set compatible with the 8051/8052, uses the same
compilers/assemblers, etc.
While the E5 does not contain FPGA logic, it does contain something that
we call "Configurable System Logic" or CSL for short. The big
difference between FPGAs/CPLDs and CSL is that the CSL functions are
tightly integrated with the processor's internal system bus. The CSL
matrix is ideal for creating custom "soft" peripherals such as
additional timers, pulse-width modulators, FIFOs, filters, serial ports,
or just about any other digital function with between 5,000 and 50,000
programmable logic "gates".
The CSL logic connects to the system bus via the "Configurable System
Interconnect" or CSI bus. A CSI bus socket provides the processor's
address and data bus plus the socket has built-in address decoding.
The address decoders allow you to decode a range of addresses from a
signle byte up to a 16M region. You can also further specify wether the
address space resides in code space, data space, or as one of the 8032's
internal registers, called Special Function Registers (SFRs). The CSI
bus socket provides a nice synchronous interface into the CSL logic.
Your peripheral receives address, data, and the address decode signal
all on the same clock edge. Your function then has a complete bus cycle
(25 ns on the 40 MHz part) to respond--either with data or by inserting
a wait-state.
Some general features of the Triscend E5 family include:
* Embedded, performance-enhanced, industry-standard 8032
microcontroller
- 40 MHz operation
- 4 clock cycles per instruction cycle (up to 10 MIPS performance)
- Similar to the Dallas 80C320 microcontroller
- Uses third-party assembers, compilers, debuggers
* Configurable System Logic Matrix
- Up to 3,200 Configurable System Logic Cells
- Each cell supports a four- to nine-input logic function,
flip-flop, memory, and bussing
- Build "soft" peripherals to create your own 8032 microcontroller
derivative
* Integrated high-peformance system bus
- Configurable System Interconnect (CSI) bus
- 40 Mbyte/sec data transfers
- Read/write data, address
- Built-in address decoding (up to 200 address selectors
per device)
- Wait-state support
- DMA request/acknowledge steering to/from peripherals
- Hardware breakpoint monitor/trigger
* 2-Channel DMA Controller
- 40 Mbytes/sec transfer rate
- Works with other system peripherals and CSL functions
* Embedded system SRAM
- Up to 40 Kbytes
- Independent of RAM available in CSL matrix
* Programmable I/O pins
- Up to 315 per device
- Input, Output, or Bidirectional
- Work in conjuction with processor or independently
* Memory Interface Unit
- Flexible memory control timing on WE-, CE-, and OE-
- Programmable timing on setup, strobe width, and hold time
- Glueless support for 256Kx8 FLASH
There is additional information available on-line at the following
addresses:
Web-Based Configurable Processor Learning Center:
http://www.triscend.com/learning/
Triscend E5 Configurable Processor Data Sheet:
http://www.triscend.com/products/IndexWhitePaper.html
Preview Version of Triscend FastChip Development Software:
http://www.triscend.com/products/IndexSoftware.html
--------------------------------------------------------------------
/\ Steven K. Knapp sknapp@triscend.com
/\/ \ Triscend Corp. Tel: 650-968-8668 ext. 166
/\/ / \ 301 N. Whisman Rd. FAX: 650-934-9393
/ / \ Mountain View, CA 94043 Web: http://www.triscend.com
U.S.A
--------------------------------------------------------------------
Article: 12995Joel, Are you doing a functional or a timing simulation in Foundation 1.5? The behaviour you are describing is to be expected at times when running a timing simulation. The reason is that many of the nodes in the schematic get absorbed into look-up-tables in the Xilinx CLBs. So... when you place a probe on such a net, the simulator cannot find that node in it's netlist (which is a back-annotated timing netlist from the Xilinx tool). Follow the net back to a flop or pad (or forward to a flop or pad), and see if placing a probe at those points work better. If you need to do a functional simulation, and you haven't edited (saved) the top level of the schematic since the last place and route, you will probably have to manually load the .alb netlist in the simulator. Good luck, John -- John DeHaven Insight Electronics Xilinx-Dedicated Senior FAE PH: (503)644-3300 -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12996
alpha wrote: > What I hope to be able to do is generate VGA color signals with a Xilinx > FPGA so that I can directly drive a VGA monitor. I also want to be able to > add an interface for a mouse so that the Xilinx chip can display the mouse > pointer on the monitor. I will probably need some D/A converters in order to > generate the analog signals for the VGA monitor, but I'm not quite sure > where to start. This has been done (amongst others, no doubt) by Embedded Solutions Ltd as part of some demonstrators for their Handel-C high-level HDL. But they made a bit of a pig's ear of generating the analog signals. Try www.embedded-solutions.ltd.uk for info. It's actually fairly simple. You need to generate TTL vertical sync, horizontal sync and three colour analog video signals. There is a good deal of coming and going about the polarity and timing of the syncs but there are two bits of good news: (1) most modern monitors will lock on to just about anything sensible, and (2) user manuals for VGA monitors often have some info. on the sync timing, to a good enough level of detail to allow you to fake up the signals. A quick peep with a scope on the outputs of your PC's video connector will help no end, too. The analog stuff is easier than it sounds unless you are looking for rather good quality. You can of course use a video DAC if you wish, but the CMOS outputs on FPGAs swing rail-to-rail and if you are happy with fewer than 8 bits of precision on each of the three colours you can build a R-2R ladder for a few cents: * | FPGA OUTPUTS | * |______q0____q1____q2____q3__| * | | | | * | | | | * R R R R * | | | | * 0V __R__|__r__|__r__|__r__|____ output where the resistors labelled R are exactly twice the value of the resistors labelled r. If you choose r=300, R=600 ohm then the output will divide itself down to exactly the required 1V swing when loaded by the 75 ohm inputs of the monitor. You can go on adding ladder stages as long as you want, but the precision of such "digital DACs" is a bit rough (the 5V supply inside the FPGA may be a bit ropey) and it probably isn't worth going beyond 6 bits. HTH Jonathan Bromley (no connection with Embedded Solutions Ltd, just a fan)Article: 12997
Hi! Is there a simple way to identify a an asynch feedback loop with Xilinx Foundation 1,4 software? I have a few loops in a design as reported by trace, but the problem is that I would like to know what nets are in the loop path. Thanks, Jonas ThorArticle: 12998
You might want to take a look at Oxford Universities Hardware Compilation Group pages. They did a few examples driving VGA monitors (more or less directly, modulo some resistors to do the D-to-A conversion). They use a C-like programming language to develop the FPGA netlist, which makes it very straight forward to get a VGA driver up and running. The URLs are: http://www.comlab.ox.ac.uk/oucl/hwcomp.html http://www.comlab.ox.ac.uk/oucl/groups/hwcweb/video/video_games.html Cheers, MatthiasArticle: 12999
take a look at the new offering by Triscend. They've got an 8032 type microcontroller with some FPGA fabric on it to do exactly that. null@I.Hate.Spam wrote: > Considering that many uC applications end up using programmible logic 'glue' > to interface the CPU to whatever it's supposed to be controlling, a > combination CPU/FPGA would seem ideal for a wide variety of embedded > controllers. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka
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