Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
This is a multi-part message in MIME format. --------------014C7FCCC92EBA5769EEDAA8 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Brian Drummond wrote: > On 19 Nov 1998 08:26:03 +0000, Alistair McEwan <aam@pierrot.comlab> > wrote: > > > > > > >Hi, > > > >I am looking for sources of information on Content Addressable > >Memorys. In particular, I want to find up to date details and > >specifications of CAM chip suppliers and CAM boards. > > > Search for MUSIC Semiconductors. http://www.music-ic.com/Definetely MUSIC, but it may depend on your application.Motorola has dedicated CAM for ATM applications. GEC-Plessey used to have CAM (still active?) Note that the use of CAM should always be compared to using a variety of search techniques. CAM are very nice but also power hungry and using external ones is not always that simple because of the interface defined by MUSIC e.g. This would be specially important if you are using inside a FPGA. > > > - Brian --------------014C7FCCC92EBA5769EEDAA8 Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Marc Delvaux Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Marc Delvaux n: Delvaux;Marc org: GlobeSpan Semiconductors adr: 100 Schulz Drive;;;Red Bank;NJ;07701;USA email;internet: mdel@globespan.net title: LSI designer tel;work: +1 (732) 345 7502 tel;fax: +1 (732) 345 7592 tel;home: +1 (732) 578 9255 x-mozilla-cpt: ;0 x-mozilla-html: TRUE version: 2.1 end: vcard --------------014C7FCCC92EBA5769EEDAA8--Article: 13201
ds12 wrote: > > do you know if it is possible to test/control a run-time reconfigurable > design using VHDL? > > and how would you go about doing that? I've done several testbenches that use a simulation control file to support configuration, running specific tests, etc.. it takes some work, but here's how to do it: 1. create a simulation control file with a known format, ie each line contains a keyword with known parameters. let's say you want to write to some registers and then run a test, then write in different values and run the same test, your control file might look like: write 0001 ff99 -- write <address> <data> write 0002 ff99 trans -- do a transmit write 0001 ff88 -- write in new data write 0002 ff88 trans -- do another transmit 2. set up the testbench to read in the control file (this example is in VHDL '87) and do some action based on the data read in. This example supports the control file format above: LIBRARY ieee; USE ieee.std_logic_1164.all; USE std.textio.all; ENTITY design_tb IS END; ARCHITECTURE testbench OF design_tb IS .... BEGIN MAIN : PROCESS file sim_control : text is in simctl.txt -- this file contains the tb info variable InLine : line; -- a pointer to the line of info in the file variable Mode : string(1 to 5); -- space to hold the test variable Address : string(1 to 4); -- space to hold the address for a write variable Data : string(1 to 4); -- space to hold the data for a write variable LineCount : natural := 0; -- space to keep track of what line you are on BEGIN IF endfile (sim_control) THEN ASSERT false REPORT "Error opening control file" SEVERITY error; WAIT; END IF; WHILE NOT endfile (sim_control) LOOP -- get the next line of info from the control file ReadLine(sim_control,InLine); LineCount := LineCount + 1; Mode := InLine.all(1 to 5); -- switch on the Mode to see what to do CASE Mode IS -- don't put parentheses around Mode WHEN "write" => -- put quotes around each string Address := InLine.all(7 to 10); Data := InLine.all(12 to 15); -- do the write WriteProcedure(Address,Data,....); WHEN "trans" => -- do the transmit TransmitData(....); WHEN others => NULL: END CASE; -- after all the tests have been completed, suspend the process WAIT; END PROCESS Main; This is a very basic example. There are many more advanced things that can be built upon this simple framework. As always, let me know if you have any questions. .Mj. mailto:mjenkins@iastate.edu -- Learn from the mistakes of others...you can't live long enough to make them all yourself.Article: 13202
Dies ist eine mehrteilige Nachricht im MIME-Format. --------------2BAE75FF41FC3B298204994C Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit I designed and optimized a DES with 16 loops in VHDL for Xilinx FPGA. The unconstrained synthesis resulted in 227 CLBs on a XC4020-3 and a speed of 23.5 MHz = 94Mbits/s. I also implemented a interface for a 8051µC and in such a way the DES can work as coprocessor. -- Mathias Schmalisch sm15@e-technik.uni-rostock.de --------------2BAE75FF41FC3B298204994C Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Visitenkarte für Mathias Schmalisch Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Mathias Schmalisch n: Schmalisch;Mathias org: University Rostock email;internet: sm15@e-technik.uni-rostock.de x-mozilla-cpt: ;0 x-mozilla-html: FALSE version: 2.1 end: vcard --------------2BAE75FF41FC3B298204994C--Article: 13203
Ray Andraka wrote: > The M1 tools do not use the xnf format. They do currently have the > ability to import xnf files, but there is no guarantee this will be > supported in future releases. > > Utku Ozcan wrote: > > > I have heard that Xilinx won't support XNF. Is this true? > > > > Utku > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka So, what will happen with Coregen ? Michel.Article: 13204
Ray Andraka wrote: > > That flip flop doesn't have to be set/reset on the transition to the equal state. > It can be set/reset based on a gross comparison of the read and write counters. The > trick is if the fifo is more than half full, it will be full when the pointers > become equal unless it first becomes less than half full and vice-versa. Where I > work in schematics, I don't have a synthesizable version of this. > > Johnny Smooth wrote: > > > Ray Andraka wrote in message <3652DA19.BD7F31CE@ids.net>... > > >Not so smooth there Johnny, > > > > > >You don't need storage for N+1 words for an N deep fifo. Read=Write means > > either > > >empty or full. The direction this condition was entered from differentiates > > the > > >two conditions. This uses an extra flip-flop in the control logic, but has the > > > > And what might you clock it with? That little flipflop is the problem. Because > > the > > two interfaces are asynchronous AND the flags must be valid AT ALL TIMES, > > there is really no good safe way to know what the last op was. Have you tried I believe your original objection to Johnny's method was that he was using an arithmetic compare in order to set the full/empty flags (in addition to wasting one location of memory). But your "gross comparison" will require an arithmetic compare of the two pointers, no? I think that Johnny may be right about a simpler circuit. When the two clocks are asynchronous, you can never make an assumption about when the output of both counters are stable. So the arithmetic compare would be very difficult. On the other hand, a gray coded counter could be examined for equality without worring about races. With only a single bit changing, you will either see the old value or the new value. I believe Johnny needed a compare of A+1 = B. This can be done by using the D inputs to the A counter FFs since the D inputs will always have the next value on them (A+1). So this also becomes an equality compare. So then the only problem is the metastability issue. Of course the best way to handle this is to synchronize one of the inputs to the clock of the other and run the entire FIFO from that clock. That is what I did in my last design. But I am sure that is not an available solution in many cases. -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 13205
Hi, I just converted a working, in production, design from the 5.2/6 tools over to the new M1.5 (with updates) tools. The design made all but three TIMESPECs with the old tools (and these TIMESPECS it didn't make were intentional...), yet with the supposed 'new and improved' tools, it could do no better than 14 missed TIMESPECS. Very dissappointing. Anyone else have similar experiences? Also, EPIC is very awkward to use, and is missing some very very usefull features the old XACT/XDE tool has, like probes.... Is there a DOS based download program with the new tools (I guess I could use the old XCHECKER???), or do I have to convert all the 486/16M/120M DOS notebooks we use in the lab for downloading over to CD based (NT only comes on CD) NT machines??? Does anyone else feel these new tools are a giant step backwards in functionality and usability? Austin Franklin darkroom@ix.netcom.comArticle: 13206
This is a multi-part message in MIME format. --------------B15BDFF9F619397CF1E8A486 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hello anybody and everybody! I have been working on a complex host/daughter card system for the PCI bus which is using a total of 5 Xilinx FPGA's along with a host of other components. We chose the XL series of the 4000 architecture for the extended RAM features and Versa-ring routing. As it happened the smaller devices of the family are only available in the low voltage XL versions. Now that I have been attempting to implement the designs I am finding major problems with designs that are logically correct but do not function as expected in the real world. These designs pass the timing constraints I'm using but do not function at all or stop in the middle of processing loops. At times the state machines hold in an apparent meta-stable state. I have found conditions where active signals associated with completely separate logic functions effect the operation of state machines in the same device. I have also found a condition where the logic will function only if the 3.3 VDC supply to the Xilinx devices is raised to 3.52 VDC, and not below. Is anyone experiencing the same type of problems with this or any other device family from Xilinx. P.S. Long live Altera!! John J. Hovey ARL: University of Texas --------------B15BDFF9F619397CF1E8A486 Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for John Hovey Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: John Hovey n: Hovey;John email;internet: hovey@arlut.utexas.edu x-mozilla-cpt: ;0 x-mozilla-html: FALSE version: 2.1 end: vcard --------------B15BDFF9F619397CF1E8A486--Article: 13207
> Now that I have been attempting to implement the designs I am finding > major problems with designs that are logically correct but do not > function as expected in the real world. These designs pass the timing > constraints I'm using but do not function at all or stop in the middle > of processing loops. At times the state machines hold in an apparent > meta-stable state. Did you do functional simulation to verify that your design works in the first place? What front end are you using (an HDL or schematic)? It sounds to me like you have two possible problems. First, if you are using an HDL, the HDL may not be giving you the results you believe you 'should' be getting. This can be either to wrong code, or erroneous HDL compilation. Secondly, sounds like you have timing problems, dispite your belief you make timing. Are you sure you have ALL your timing paths specified, and did you verify that all the paths are correct? Austin Franklin darkroom@ix.netcom.comArticle: 13208
You can try the following Web Site:http://www.xess.com/FPGAKarl -**** Posted from Supernews, Discussions Start Here(tm) ****- http://www.supernews.com/ - Host to the the World's Discussions & UsenetArticle: 13209
Hello I have designed I2C circuit on Xilinx XC42XXE FPGA. I lost the simulation file but I have a hardcopy. If you would like to read the source, email to me and I will reply to you ----- email: leslieyip@ctimail.com In article <36519683.EF48F3E3@yahoo.com>, Rickman <spamgoeshere4@yahoo.com> wrote: > Le mer Michel wrote: > > > > ovilup wrote: > > > > > Hello ! > > > > > > I am working on an I2C controller. Now, I am designing the > > > internal clock generator. I have an 1.5 MHz internal clock, > > > from which I have to generate the 100 KHz, 90 KHz, 44 KHz > > > 1.5 KHz SCL clocks. > > > > > > Any examples of such an clock generator would be appreciated ! > > > > > > Thank you in advance. > > > OL > > > > Hello > > > > I do not know exactly what it is but I heard about the direct numeric > > synthesis. It is use in the signal generators to privide a wave of a > > specific frequency. > > > > Bye. > > Michel. > > If I may add my two cents worth to the thread. NCO and DDS are the same > in this context. Both use an phase angle accumulator with a constant > phase step. The output of the phase accumulator can be used directly by > picking the top bit, or by using some number of top bits to generate a > sine wave via a translation table. This digital sine wave would be > converted to an analog signal via a DAC, filtered to remove the "jitter" > component, and run into a comparator to generate a symetrical square > wave, jitter free clock. This is a lot of work for what Ovilup is doing. > > Unfortunately, OL's frequencies are not exact multiples, so that you > can't just divide the 1.5 MHz down to get 90 kHz or 44 kHz exactly. So a > slightly different master frequency is needed or one of the above > methods need to be used, depending on the accuracy required. > > -- > > Rick Collins > > redsp@XYusa.net > > remove the XY to email me. > -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 13210
Below is the Synthesiable code of 3-level FIFO on ALtera. For the simulation
file and waveform file, email to me.
Leslie Yip
CityU of Hong Kong
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Entity FIFO is
port( NRST: in std_logic;
WR,RD: in std_logic;
DIN: in std_logic_vector(15 downto 0);
EMPTY,FULL: out std_logic;
DOUT: out std_logic_vector(15 downto 0)
);
end FIFO;
architecture FIFO_ARCH of FIFO is
type RAM_TYPE is array(2 downto 0) of std_logic_vector(15 downto 0);
signal WCNT,RCNT: std_logic_vector(1 downto 0); --integer range 0 to 2;
signal T_WCNT,T_RCNT: integer range 0 to 2;
signal MEM: RAM_TYPE := RAM_TYPE'(
"0000000000000000",
"0000000000000000",
"0000000000000000"); -- FIFO memory
-- signal DWEN,DDWEN,RWEN : std_logic;
-- signal DOE,DDOE,ROE : std_logic;
-- signal TDOUT : std_logic_vector(15 downto 0);
begin
process(NRST,WR)
begin
if NRST = '0' then
for i in MEM'range loop
MEM(i)<= (others=>'0');
end loop;
elsif WR='1' and WR'event then
MEM(T_WCNT) <= DIN;
end if;
end process;
T_WCNT <= conv_integer(WCNT);
T_RCNT <= conv_integer(RCNT);
process(NRST,WR)
begin
if NRST='0' then
WCNT <= "00";
elsif WR='1' and WR'event then
if WCNT = 2 then
WCNT <= "00";
else
WCNT <= WCNT +1;
end if;
end if;
end process;
process(NRST,RD)
begin
if NRST='0' then
RCNT <= "00";
elsif RD='1' and RD'event then
if RCNT = 2 then
RCNT <= "00";
else
RCNT <= RCNT + 1;
end if;
end if;
end process;
--process(NRST,REN)
--begin
-- if REN='1' then
-- DOUT <= TDOUT;
-- else
-- DOUT <= (others=>'Z');
-- end if;
--end process;
DOUT <= MEM(T_RCNT);
process(WCNT,RCNT)
begin
if WCNT = RCNT then
EMPTY <= '1';
else
EMPTY <= '0';
end if;
if (RCNT=0 and WCNT=2) or
(RCNT=1 and WCNT=0) or
(RCNT=2 and WCNT=1) then
FULL <= '1';
else
FULL <= '0';
end if;
end process;
end FIFO_ARCH;
In article <3650C15B.BBA0EC00@worldnet.att.net>,
James LaLone <lalone@worldnet.att.net> wrote:
> Can someone shed light on building a fifo that can be synthesized?
> The pointers, and ram, are no problem. What I'm having problems with
> are the flags. Of course, the fifo that I want to build have
> asynchronous read and write clocks.
> I've looked over Xilinx applications XAPP051 and XAPP131, but they still
> leave me with some implementation questions.
>
> Thanks in advance,
> -Jim
>
-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own
Article: 13211Austin, The Xact6 floorplanner used to be useful as a viewer to show me where my RLOCs were. M1.5 can not even do that. (Now, I use Fliptronic's Chipview) M1.5 doesn't seem to have any good report to show which paths are not covered by any time specs, or multiple time specs. I do think the place and rout does a good job assuming Data Path RLOCs, and comprehensive time specs, and effort set to max and clean-ups set to 5. I've heard that the M1.5 default efforts are lower than Xact6, so give it a try at a higher effort, Cheers, Dave Decker Diablo Research Co. LLC Please use only one 'h' in mush. I'm trying to reduce the spam. "Animals . . . are not brethren they are not underlings; they are other nations, caught with ourselves in the net of life and time, fellow prisoners of the splendor and travail of the earth." Henry Beston - The Outermost HouseArticle: 13212
Depends on the size of the fifo. For a 16 deep fifo, you can use a pair of 2 bit gray counters for each pointer. The top one indicates which quadrant of the fifo the pointer is in, the bottom points to one of the four entries. The top halves of the two pointers feed one 4 lut to do the gross compare. Since the counters are gray coded, you don't have the multi-bit race problem. This works great for a 16 deep fifo. Bigger than that, and you get into more complexity. In that case, I suppose the cost of an extra word becomes a smaller percentage of the fifo so it may not be so bad. I don't often have a need for an async fifo deeper than 16 entries in an FPGA. Rickman wrote: > Ray Andraka wrote: > > > > That flip flop doesn't have to be set/reset on the transition to the equal state. > > It can be set/reset based on a gross comparison of the read and write counters. The > > trick is if the fifo is more than half full, it will be full when the pointers > > become equal unless it first becomes less than half full and vice-versa. Where I > > work in schematics, I don't have a synthesizable version of this. > > > > Johnny Smooth wrote: > > > > > Ray Andraka wrote in message <3652DA19.BD7F31CE@ids.net>... > > > >Not so smooth there Johnny, > > > > > > > >You don't need storage for N+1 words for an N deep fifo. Read=Write means > > > either > > > >empty or full. The direction this condition was entered from differentiates > > > the > > > >two conditions. This uses an extra flip-flop in the control logic, but has the > > > > > > And what might you clock it with? That little flipflop is the problem. Because > > > the > > > two interfaces are asynchronous AND the flags must be valid AT ALL TIMES, > > > there is really no good safe way to know what the last op was. Have you tried > > I believe your original objection to Johnny's method was that he was > using an arithmetic compare in order to set the full/empty flags (in > addition to wasting one location of memory). But your "gross comparison" > will require an arithmetic compare of the two pointers, no? I think that > Johnny may be right about a simpler circuit. When the two clocks are > asynchronous, you can never make an assumption about when the output of > both counters are stable. So the arithmetic compare would be very > difficult. On the other hand, a gray coded counter could be examined for > equality without worring about races. With only a single bit changing, > you will either see the old value or the new value. > > I believe Johnny needed a compare of A+1 = B. This can be done by using > the D inputs to the A counter FFs since the D inputs will always have > the next value on them (A+1). So this also becomes an equality compare. > > So then the only problem is the metastability issue. Of course the best > way to handle this is to synchronize one of the inputs to the clock of > the other and run the entire FIFO from that clock. That is what I did in > my last design. But I am sure that is not an available solution in many > cases. > > -- > > Rick Collins > > redsp@XYusa.net > > remove the XY to email me. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 13213
Ain't progress grand! I use the 6.02 whenever I can get away with it. Unfortunately since it doesn't support the newer devices that is becoming less often than I like. M1 is designed for the push-a- button-get-a-design crowd. Unfortunately, the attention given to making a push button thing work OK came at the price of the controls us expert users depend on. Yell, scream, kick etc. Xilinx might even notice you raising an objection. Just wait till austin discovers that m1 doesn't support all the legal mappings that 6.0 did, or that some designs that were placed and routed under 6.0 won't route at all under M1. I can just hear him now when he needs to massage the xnf file to do something like setting INIT= values (due to xilinx not supporting occurence attributes) and he discovers that the ngd is a closed format binary file. Austin Franklin wrote: > Hi, > > I just converted a working, in production, design from the 5.2/6 tools over > to the new M1.5 (with updates) tools. > > The design made all but three TIMESPECs with the old tools (and these > TIMESPECS it didn't make were intentional...), yet with the supposed 'new > and improved' tools, it could do no better than 14 missed TIMESPECS. Very > dissappointing. > > Anyone else have similar experiences? > > Also, EPIC is very awkward to use, and is missing some very very usefull > features the old XACT/XDE tool has, like probes.... > > Is there a DOS based download program with the new tools (I guess I could > use the old XCHECKER???), or do I have to convert all the 486/16M/120M DOS > notebooks we use in the lab for downloading over to CD based (NT only comes > on CD) NT machines??? > > Does anyone else feel these new tools are a giant step backwards in > functionality and usability? > > Austin Franklin > darkroom@ix.netcom.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 13214
Assuming you've done a thorough simulation and timing analysis, it sounds like you might have a signal integrity problem. First, make sure you've got a bypass cap on every vcc pin and close by at that. Check to make sure you clock(s) are clean. Ringing on the clock _will_ cause the symptoms you are describing, as will severe groundbounce. Most of all, don't panic. Xilinx parts are pretty good. If you feed them good power (none of the cheap discount stuff), keep their clocks clean, and load a verified design, they will work every time. John J. Hovey wrote: > Hello anybody and everybody! > > I have been working on a complex host/daughter card system for the PCI > bus which is using a total of 5 Xilinx FPGA's along with a host of other > components. We chose the XL series of the 4000 architecture for the > extended RAM features and Versa-ring routing. As it happened the > smaller devices of the family are only available in the low voltage XL > versions. > Now that I have been attempting to implement the designs I am finding > major problems with designs that are logically correct but do not > function as expected in the real world. These designs pass the timing > constraints I'm using but do not function at all or stop in the middle > of processing loops. At times the state machines hold in an apparent > meta-stable state. > I have found conditions where active signals associated with completely > separate logic functions effect the operation of state machines in the > same device. > I have also found a condition where the logic will function only if the > 3.3 VDC supply to the Xilinx devices is raised to 3.52 VDC, and not > below. > Is anyone experiencing the same type of problems with this or any other > device family from Xilinx. > > P.S. > > Long live Altera!! > > John J. Hovey > ARL: University of Texas > > ------------------------------------------------------------------------ > > John Hovey <hovey@arlut.utexas.edu> > > John Hovey > <hovey@arlut.utexas.edu> > Netscape Conference Address > Netscape Conference DLS Server > Additional Information: > Last Name Hovey > First Name John > Version 2.1 -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 13215
For now, check Atmel for EEprom alternatives to Xilinx OTP SPROMs. Look for Xilinx to announce FLASH reprogrammable SPROMs in 1H99. John In article <36534FB6.F5523F38@yordas.demon.co.uk>, Chris Eilbeck <chris@yordas.demon.co.uk> wrote: > Are there any serial EPROMs for use with Xilinx XC4k chips? The XC170x > chips seem not to have an erasable variant but I'd like to avoid the > wasted PCB space and adding jumpers etc. to change between a parallel > III cable for development and a regular EPROM for the semi-permanent > design. > > Chris > -- > Chris Eilbeck > mailto:chris@yordas.demon.co.uk > -- John DeHaven Insight Electronics Xilinx-Dedicated Senior FAE PH: (503)644-3300 -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 13216
Sounds like you have some serious problems. Some ideas: 1. Check your timing. That fact that raising voltage to the part makes it work sounds like you're on the hairy edge timing-wise. Learn how to use trace to run useful reports and make sure you've got all your paths covered. 2. If you're using HDL design entry read the Xilinx map and par reports to make sure critical logic is not getting ripped out. Code that simulates fine can sometimes synthesize to garbage. Read the trimming reports carefully and try to account for everything. Also look at CLB and FF usage and make sure it makes sense. 3. Make sure your global reset was implemented correctly and that your clocks were routed using global buffers. 4. Make sure you don't use the JTAG pins for general-purpose I/O. Prohibit these in your UCF file and terminate them on the board. I've never seen a Xilinx FPGA design that simulated correctly and met timing (assuming it was properly constrained) that did not work in the system. If it doesn't work then 99.99% of the time it's your fault, not the part or the tools. If you're so sold on Altera then why the change? Sometimes it's better to stay with what you know and love. Good luck. Give us a post when you figure it out. RJS "John J. Hovey" wrote: > > Hello anybody and everybody! > > I have been working on a complex host/daughter card system for the PCI > bus which is using a total of 5 Xilinx FPGA's along with a host of other > components. We chose the XL series of the 4000 architecture for the > extended RAM features and Versa-ring routing. As it happened the > smaller devices of the family are only available in the low voltage XL > versions. > Now that I have been attempting to implement the designs I am finding > major problems with designs that are logically correct but do not > function as expected in the real world. These designs pass the timing > constraints I'm using but do not function at all or stop in the middle > of processing loops. At times the state machines hold in an apparent > meta-stable state. > I have found conditions where active signals associated with completely > separate logic functions effect the operation of state machines in the > same device. > I have also found a condition where the logic will function only if the > 3.3 VDC supply to the Xilinx devices is raised to 3.52 VDC, and not > below. > Is anyone experiencing the same type of problems with this or any other > device family from Xilinx. > > P.S. > > Long live Altera!! > > John J. Hovey > ARL: University of Texas -- --------------------------- real addr: rsefton_@_home.com (remove the underscores) ---------------------------Article: 13217
In article <3653A41D.47B8C5D6@ids.net>,
Ray Andraka <no_spam_randraka@ids.net> wrote:
> That flip flop doesn't have to be set/reset on the transition to the equal
state.
> It can be set/reset based on a gross comparison of the read and write
counters. The
> trick is if the fifo is more than half full, it will be full when the pointers
> become equal unless it first becomes less than half full and vice-versa.
Where I
> work in schematics, I don't have a synthesizable version of this.
>
> Johnny Smooth wrote:
>
> > Ray Andraka wrote in message <3652DA19.BD7F31CE@ids.net>...
> > >Not so smooth there Johnny,
> > >
> > >You don't need storage for N+1 words for an N deep fifo. Read=Write means
> > either
> > >empty or full. The direction this condition was entered from
differentiates
> > the
> > >two conditions. This uses an extra flip-flop in the control logic, but has
the
> >
> > And what might you clock it with? That little flipflop is the problem.
Because
> > the
> > two interfaces are asynchronous AND the flags must be valid AT ALL TIMES,
> > there is really no good safe way to know what the last op was. Have you
tried
> > this,
> > or are you just speculating? It's a deceptive problem. I've revisited that
> > extra flipflop
> > several times, and for truly Asynchronous FIFOs, the cleanest approach I've
> > found is just to take the hit on the extra word and flag logic for the
guarantee
> > of
> > asynchronicity (wasn't that a Police album? :-) ). For a custom CMOS
FIFO I
> > designed,
> > I did come up with a circuit based on SR latches and an EQUAL signal to
generate
> > the flags, but that was far from synthesizable. Again, this is for small
> > FIFOs (tens of words); for larger FIFOs, use a synchronous controller for a
> > RAM in the middle, and use small asynchronous FIFOs on the front and back.
> > If you can synchronize one port to the internal sync. FIFO, then bonus!
> >
> > I'll try to get a copy of my code from work and email it to you. If you
have a
> > better
> > solution, then I would certainly like to see it (and use it!).
> >
> > Thanks,
> > John
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930 Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka
>
>
Hi,
Here is a synthesizable version of xilinx xapp note 051. I have modified is a
bit. It is designed with several components and It works with leonardo. I
think that synopsys guys will have problem since their tools can handle this
level of VHDL.
In order to have use Virtex families one has only to write a new archtecture
of the dual-port RAM component which I have if someone is interested.
Have fun with it.
Göran Bilski
Enator Elektroniksystem AB
A lot of VHDL code
First some dual-port memory.
<Gen_DpRAM_e.vhd>
--===========================================================================
== -- Project : -- Filename : $RCSfile: Gen_DpRAM_e.vhd,v $ -- Designer :
Goran Bilski RDOE-GB(K) <gorbi@kairo.rld.smab> -- Version : $Revision: 1.2
$ -- Version Date : $Date: 1998/11/19 08:48:14 $ -- -- Description --
Implement a true Dual-Port RAM with a read port and a write/read port. --
The two ports works independent from each other. The read is asynchronously.
-- -- Signal Description -- -- Reset => Reset the DPRAM if possible! (True
for DFF implementation -- not true for xilinx) -- Addr1 => Write/Read
address -- WrClk => Write Clock -- DataIn => Data to write -- DataOut1
=> Data read by the address Addr1 -- Addr2 => Read address -- DataOut2 =>
Data read by the address Addr2 -- -- Change Log -- -- $Log: Gen_DpRAM_e.vhd,v
$ -- Revision 1.2 1998/11/19 08:48:14 qmwgobi -- Header modification -- --
Revision 1.1.1.1 1998/10/20 12:39:51 qmwgobi -- -- -- Revision 1.1
1998/02/25 13:21:51 gorbi -- Initial revision -- -- -- Copyright ******
Enator Elektroniksystem AB ******
--===========================================================================
== library IEEE; use IEEE.Std_Logic_1164.all;
entity Gen_DpRAM is
generic (
Use_Muxes : Boolean := False;
Mem_Size : Integer := 36;
Addr_Size : Integer := 6;
Data_Size : Integer := 16
);
port (
Reset : in Boolean;
-- Read/Write port 1
Addr1 : in Std_Logic_Vector(Addr_Size-1 downto 0);
WrClk : in Std_Logic;
WE : in Boolean;
DataIn : in Std_Logic_Vector(Data_Size-1 downto 0);
DataOut1 : out Std_Logic_Vector(Data_Size-1 downto 0);
-- Read port 2
Addr2 : in Std_Logic_Vector(Addr_Size-1 downto 0);
DataOut2 : out Std_Logic_Vector(Data_Size-1 downto 0)
);
end Gen_DpRAM;
<Gen_DpRAM_a.vhd>
--===========================================================================
== -- Project : -- Filename : $RCSfile: Gen_DpRAM_xilinx_a.vhd,v $ --
Designer : Goran Bilski RDOE-GB(K) <gorbi@kairo.rld.smab> -- Version :
$Revision: 1.2 $ -- Version Date : $Date: 1998/11/19 08:48:14 $ -- --
Description -- Implement a dual-port ram for the Xilinx 4000 family -- --
Signal Description -- -- -- -- Change Log -- -- $Log:
Gen_DpRAM_xilinx_a.vhd,v $ -- Revision 1.2 1998/11/19 08:48:14 qmwgobi --
Header modification -- -- Revision 1.1.1.1 1998/10/20 12:39:51 qmwgobi --
-- -- Revision 1.3 1998/08/20 11:35:28 kxriche -- Fixed address sizes to
Dual-Port RAM for Mem_Sizes smaller than 16 -- -- Revision 1.2 1998/03/03
08:49:00 gorbi -- Changed library Exemplar to library Work -- -- Revision
1.1 1998/02/25 13:26:16 gorbi -- Initial revision -- -- -- Copyright ******
Enator Elektroniksystem AB ******
--===========================================================================
== library IEEE; use IEEE.Std_Logic_1164.all; --use IEEE.Numeric_Std.all;
library Work; use Work.Exemplar_1164.all;
architecture XILINX_RTL of Gen_DpRAM is
component RAM16x1D
port (
a3,a2,a1,a0 : in Std_Logic;
dpra3,dpra2,dpra1,dpra0 : in Std_Logic;
we,wclk,d : in Std_Logic;
spo, dpo : out Std_Logic
);
end component;
component TBuf
port (
I : in Std_Logic;
T : in Std_Logic;
O : out Std_Logic
);
end component;
constant RAM_Banks : integer := 1 + ((Mem_Size - 1) / 16);
signal Write : Std_Logic_Vector(RAM_Banks-1 downto 0);
subtype Word is Std_Logic_Vector(Data_Size-1 downto 0);
type Mux_Level_Array is array(natural range <>) of Word;
signal RAM_Bank_Out1 : Mux_Level_Array(Ram_Banks-1 downto 0);
signal RAM_Bank_Out2 : Mux_Level_Array(Ram_Banks-1 downto 0);
signal RAM_Sel1 : Integer range Ram_Banks-1 downto 0;
signal RAM_Sel2 : Integer range Ram_Banks-1 downto 0;
signal Read1 : Std_Logic_Vector(Ram_Banks-1 downto 0);
signal Read2 : Std_Logic_Vector(Ram_Banks-1 downto 0);
signal Ram_Addr1 : Std_Logic_Vector(3 downto 0);
signal Ram_Addr2 : Std_Logic_Vector(3 downto 0);
-- function To_Integer(Arg : Std_Logic_Vector) return Natural is
-- variable XArg : Std_Logic_Vector(Arg'Length-1 downto 0) := Arg;
-- variable RESULT: NATURAL := 0;
-- begin
-- for I in XARG'RANGE loop
-- RESULT := RESULT+RESULT;
-- if XARG(I) = '1' then
-- RESULT := RESULT + 1;
-- end if;
-- end loop;
-- return RESULT;
-- end To_Integer;
function Mux_Tree(Datas : in Mux_Level_Array;
Selects : in Std_Logic_Vector) return Word is
variable Len,Middle : Integer;
variable Left,Right : Word;
begin
Len := Datas'LENGTH;
Middle := Len/2 + Datas'Right;
if Len = 1 then
return Datas(Datas'Left);
-- TBD Check that Selects'Length is ....
elsif Len = 2 then
if Selects(Selects'Left) = '0' then
return Datas(Datas'Left);
else
return Datas(Datas'Right);
end if;
else
Left := Mux_Tree(Datas(Datas'Left downto Middle),
Selects(Selects'Left-1 downto Selects'Right));
Right := Mux_Tree(Datas(Middle-1 downto Datas'Right),
Selects(Selects'Left-1 downto Selects'Right));
if Selects(Selects'Left) = '0' then
return Left;
else
return Right;
end if;
end if;
end Mux_Tree;
begin
RAM_Sel_Gen : if Ram_Banks > 1 generate
Ram_Sel1 <= evec2int(Addr1(Addr1'Left downto 4));
Ram_Sel2 <= evec2int(Addr2(Addr2'Left downto 4));
end generate;
Write_Select : process(WE,Ram_Sel1)
begin
Write <= (others => '0');
if WE then
if Ram_Banks > 1 then
Write(Ram_Sel1) <= '1';
else
Write(0) <= '1';
end if;
end if;
end process Write_Select;
Read1_Select : process(Ram_Sel1)
begin
Read1 <= (others => '0');
if Ram_Banks > 1 then
Read1(Ram_Sel1) <= '1';
else
Read1(0) <= '1';
end if;
end process Read1_Select;
Read2_Select : process(Ram_Sel2)
begin
Read2 <= (others => '0');
if Ram_Banks > 1 then
Read2(Ram_Sel2) <= '1';
else
Read2(0) <= '1';
end if;
end process Read2_Select;
Fixed_Addr_Bits : if Mem_Size >= 8 generate
Ram_Addr1(3 downto 0) <= Addr1(3 downto 0);
Ram_Addr2(3 downto 0) <= Addr2(3 downto 0);
end generate Fixed_Addr_Bits;
Align_to_4_Addr_Bits : if Mem_Size < 8 generate
Ram_Addr1(3 downto Addr1'Left+1) <= (others => '0');
Ram_Addr1(Addr1'Range) <= Addr1;
Ram_Addr2(3 downto Addr2'Left+1) <= (others => '0');
Ram_Addr2(Addr2'Range) <= Addr2;
end generate Align_to_4_Addr_Bits;
FIFO_RAM : for I in 0 to RAM_Banks-1 generate RAMBANKx : for J in 0 to
Data_Size-1 generate RAMx : RAM16x1D port map ( A3 => Ram_Addr1(3), A2 =>
Ram_Addr1(2), A1 => Ram_Addr1(1), A0 => Ram_Addr1(0), DpRA3 =>
Ram_Addr2(3), DpRA2 => Ram_Addr2(2), DpRA1 => Ram_Addr2(1), DpRA0 =>
Ram_Addr2(0), WE => Write(I), WClk => WrClk, D => DataIn(J), SpO =>
RAM_Bank_Out1(I)(J), DpO => RAM_Bank_Out2(I)(J) ); TBuffs : if not
Use_Muxes generate -- TBuf1x : TBuf port map ( RAM_Bank_Out1(I)(J),
Read1(I), DataOut1(J)); -- TBuf2x : TBuf port map ( RAM_Bank_Out2(I)(J),
Read2(I), DataOut2(J)); DataOut1(J) <= RAM_Bank_Out1(I)(J) when Read1(I) =
'1' else 'Z'; DataOut2(J) <= RAM_Bank_Out2(I)(J) when Read2(I) = '1' else
'Z'; end generate; end generate; end generate;
Muxes : if Use_Muxes generate DataOut1 <= RAM_Bank_Out1(0) when
(Addr1'Left < 4) else Mux_Tree(RAM_Bank_Out1,Addr1(Addr1'Left downto 4));
DataOut2 <= RAM_Bank_Out2(0) when (Addr2'Left < 4) else
Mux_Tree(RAM_Bank_Out2,Addr2(Addr2'Left downto 4)); end generate;
end XILINX_RTL;
Here is the actual FIFO <Gen_FIFO_e.vhd>
--===========================================================================
== -- Project : -- Filename : $RCSfile: Gen_FIFO_e.vhd,v $ -- Designer :
Goran Bilski RDOE-GB(K) <gorbi@kairo.rld.smab> -- Version : $Revision: 1.2
$ -- Version Date : $Date: 1998/11/19 08:48:15 $ -- -- Description --
Implements a synchronously FIFO with independent read and write ports. -- --
The Full flag will go true synchronously with the write clock and will go --
inactive asynchronously with the read clock. -- -- The Empty flag will go
true synchronously with the read clock and will go -- inactive
asynchronously with the write clock. -- -- The DataOut contains the present
data which means that when RD goes true the -- dataout contains the data and
will change at the next clock to the data to -- be read when RD goes active
next time.
-- Signal Description -- Reset => Sets the read and write pointer to zero
(Empties the FIFO) -- WrClk => The write data clock -- WE => True for
writing new data -- DataIn => New data to write to the FIFO -- Full =>
The FIFO is full anymore writing will result in undefined state -- RdClk =>
The read data clock -- RD => True for reading out new data from the FIFO --
DataOut => Data which HAS been read -- Empty => The FIFO is empty anymore
reading will result in undefined state -- -- -- Change Log -- -- $Log:
Gen_FIFO_e.vhd,v $ -- Revision 1.2 1998/11/19 08:48:15 qmwgobi -- Header
modification -- -- Revision 1.1.1.1 1998/10/20 12:39:51 qmwgobi -- -- --
Revision 1.2 1998/08/05 09:23:17 gorbi -- Added a Protect generic which
when true inhibits read when empty and -- write when full -- -- Revision 1.1
1998/02/25 13:34:42 gorbi -- Initial revision -- -- -- Copyright ******
Enator Elektroniksystem AB ******
--===========================================================================
== library IEEE; use IEEE.Std_Logic_1164.all;
entity Gen_FIFO is
generic (
WordSize : Integer := 16;
MemSize : Integer := 8;
Protect : Boolean := False
);
port (
Reset : in Boolean;
-- Clock region WrClk
WrClk : in Std_Logic;
WE : in Boolean;
DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
Full : out Boolean;
-- Clock region RdClk
RdClk : in Std_Logic;
RD : in Boolean;
DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
Empty : out Boolean
);
end Gen_FIFO;
<Gen_FIFO_a.vhd>
--===========================================================================
== -- Project : -- Filename : $RCSfile: Gen_FIFO_a.vhd,v $ -- Designer :
Goran Bilski RDOE-GB(K) <gorbi@kairo.rld.smab> -- Version : $Revision: 1.3
$ -- Version Date : $Date: 1998/11/19 08:48:14 $ -- -- Description --
Implements a FIFO using dual-port RAMS -- -- Signal Description -- -- -- --
Change Log -- -- $Log: Gen_FIFO_a.vhd,v $ -- Revision 1.3 1998/11/19
08:48:14 qmwgobi -- Header modification -- -- Revision 1.2 1998/10/26
10:56:53 qmwgobi -- Added MemSize of 256. -- Ignoring reads when empty and
writes when full -- -- Revision 1.1.1.1 1998/10/20 12:39:51 qmwgobi -- --
-- Revision 1.3 1998/08/05 09:27:37 gorbi -- Added a Protect generic which
when true inhibits read when empty and -- write when full -- Done some
cosmetics changes with the code -- -- Revision 1.2 1998/06/25 06:45:49
gorbi -- Updated from Peter Alfke app.note -- Added my updown counter -- --
Revision 1.1 1998/02/25 13:35:25 gorbi -- Initial revision -- -- --
Copyright ****** Enator Elektroniksystem AB ******
--===========================================================================
== library IEEE; use IEEE.Std_Logic_1164.all; use IEEE.Std_Logic_Arith.all;
library Syntes_Lib; use Syntes_Lib.all;
architecture VHDL_RTL of Gen_FIFO is
-----------------------------------------------------------------------------
-- A function which tries to calculate the best Mem_Size and by that the
best -- counting scheme
-----------------------------------------------------------------------------
function Calculate_Right_Mem_Size (Mem_Size : in Natural) return Integer is
begin -- Calculate_Right_Mem_Size case Mem_Size is when 0 to 3 => assert
false report "To small FIFO" severity failure; return 0; when 4 to 16 =>
return 16; when 17 to 32 => return 32; when 33 to 48 => -- Check if to use
up/down counter instead of a true 6-bit grey counter -- It seems that the
up/down counter takes 9 more CLBs than a ordinary -- grey counter so if the
width is greater than 9 the up/down counter -- will save area if WordSize >
8 then return 48; else return 64; end if; when 49 to 64 => return 64;
when 65 to 256 => -- Do not yet need to check if to use the up/down counting
scheme since -- there is not true 7-bit counter implemented yet return
((MemSize+15)/16)*16; when others => assert false report "Unsupported FIFO
Depth (Not yet implemented)" severity failure; return 0; end case; end
Calculate_Right_Mem_Size;
-- Convert the FIFO memsize to memsizes in steps of 16
constant True_Mem_Size : Integer := Calculate_Right_Mem_Size(MemSize);
component Gen_DpRAM
generic (
Use_Muxes : Boolean := False;
Mem_Size : Integer := 36;
Addr_Size : Integer := 6;
Data_Size : Integer := 16
);
port (
Reset : in Boolean;
-- Read/Write port 1
Addr1 : in Std_Logic_Vector(Addr_Size-1 downto 0);
WrClk : in Std_Logic;
WE : in Boolean;
DataIn : in Std_Logic_Vector(Data_Size-1 downto 0);
DataOut1 : out Std_Logic_Vector(Data_Size-1 downto 0);
-- Read port 2
Addr2 : in Std_Logic_Vector(Addr_Size-1 downto 0);
DataOut2 : out Std_Logic_Vector(Data_Size-1 downto 0)
);
end component;
----------------------------------------------------------------------
-- Returns the vector size needed to represent the X
-- The result is > 0
----------------------------------------------------------------------
function Vec_Size( X : in Natural) return Natural is
variable I : Natural := 1;
begin
while (2**I) < X loop
I := I + 1;
end loop;
return I;
end function Vec_Size;
-- Declare the types and constant counting schemes
subtype Count_Word is Std_Logic_Vector(3 downto 0);
type Count_Array_Type is array (integer range <>) of Count_Word;
-- Even if there is four bits for the Cnt8, the fourth bit will never be
used constant Cnt8 : Count_Array_Type(0 to 7) := (
"0000","0001","0011","0010", "0110","0111","0101","0100"); constant Cnt10 :
Count_Array_Type(0 to 9) := ( "0000","1000","1001","0001",
"0011","0010","0110","0111", "0101","0100" ); constant Cnt12 :
Count_Array_Type(0 to 11) := ( "0000","1000","1001","1011",
"1010","0010","0011","0001", "0101","0111","0110","0100" ); constant Cnt14
: Count_Array_Type(0 to 13) := ( "0000","1000","1100","1101",
"1001","1011","1010","0010", "0011","0001","0101","0111", "0110","0100");
constant Cnt16 : Count_Array_Type(0 to 15) := ( "0000","0001","0011","0010",
"0110","0100","0101","0111", "1111","1110","1100","1101",
"1001","1011","1010","1000");
-----------------------------------------------------------------------------
-- A function that do all the boolean equations for a counting scheme --
given as a parameter -- The synthesis tool will unroll the loops and then do
the boolean equation -- minimization (hopefully the optimimal). -- At
present it only handles counting scheme with 4 bits due to the --
Count_Array_Type definition
-----------------------------------------------------------------------------
function Gen_Counter(Count_Scheme : in Count_Array_Type; Up : in Boolean;
Count : in Std_Logic_Vector) return Std_Logic_Vector is variable Temp :
Std_Logic; variable L : Integer range Count_Scheme'Range; variable Q :
Std_Logic_Vector(Count'Length-1 downto 0); variable Q_Temp :
Std_Logic_Vector(Count'Length-1 downto 0); begin -- Gen_Counter Q :=
Count; for G in Q'Range loop Q_Temp(G) := '0'; for I in Count_Scheme'range
loop if Count_Scheme(I)(G) = '1' then if Up then L := I - 1; else if I
/= Count_Scheme'High then L := I + 1; else L := Count_Scheme'Low; end if;
end if; Temp := '1'; for J in Q'Range loop if Count_Scheme(L)(J) = '1'
then Temp := Temp and Q(J); else Temp := Temp and not Q(J); end if; end
loop; Q_Temp(G) := Q_Temp(G) or Temp; end if; end loop; -- I end loop;
-- G return Q_Temp; end Gen_Counter;
-----------------------------------------------------------------------------
-- Implements the improved 32-depth FIFO counting scheme from the XAPP051
-----------------------------------------------------------------------------
function XAPP_Count_32 (Q : in Std_Logic_Vector(4 downto 0)) return
Std_Logic_Vector is variable Res : Std_Logic_Vector(4 downto 0); variable A
: Std_Logic; begin -- XAPP_Count_32 -- Do Peter Alfke improvement on XAPP
051 A := (Q(1) xnor Q(2)) and (Q(0) xor (Q(3) xor Q(4))); Res(0) := (Q(1)
and not A) or (Q(0) and A); Res(1) := (not(Q(0)) and not A) or (Q(1) and A);
Res(2) := ( (Q(3) xnor Q(4)) and A) or (Q(2) and not A); Res(3) := ( (
(Q(2) and Q(3)) or (not(Q(2)) and Q(4))) and A) or (Q(3) and not A); Res(4)
:= ( ( (Q(2) and not Q(3)) or (not(Q(2) and Q(4)))) and A) or (Q(4) and not
A); return Res; end XAPP_Count_32;
-----------------------------------------------------------------------------
-- Implements the improved 64-depth FIFO counting scheme from the XAPP051
-----------------------------------------------------------------------------
function XAPP_Count_64 (Q : in Std_Logic_Vector(5 downto 0)) return
Std_Logic_Vector is variable Res : Std_Logic_Vector(5 downto 0); variable A
: Std_Logic; begin -- XAPP_Count_64 -- Do Peter Alfke improvement on XAPP
051 A := (Q(1) xor Q(4)) and (Q(0) xnor Q(3)) and (Q(2) xnor Q(5)); Res(0)
:= ( (Q(1) xnor Q(2)) and not A) or (Q(0) and A); Res(1) := ( ( (not(Q(0))
and Q(2)) or (Q(0) and Q(1))) and not A) or (Q(1) and A); Res(2) := ( (
(Q(0) and not Q(1)) or (not(Q(0) and Q(2)))) and not A) or (Q(2) and A);
Res(3) := ( (Q(4) xnor Q(5)) and A) or (Q(3) and not A); Res(4) := ( (
(not(Q(3) and Q(5))) or (Q(3) and Q(4))) and A ) or (Q(4) and not A);
Res(5) := ( ( (Q(3) and not Q(4)) or (not(Q(3)) and Q(5))) and A ) or (Q(5)
and not A); return Res; end XAPP_Count_64;
----------------------------------------------------------------------
-- Generate the Address counter for FIFO handling
-- generates different counters depending of the counter size
----------------------------------------------------------------------
Procedure FIFO_Count( Count : inout Std_Logic_Vector;
Incr : in Boolean;
Up : inout Boolean;
Change : inout Boolean) is
variable Cnt : Std_Logic_Vector(Count'Left-Count'Right downto 0) := Count;
variable Res : Std_Logic_Vector(Count'Left-Count'Right downto 0) := Count;
begin
if True_Mem_Size = 16 then
if Incr then
Res := Gen_Counter(Cnt16,True,Cnt);
end if;
elsif True_Mem_Size = 32 then
if Incr then
Res := XAPP_Count_32(Cnt);
end if;
elsif True_Mem_Size = 48 then
-- Do a 2-bit grey counter + a grey counter which counts between 0 to 11
if Incr then
if not Change and
(( (Cnt(3 downto 0) = Cnt12(Cnt12'High)) and Up) or
( (Cnt(3 downto 0) = Cnt12(Cnt12'Low)) and not Up)) then
Res(5) := Cnt(4);
Res(4) := not Cnt(5);
Res(3 downto 0) := Cnt(3 downto 0);
Up := not Up;
Change := True;
else
Change := False;
Res(5 downto 4) := Cnt(5 downto 4);
Res(3 downto 0) := Gen_Counter(Cnt12,Up,Cnt(3 downto 0));
end if;
end if;
elsif True_Mem_Size = 64 then
if Incr then
Res := XAPP_Count_64(Cnt);
end if;
elsif True_Mem_Size = 80 then
-- Do a 3-bit grey counter + a grey counter which counts between 0 to 9
if Incr then
if not Change and
(( (Cnt(3 downto 0) = Cnt10(Cnt10'High)) and Up) or
( (Cnt(3 downto 0) = Cnt10(Cnt10'Low)) and not Up)) then
Res(6 downto 4) := Gen_Counter(Cnt8,True,Cnt(6 downto 4));
Res(3 downto 0) := Cnt(3 downto 0);
Up := not Up;
Change := True;
else
Change := False;
Res(6 downto 4) := Cnt(6 downto 4);
Res(3 downto 0) := Gen_Counter(Cnt10,Up,Cnt(3 downto 0));
end if;
end if;
elsif True_Mem_Size = 96 then
-- Do a 3-bit grey counter + a grey counter which counts between 0 to 11
if Incr then
if not Change and
(( (Cnt(3 downto 0) = Cnt12(Cnt12'High)) and Up) or
( (Cnt(3 downto 0) = Cnt12(Cnt12'Low)) and not Up)) then
Res(6 downto 4) := Gen_Counter(Cnt8,True,Cnt(6 downto 4));
Res(3 downto 0) := Cnt(3 downto 0);
Up := not Up;
Change := True;
else
Change := False;
Res(6 downto 4) := Cnt(6 downto 4);
Res(3 downto 0) := Gen_Counter(Cnt12,Up,Cnt(3 downto 0));
end if;
end if;
elsif True_Mem_Size = 112 then
-- Do a 3-bit grey counter + a grey counter which counts between 0 to 13
if Incr then
if not Change and
(( (Cnt(3 downto 0) = Cnt14(Cnt14'High)) and Up) or
( (Cnt(3 downto 0) = Cnt14(Cnt14'Low)) and not Up)) then
Res(6 downto 4) := Gen_Counter(Cnt8,True,Cnt(6 downto 4));
Res(3 downto 0) := Cnt(3 downto 0);
Up := not Up;
Change := True;
else
Change := False;
Res(6 downto 4) := Cnt(6 downto 4);
Res(3 downto 0) := Gen_Counter(Cnt14,Up,Cnt(3 downto 0));
end if;
end if;
elsif True_Mem_Size = 128 then
-- Do a 3-bit grey counter + a 4-bit grey counter
if Incr then
if not Change and
(( (Cnt(3 downto 0) = Cnt16(Cnt16'High)) and Up) or
( (Cnt(3 downto 0) = Cnt16(Cnt16'Low)) and not Up)) then
Res(6 downto 4) := Gen_Counter(Cnt8,True,Cnt(6 downto 4));
Res(3 downto 0) := Cnt(3 downto 0);
Up := not Up;
Change := True;
else
Change := False;
Res(6 downto 4) := Cnt(6 downto 4);
Res(3 downto 0) := Gen_Counter(Cnt16,Up,Cnt(3 downto 0));
end if;
end if;
elsif True_Mem_Size = 256 then
-- Do a 4-bit grey counter + a 4-bit grey counter
if Incr then
if not Change and
(( (Cnt(3 downto 0) = Cnt16(Cnt16'High)) and Up) or
( (Cnt(3 downto 0) = Cnt16(Cnt16'Low)) and not Up)) then
Res(7 downto 4) := Gen_Counter(Cnt16,True,Cnt(7 downto 4));
Res(3 downto 0) := Cnt(3 downto 0);
Up := not Up;
Change := True;
else
Change := False;
Res(7 downto 4) := Cnt(7 downto 4);
Res(3 downto 0) := Gen_Counter(Cnt16,Up,Cnt(3 downto 0));
end if;
end if;
else
assert false
report "To BIG FIFO (not yet supported)"
severity failure;
end if;
Count := Res;
end FIFO_Count;
Procedure FIFO_Counter( signal Count : inout Std_Logic_Vector; Incr : in
Boolean; Up : inout Boolean; Change : inout Boolean) is variable Res :
Std_Logic_Vector(Count'Left-Count'Right downto 0) := Count; begin
FIFO_Count(Res,Incr,Up,Change); Count <= Res; end FIFO_Counter;
---------------------------------------------------------------------- --
Generate the Address counter for FIFO handling -- generates different
counters depending of the counter size
---------------------------------------------------------------------- --
function FIFO_Cnt_Reset_Value(Count : in Std_Logic_Vector; -- Diff : in
Integer) return Std_Logic_Vector is -- variable Cnt :
Std_Logic_Vector(Count'Left-Count'Right downto 0) := "0000"; -- variable
Write : Boolean := True; -- variable Up : Boolean := True; -- variable
Change : Boolean := False; -- begin -- for I in 1 to Diff loop --
FIFO_Count(Cnt,Write,Up,Change); -- end loop; -- return Cnt; -- end
FIFO_Cnt_Reset_Value;
constant Log2_Mem_Size : Integer := Vec_Size(True_Mem_Size);
-- The read and write pointers
subtype Pointer_Type is Std_Logic_Vector(Log2_Mem_Size-1 downto 0);
signal Write_Ptr : Pointer_Type;
signal Read_Ptr : Pointer_Type;
signal Write_Addr : Pointer_Type;
signal Read_Addr : Pointer_Type;
signal DataOut1 : Std_Logic_Vector(WordSize-1 downto 0); -- NOT USED
signal Dir_Latched : Boolean;
signal Direction : Boolean;
signal Equal : Boolean;
signal Full_I : Boolean;
signal Empty_I : Boolean;
signal Full_Out : Boolean;
signal Empty_Out : Boolean;
signal Read : Boolean;
signal Write : Boolean;
-- constant Almost_Reset_Value : Pointer_Type :=
FIFO_Cnt_Reset_Value(Read_Ptr,P);
begin
-----------------------------------------------------------------------------
-- Change the Read and Write pointer to get the FIFO addresses -- This will
get the four lowest bits from the Read/Write pointers to be the -- higest
bits in FIFO addresses. This assures that when the FIFO depth is -- not a
power of 2, that the FIFO addresses is within the FIFO depth range
-----------------------------------------------------------------------------
Do_FIFO_Addr : process (Write_Ptr, Read_Ptr) begin -- process Do_FIFO_Addr
Write_Addr(Write_Addr'High downto Write_Addr'High-3) <= Write_Ptr(3 downto
0); if Write_Ptr'Length > 4 then Write_Addr(Write_Addr'High-4 downto
Write_Addr'Low) <= Write_Ptr(Write_Ptr'High downto 4); end if;
Read_Addr(Read_Addr'High downto Read_Addr'High-3) <= Read_Ptr(3 downto 0);
if Read_Ptr'Length > 4 then Read_Addr(Read_Addr'High-4 downto Read_Addr'Low)
<= Read_Ptr(Read_Ptr'High downto 4); end if; end process Do_FIFO_Addr;
----------------------------------------------------------------------
-- Instansiate the Dual Port memory
----------------------------------------------------------------------
FIFO_MEM : Gen_DpRAM
generic map(
Use_Muxes => false,
Mem_Size => MemSize,
Addr_Size => Log2_Mem_Size,
Data_Size => WordSize
)
port map (
Reset => Reset,
Addr1 => Write_Addr,
WrClk => WrClk,
WE => WE,
DataIn => DataIn,
DataOut1 => DataOut1,
Addr2 => Read_Addr,
DataOut2 => DataOut
);
Protect_FIFO : if Protect generate
Read <= Rd and not Empty_Out;
Write <= We and not Full_Out;
end generate Protect_FIFO;
Non_Protect_FIFO : if not Protect generate
Read <= Rd;
Write <= We;
end generate Non_Protect_FIFO;
----------------------------------------------------------------------
-- Read Pointer
----------------------------------------------------------------------
Read_Ptr_Counter : process(Reset,RdClk)
variable Up : Boolean;
variable Change : Boolean;
begin
if Reset then
Read_Ptr <= (others => '0');
Up := True;
Change := False;
elsif RdClk'Event and RdClk = '1' then
if not Empty_Out then
FIFO_Counter(Read_Ptr,Read,Up,Change);
end if;
end if;
end process Read_Ptr_Counter;
----------------------------------------------------------------------
-- Write Pointer
----------------------------------------------------------------------
Write_Ptr_Counter : process(Reset,WrClk)
variable Up : Boolean;
variable Change : Boolean;
begin
if Reset then
Write_Ptr <= (others => '0');
Up := True;
Change := False;
elsif WrClk'Event and WrClk = '1' then
if not Full_Out then
FIFO_Counter(Write_Ptr,Write,Up,Change);
end if;
end if;
end process Write_Ptr_Counter;
----------------------------------------------------------------------
-- Flag handling
----------------------------------------------------------------------
-------------------------------------------------------------------------
-- Dir_Latched is false after reset and then true after the first write
---------------------------------------------------------------------------
Direction_Latch : process(Reset,WE,WrClk)
begin
if Reset then
Dir_Latched <= False;
elsif WrClk'Event and WrClk = '1' then
Dir_Latched <= Dir_Latched or WE;
end if;
end process Direction_Latch;
-----------------------------------------------------------------------------
-- Trying to see if the read pointer is catching up the write pointer or --
vice verse -- The top two bits of the pointers always counts as follows --
00 -- 01 -- 11 -- 10 -- 00 -- .. -- So if read pointer is one step
behind the write pointer => Reset = True -- And if write pointer is one step
behind the read pointer => Set = True
-----------------------------------------------------------------------------
Direction_Proc : process(Read_Ptr,Write_Ptr,Dir_Latched,Direction) variable
Set : Boolean; variable Reset : Boolean; variable Read :
Std_Logic_Vector(1 downto 0); variable Write : Std_Logic_Vector(1 downto 0);
begin Read := Read_Ptr(Read_Ptr'Left) & Read_Ptr(Read_Ptr'Left-1); Write
:= Write_Ptr(Write_Ptr'Left) & Write_Ptr(Write_Ptr'Left-1); if (Read = "00"
and Write = "01") or (Read = "01" and Write = "11") or (Read = "11" and
Write = "10") or (Read = "10" and Write = "00") then Reset := True; else
Reset := False; end if; if (Write = "00" and Read = "01") or (Write = "01"
and Read = "11") or (Write = "11" and Read = "10") or (Write = "10" and
Read = "00") then Set := True; else Set := False; end if; Direction <=
not ((not Dir_Latched) or Reset or not(Set or Direction)); end process
Direction_Proc;
Equal <= (Read_Ptr = Write_Ptr);
Full_I <= Equal and Direction;
Empty_I <= Equal and not Direction;
-- Allow Empty to go active directly since the change is due to a read --
which means that the Empty_I is synchronized with RdClk. -- But is only
allow to go inactive when RdClk is High since the transaction -- is due to a
Write and Empty_I is NOT synchronized with RdClk. -- By this way the Empty
is not changed state just before rising edge of RdClk Empty_DFF :
process(Empty_I,RdClk) begin if Empty_I then Empty_Out <= True; elsif
RdClk'Event and RdClk = '1' then Empty_Out <= Empty_I; end if; end process
Empty_DFF;
Empty <= Empty_Out;
-- See above but for Full and WrClk
Full_DFF : process(Full_I,WrClk)
begin
if Full_I then
Full_Out <= True;
elsif WrClk'Event and WrClk = '1' then
Full_Out <= Full_I;
end if;
end process Full_DFF;
Full <= Full_Out;
end VHDL_RTL;
-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own
Article: 13218wluka@hotmail.com wrote: > Gentlemen, > It seems you have a good dialog going on here: I have one question which I am > still searching for an answer to: For what application would you like to > integrate an FPGA type architecture into an ASIC? > Assume that the tools (whether Xilinx, Altera, or another) to support the > configuration of the FPGA architecture were available. > I know that Lucent offer a hybrid FPGA/Gate Array device, but I am struggling > to conceive of an application where it would make sense. This would make perfect sense for me, even without breaking sweat :-) I've worked on applications where we used both ASICs and FPGAs (Xilinx) side by side. The ASIC was used for stuff that was common to several cards in the system and that was essential for getting the card up and running and the Xilinx for stuff where reconfigurations due to new specifications was expected. Some of those cards have been sold in large amounts, over 100k today. A single chip that would have taken care of both could probably have saved money, power and board space. /HenrikArticle: 13219
John, Suggestions: Thoroughly check static timing once again for sanity of worse case timing. XLNX has been known to issue device timing files that were overly aggressive relative to Silicon. When Silicon at customers or samples fail, they 'slow' down the device timing an re-release new timing files. You may want to ask them if this is the case. Others ideas would be to check with your synthesizer company regarding the SM synthesis for how it handles the CASE statement (if used) and OTHERS clauses. Your SM may be entering into an unrecoverable state due to timing problems of the device. Switch to Altera - Maxplus2 supposedly does min time analysis for hold violations using the Timing Analyzer in Fmax mode as well as worse case timing. Cheers. John J. Hovey wrote in message <3654A445.68D25580@arlut.utexas.edu>... >Hello anybody and everybody! > > I have been working on a complex host/daughter card system for the PCI >bus which is using a total of 5 Xilinx FPGA's along with a host of other >components. We chose the XL series of the 4000 architecture for the >extended RAM features and Versa-ring routing. As it happened the >smaller devices of the family are only available in the low voltage XL >versions. > Now that I have been attempting to implement the designs I am finding >major problems with designs that are logically correct but do not >function as expected in the real world. These designs pass the timing >constraints I'm using but do not function at all or stop in the middle >of processing loops. At times the state machines hold in an apparent >meta-stable state. > I have found conditions where active signals associated with completely >separate logic functions effect the operation of state machines in the >same device. > I have also found a condition where the logic will function only if the >3.3 VDC supply to the Xilinx devices is raised to 3.52 VDC, and not >below. > Is anyone experiencing the same type of problems with this or any other >device family from Xilinx. > >P.S. > >Long live Altera!! > >John J. Hovey >ARL: University of TexasArticle: 13220
I collect Big endian vs. little endian information at http://www.rdrop.com/~cary/html/endian_faq.html . I have the classic article ON HOLY WARS AND A PLEA FOR PEACE by Danny Cohen (1980) there. Highly recommended. I'm always astonished how many unexpected problems come from endian misunderstandings. I'm also kind of surprised at how many people say "Use little-endian" (or "Use Big-endian"), then try to justify it with some "reason" that applies equally well to the other format. Are there any *real* reasons to favor one over the other that I haven't already listed ? -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 13221
Austin Franklin wrote: > > > Also, EPIC is very awkward to use, and is missing some very very usefull > features the old XACT/XDE tool has, like probes.... The easiest way to add probes is to use a PERL script. I beleive I obtained it for M1.4 from the Xilinx web site. It's certainly not as good as having an integrated add probe command but it's better than having to configure all the bits of an IOB. (It basically generates a script file to do several things to an IOB from configuring it to adding a selected net). > > Is there a DOS based download program with the new tools (I guess I could > use the old XCHECKER???), or do I have to convert all the 486/16M/120M DOS > notebooks we use in the lab for downloading over to CD based (NT only comes > on CD) NT machines??? It can be run under 95 according to Xilinx (but I've not tried). > > Does anyone else feel these new tools are a giant step backwards in > functionality and usability? > In many ways I think that they're better, but there's room for improvement. -- Peter CrightonArticle: 13222
John J. Hovey wrote: > > Hello anybody and everybody! > > I have been working on a complex host/daughter card system for the PCI > bus which is using a total of 5 Xilinx FPGA's along with a host of other > components. We chose the XL series of the 4000 architecture for the > extended RAM features and Versa-ring routing. As it happened the > smaller devices of the family are only available in the low voltage XL > versions. > Now that I have been attempting to implement the designs I am finding > major problems with designs that are logically correct but do not > function as expected in the real world. These designs pass the timing > constraints I'm using but do not function at all or stop in the middle > of processing loops. At times the state machines hold in an apparent > meta-stable state. > I have found conditions where active signals associated with completely > separate logic functions effect the operation of state machines in the > same device. How are you designing your state machines? It may be that you have got to a state where more than one path out of that state is active, or alternatively no path is active. This is possible with the state editor program but requires the designer to define what exactly is required (after all the software will usually only do what you tell it, bugs excepted). > I have also found a condition where the logic will function only if the > 3.3 VDC supply to the Xilinx devices is raised to 3.52 VDC, and not > below. > Is anyone experiencing the same type of problems with this or any other > device family from Xilinx. Are you sure that you have a low voltage part? That sounds like the voltage at which 5V parts start to work. -- Peter CrightonArticle: 13223
Rickman <spamgoeshere4@yahoo.com> writes: > I believe Johnny needed a compare of A+1 = B. This can be done by using > the D inputs to the A counter FFs since the D inputs will always have > the next value on them (A+1). So this also becomes an equality > compare. Is this in A's clock domain or B's clock domain? If B's, the D inputs to A's FFs won't satisfy the "off by one at most" property because they're stabilising between clocks. -- JamieArticle: 13224
I assume the the PCI pins are in fast slew rate mode. Which package are you using, is it 32 or 64 bit PCI, and have you spaced out the PCI pins to limit ground bounce? I believe the standard Xilinx designs all do this. For testing purposes you might consider putting the PCI bus in slow slew rate mode. You don't have much chance of meeting timing, but if you are having ground bounce problems they should disappear. Are you running 3.3 or 5V PCI? If 3.3V you need to supply clamping diodes, and if you turn on the internal ones you lose your 5V tolerance. Steve
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z