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In article <3657cf9d.359868@news.megsinet.net>, msimon@tefbbs.com wrote: > I am working with the Xilinx Student Edition. > > I am using schematic capture. > > I have two input busses A[0..7] and B[0..7] > > I want to take A[4..7] and B[0..3] and make C[0..7]. > > How do I do this? > > Simon > > Simon, I assume you are using Foundation. I use ViewLogic, so don't know if compound bus names work in Foundation, but just wanted to show how this is done on the Alliance side of the world, in case it might work in Foundation. Note: in ViewDraw, the left most bit is MSB, so I'll modify your bus names accordingly. If we have bus A[7:0] and bus B[7:0] we can make a new bus just by plopping a bus section on the same page and labeling it: A[7:4],B[3:0]. This new bus would be functional for simulation and place and routs (although not backannotated or traceable as a single bus in simulation,) so there is no compelling need for another bus labeled 'C.' If you wanted one you would attach a BUF input to the bus labeled A[7:4],B[3:0] attach a new bus section to the BUF output and label it c[7:0]. Also, add an $ARRAY=8 attribute to the BUF so it becomes 8 buffers. Normally, BUF is only a semantic tool for changing net names. No actual chip resources are used so no additional delay is incurred. In ViewDraw, there would be no need to draw connections to the new busses. They are automatically connected by matching labels. For clarity here' how the bus signals would connect. A7 -> C7 (MSB) A6 -> C6 A5 -> C5 A4 -> C4 B3 -> C3 B2 -> C2 B1 -> C1 B0 -> C0 (LSB) I use this compound bus label feature of ViewLogic so much I don't know how I would manage without it. Hope something similar works for you. Dave Decker Diablo Research Co. LLCArticle: 13276
Hello,
A while ago, I designed a system which uses a 4010XL and 4028XL.
Now I need to order more components to build more boards. I have
seen that Xilinx has added the XLA series to their list. I am
wondering if I can just order the 4010XLA and 4028XLA devices to
fit the board. What things do I need to look at to verify this?
My understanding is that the XLA parts can handle the same
voltages as the XL in the same way (that is, no 5v power connections
are required). So, assuming that I recompile my designs for the
new logic, what else is needed?
[the XLA devices seem to be much cheaper and faster]
Cheers,
Jake
--
janovetz@uiuc.edu | Once you have flown, you will walk the earth with
University of Illinois | your eyes turned skyward, for there you have been,
| there you long to return. -- da Vinci
PP-ASEL | http://www.ews.uiuc.edu/~janovetz/index.html
Article: 13277Hi, just wondering if anyone out there knows of a site that discusses the differences between CPLD's and FPGA's? Thanks for info, PLEASE EMAIL, dddavids@topaz.iupui.eduArticle: 13278
David Wragg wrote: > > brian@shapes.demon.co.uk (Brian Drummond) writes: > > Consider for example, adding two numbers, in assembly language, with an > > 1 byte wide accumulator. You have to add the LSByte first, to get the > > "carry" for the next addition, and so on. That's a pain with a > > big-endian format, and an even bigger pain with a mixture of 16-bit and > > 32-bit big-endian... (do you look at address n+1 first, or n+3???) > > > > Byte order for a 64-bit (or greater) add would be: > > > > little-endian system: > > > > bytes 0,1,2,3,4,5,6,7 (...) > > > > big-endian system: > > bytes 1,0,3,2,5,4,7,6 (if it's a 16-bit machine) > > bytes 3,2,1,0,7,6,5,4 (if it's a 32-bit machine) > > Huh? Why would you store 64-bit numbers as a little-endian sequence of > big-endian words? > > There is a famous document called "On Holy Wars and a Plea for > Peace" (a web search will find it) which discusses big- > vs. little-endian, and the conclusion is that it doesn't much matter: > the important thing is to be consistent, from the word level on up (or > for serial communications, from the bit level on up). As your example > shows, inconsistant endianness at different levels causes pain. > http://www.rdrop.com/~cary/html/endian_faq.html AFAIK it was the first to use the names little-endian and big-endian, -- Lasse ---------------------------------------------------------- Lasse Langwadt Christensen, M.Sc. EE (to be in 1999) Aalborg University, Department of communication technology Applied Signal Processing and Implementation (ASPI) http://www.kom.auc.dk/~fuz , ICQ# 13068090Article: 13279
A wallace tree multiplier is not a good fit for an FPGA that has optimized ripple carry chains. Assuming no routing delays (which won't happen), a wallace tree implemented with a ripple carry adder for the final add has about the same delay as a tree of ripple adders. The wallace tree provides a gain when you use a faster adder for the final sum. The faster adders are more complex, so the wallace tree provides a savings in gate count for fast adder trees. Now, most FPGAs have an optimized ripple carry structure which provides enough of a performance advantage that it is very difficult and expensive to improve on the performance for typical bit widths. With this in mind, the best you can hope for with a wallace tree implemented in an FPGA is parity with an ripple adder tree. The wallace tree performance in an FPGA is further degraded by the irregular routing required to connect the carry save adders in the tree. The irregular routing leads to routing delays that are considerably longer than those encountered in the regular structure of a ripple adder tree. For a more detailed discussion of multiplier designs for FPGAs, you might refer to the multiplier page on my website. Mohsin Riaz wrote: > Hi there! > > Why don't you go for a Wallace tree multiplier design, which is quite > suitable for implementation in FPGAs. In fact, i have also synthesized a > 32 x 32 binary multiplier that is based on the Wallace tree design. Its > a purely structural design.Its a fast impementation too!! > > Mohsin Riaz > > Computers & Communication Security Lab, > Faculty Of Engineering, > Memorial University Of Newfoundland, > St.John's,Newfoundland,Canada. > email:mohsin@engr.mun.ca > Web:www.engr.mun.ca/~mohsin > > On Mon, 16 Nov > 1998 smeiyapp@my-dejanews.com wrote: > > > Try some floating point circuits. They are challenging and > > you will *LEARN* a heck of a lot in modelling! > > > > In article <72g0mm$uud$1@nnrp1.dejanews.com>, > > leslie.yip@asmpt.com wrote: > > > Hello > > > > > > I think that a 16-bit x 16-bit binary multiplier will be quite challenging. > > > After you implemented your project, would you place on the web site or give me > > > to have a look? > > > > > > Leslie Yip > > > > > > In article <3ej22.1081$4S.3996@weber.videotron.net>, > > > "Stephane Marcouiller" <mars02@gel.usherb.ca> wrote: > > > > I have to find a suitable VHDL project for my course Computer Architecture > > > > II > > > > Suggestions are welcome > > > > > > > > Currently I have a couple of ideas like : branch prediction buffer, > > > > pipelined CPU, L1 et L2 cache,... > > > > > > > > Do you have other ideas ? > > > > > > > > P.S. It must be possible to do it whitin 3 weeks * 5 hours/week = 15 hours > > > > approx. > > > > > > > > Thx > > > > > > > > > > > > > > -----------== Posted via Deja News, The Discussion Network ==---------- > > > http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own > > > > > > > -----------== Posted via Deja News, The Discussion Network ==---------- > > http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own > > > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 13280
I use compound busses extensively in viewlogic too. Last time I tried it in foundation, it was broken so you had to use the bus elements or buffers. I believe compound busses may work now in foundation. Anybody out there using foundation that knows for sure? Unfortunately foundation is still very awkward and toy-like when compared with viewlogic. Even more unfortunate, the foundation viewlogic import is not anywhere near bullet-proof, so translation of a design from viewlogic to foundation so that a customer without viewlogic can maintain a design cheaply is a royal pain in the patoot. Dave Decker wrote: > In article <3657cf9d.359868@news.megsinet.net>, > msimon@tefbbs.com wrote: > > I am working with the Xilinx Student Edition. > > > > I am using schematic capture. > > > > I have two input busses A[0..7] and B[0..7] > > > > I want to take A[4..7] and B[0..3] and make C[0..7]. > > > > How do I do this? > > > > Simon > > > > > Simon, > > I assume you are using Foundation. I use ViewLogic, so don't know if compound > bus names work in Foundation, but just wanted to show how this is done on the > Alliance side of the world, in case it might work in Foundation. > > Note: in ViewDraw, the left most bit is MSB, so I'll modify your bus names > accordingly. > > If we have bus > A[7:0] and bus > B[7:0] > we can make a new bus just by plopping a bus section on the same page and > labeling it: > A[7:4],B[3:0]. > > This new bus would be functional for simulation and place and routs (although > not backannotated or traceable as a single bus in simulation,) so there is no > compelling need for another bus labeled 'C.' If you wanted one you would attach > a BUF input to the bus labeled A[7:4],B[3:0] attach a new bus section to the > BUF > output and label it c[7:0]. Also, add an $ARRAY=8 attribute to the BUF so it > becomes 8 buffers. > > Normally, BUF is only a semantic tool for changing net names. No actual chip > resources are used so no additional delay is incurred. > > In ViewDraw, there would be no need to draw connections to the new busses. They > are automatically connected by matching labels. > > For clarity here' how the bus signals would connect. > A7 -> C7 (MSB) > A6 -> C6 > A5 -> C5 > A4 -> C4 > B3 -> C3 > B2 -> C2 > B1 -> C1 > B0 -> C0 (LSB) > > I use this compound bus label feature of ViewLogic so much I don't know how I > would manage without it. Hope something similar works for you. > > Dave Decker > Diablo Research Co. LLC -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 13281
works fine. The pod supply needs to be connected to 5v though. If you don't have 5v available on the board, xilinx does have an adapter for xchecker and the parallel cables that basically has an inverter on it to generate the 5v. The inverter is a bit pricey though. Austin Franklin wrote: > Hi, > > I'm curious is anyone has used the Xilinx XChecker cable with a Spartan XL > part (3.3V)? > > Any problems? Do you hook VCC on the pod up to 5V or 3.3V? > > Thanks, > > Austin -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 13282
Rickman wrote: > It is much easier to see if you draw out the logic, but the ripple chain > does not work like a binary adder. But HDLs are supposed to be so much more readable, aren't they??? :-) -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 13283
> ... The pod supply needs to be connected to 5v though. That kinda sucks. I hope they re-do the product to accommodate the other voltages they currently support... I do have +5, it's just that making a route from the bottom of the card, to the top, JUST for +5 for the XChecker cable, is more trouble than it's worth. AustinArticle: 13284
Le mer Michel (michel.lemer@ago.fr) wrote: : Do you have a bus master and a bus slave? : Is it possible than one fpga is always programming while the other one is ready : to work? In this case, may be one fpga interpret the tri-state level of the : other fpga as valid signals. : Good luck. : Michel. I don't have a master and a bus slave, but the 2 chips are not connected to each other until I have programmed them separately successfully. Anyway, Thanks a lot. OliverArticle: 13285
Hi, I get the following error message when trying to compile my design in foundation 1.4: CONV_ACS, 2.5.4.96, Mon Nov 23 21:09:05 1998 Macro 'jamvga' is not updated Different symbol pins number (16) and netlist terminals (0) EDIF netlist cannot be exported correctly Circular reference in symbols: Input netlist 'jamvga' has reference to: jamvga - U1 I am using Abel code in the macro "jamvga". Thanks for any help! Regards, Jamie MorkenArticle: 13286
I am having trouble finding relevant information on the internet regarding my project. I would like to find a general overview of FPGA Design, simulation and implementation. I do not need a lot of detail as I am only a first year university student. Any useful website suggestions would be appreciated. Thankyou.Article: 13287
> Hello, > > we are looking into prototype development using Actel FPGAs. > Currently we work with Synopsys Tools, using Designware and the FPGA-Compiler > as well. > I was wondering, whether anybody knows, where I can find the > > required libraries for the > Synopsys-FPGA compiler. I would appreciate any help on that > topic, since I have not been able to find any resources on the > web. > Thanks , Andreas -- Andreas Jungmaier, Dipl.-Ing. Gerhard-Mercator-Universitaet-GH Duisburg FB9/DV Bismarckstr. 81, 47048 Duisburg, Germany Tel.: +49 (0203) 379-2728 Fax: +49 (0203) 370439 email: ajung@uni-duisburg.de www.fb9dv.uni-duisburg.de/members/ajung/Article: 13288
On Sun, 22 Nov 1998 23:28:18 GMT, msimon@tefbbs.com wrote: >Don't buffers consume resources and add delay? Not necessarily... In some cases were you have a high fan-out net inserting a buffer may improve the timing. However a BUF component are not preserved after mapping unless you attach an X attribute. (Note that global buffers is different from BUF components). The following from the libraries manual might clearify this: "BUF is a general purpose, non-inverting buffer. In FPGA architectures, BUF is usually not necessary and is removed by the partitioning software (MAP). The BUF element can be preserved for reducing the delay on a high fan-out net, for example, by splitting the net and reducing capacitive loading. In this case, the buffer is preserved by attaching an X (explicit) attribute to both the input and output nets of the BUF." Jonas ThorArticle: 13289
Well, I'm use usually AHDL with ALTERA, but I believe it's the same procediment. You can assign a port to a pin with the menu: Menu->Assign->Pin/Location/Chip It opens a dialog box where you can select the port (node) with a number pin. The pin assigments aren't in the source code. They are in the *.acf files. Bye.Article: 13290
Attention Process Engineers! Boin GmbH, Germany, has developed a Win95/ NT metrology software for the semiconductor industry to review data files. WAFERMAP can import data from 4 point probes (KLA-Tencor, CDE ResMap, 4 Dimensions), ellipsometers (Rudolph, Philips Analytical, Sopra) an others (Thermawave, Nicolet, Jenoptik). Data files can be visualized off-line and outside the cleanroom as 1D plots, 2D contour and color plots, 3D plots. A wafer data editor and a SPC module is integrated. Data files can be compared and mathematical operations can be applied to single files as well as between two files. Files can be exported to other formats. WAFERMAP is the top choice for paperless fabs! Download your free evaluation copy at http://www.boin-gmbh.com WAFERMAP was selected as TOP product at Semiconductor Online (http://www.semiconductoronline.com).Article: 13291
You might try the programmable logic FAQ available on The Programmable Logic Jump Station at http://www.optimagic.com/faq.html . R A Felton wrote in message <365AA82E.6B8CB87@sheffield.ac.uk>... >I am having trouble finding relevant information on the internet >regarding my project. I would like to find a general overview of FPGA >Design, simulation and implementation. I do not need a lot of detail as >I am only a first year university student. >Any useful website suggestions would be appreciated. > >Thankyou.Article: 13292
There is a quick comparison at http://www.optimagic.com/comparison.html. You will find other details on the programmable logic FAQ at http://www.optimagic.com/faq.html. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Guest wrote in message <3659CE7F.B7A0F024@tech.iupui.edu>... >Hi, just wondering if anyone out there knows of a site that discusses >the differences between CPLD's and FPGA's? Thanks for info, > >PLEASE EMAIL, > >dddavids@topaz.iupui.edu > >Article: 13293
I have a flex10k part on the end of a daisy chain with two xilinx parts. I need information that is available on supporting multiple fpga files. I need to add an Altera programming file to the end of the Xilinx files. I can use a file formatter tool for the xilinx config., but not for the altera. Therefore, I need to know what information needs to be added to the programming file. Anyone have any experience here???????? PLEASE HELP!!!Article: 13294
Hi all, Can anyone point me to some good references on implementing arithmetic functions in high-speed digital logic? I'm especially interested in integer divide algorithms, but all other operations are also of interest (i.e. multipliers, adders, etc.). Books of a more practical nature covering real-world implementations would be ideal, as I'm looking for suitable circuits to be used in a production design in the near future. I've only just begun looking, but some of the titles I've run across include: "Computer Arithmetic Algorithms" by Israel Koren "Concrete Mathematics" by Graham, Knuth, Patashnik "Computer Arithmetic Systems" by Amos R. Omondi (appears to be out of print) "The Art of Computer Programming : Seminumerical Algorithms (Vol 2, 3rd Ed)" by Knuth Thanks, Paul pss1@hopper.unh.eduArticle: 13295
hi, we just went through the same exercise. it turns out that the synopsys libraries are a product and are not free. when you order the designer software, there is an option to order synopsys, too. they call it designer*synopsys. hope this helps, rk ==================================================== Andreas Jungmaier wrote: > > Hello, > > > > we are looking into prototype development using Actel FPGAs. > > Currently we work with Synopsys Tools, using Designware and the FPGA-Compiler > > as well. > > I was wondering, whether anybody knows, where I can find the > > > > required libraries for the > > Synopsys-FPGA compiler. I would appreciate any help on that > > topic, since I have not been able to find any resources on the > > web. > > > Thanks , > > Andreas > > -- > Andreas Jungmaier, Dipl.-Ing. > Gerhard-Mercator-Universitaet-GH Duisburg FB9/DV > Bismarckstr. 81, 47048 Duisburg, Germany > Tel.: +49 (0203) 379-2728 Fax: +49 (0203) 370439 > email: ajung@uni-duisburg.de www.fb9dv.uni-duisburg.de/members/ajung/Article: 13296
Paul S Secinaro wrote: > Hi all, > > Can anyone point me to some good references on implementing arithmetic > functions in high-speed digital logic? I'm especially interested in > integer divide algorithms, but all other operations are also of > interest (i.e. multipliers, adders, etc.). Books of a more practical > nature covering real-world implementations would be ideal, as I'm > looking for suitable circuits to be used in a production design in the > near future. > > I've only just begun looking, but some of the titles I've run across > include: Look for "Division and Square Root" by Ercegovac and Lang (Kluwer). Most of the literature about division is for floating point. Probably the only "practical-real-world-safe-bet" solution is the standard "digit recurrence" non-restoring algorithm, implemented with a signed-digit quotient (saves one sum in radix-2). If you have area (two multipliers) and need low latency maybe an iterative division with rounding (gosh !) can be implemented. An option is to convert the data to fp and use a floating pointer divider which provides unnormailzed data (integer). There is much more for multipliers and adders, but I don't remember anything "great" in books. There is an adder published in 1990 (I think) by Swartzlander and Lynch on the IEEE Transactions on Computers which has been built for AMD, so it's a real-world implementation, and it's quite interesting. For multipliers there are a lot of articles on how to connect compressors in the most efficient way (some are very recent on IEEE Trans. Comp.). They are especially interesting since the interconnect delays are getting more and more important (so all those guys who have been scaling array multipliers for the whole time are getting happy again now ;) ). -- Lorenzo Di Gregorio lorenzo.digregorio@hl.siemens.deArticle: 13297
I am doing a school project on FPGAs and became aware of a board that you can add into your computer that contains FPGA technology as a programmable chip that acts as a secondary processor, letting the CPU do all of the system management while the FPGA board completes the specialized task. Does anyone have any information on FPGA add-in boards? Vito P. ErricoArticle: 13298
Paul S Secinaro wrote: > > Hi all, > > Can anyone point me to some good references on implementing arithmetic > functions in high-speed digital logic? I'm especially interested in > integer divide algorithms, but all other operations are also of > interest (i.e. multipliers, adders, etc.). Books of a more practical > nature covering real-world implementations would be ideal, as I'm > looking for suitable circuits to be used in a production design in the > near future. > > I've only just begun looking, but some of the titles I've run across > include: > > "Computer Arithmetic Algorithms" by Israel Koren > "Concrete Mathematics" by Graham, Knuth, Patashnik > "Computer Arithmetic Systems" by Amos R. Omondi (appears to be out of print) > "The Art of Computer Programming : Seminumerical Algorithms (Vol 2, 3rd Ed)" > by Knuth > > Thanks, > > Paul > pss1@hopper.unh.edu you could try: "Architectures for Digital Signal Processing", Peter Pirsch -- Lasse ---------------------------------------------------------- Lasse Langwadt Christensen, M.Sc. EE (to be in 1999) Aalborg University, Department of communication technology Applied Signal Processing and Implementation (ASPI) http://www.kom.auc.dk/~fuz , ICQ# 13068090Article: 13299
I'm just an amateur here myself, so take this "cum granum salis", but...: Lorenzo Di Gregorio (lorenzo.digregorio@hl.siemens.de) wrote: : Paul S Secinaro wrote: : > Hi all, : > : > Can anyone point me to some good references on implementing arithmetic : > functions in high-speed digital logic? I'm especially interested in : > integer divide algorithms : Look for "Division and Square Root" by Ercegovac and Lang (Kluwer). Most of : the literature about division is for floating point. Probably the only : "practical-real-world-safe-bet" solution is the standard "digit recurrence" : non-restoring algorithm, implemented with a signed-digit quotient (saves one : sum in radix-2). If you have area (two multipliers) and need low latency maybe : an iterative division with rounding (gosh !) can be implemented. An option is : to convert the data to fp and use a floating pointer divider which provides : unnormailzed data (integer). If he is actually looking to build the thing, "convert to F.P. and use the F.P. divider" is at best a diversion. The only time advantage an F.P. divide has over an integer one (of the same size :-) is the ability to presume normalized inputs, but converting integer to F.P. is (to a first approximation) dominated by normalization. So once one "knows how to" normalize the inputs, there is no real point going all the way to F.P. (if what you really want is an integer divide). To the original poster: if your application is more likely to be bandwidth limited than latency limited, you might very well want to build a pipelined divider around a textbook algorithm. I have seen a few late-1970's graphics systems that did this (as well as using parallel/serial "Whiffle tree" multipliers for the matrix multiplies), but as I said, it depends on the demands of your application. Mike | albaugh@agames.com, speaking only for myself
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