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Lasse Langwadt Christensen <langwadt@ieee.org> wrote in message news:<3F0371D7.30906@ieee.org>... > Bill wrote: > > "Leon Heller" <leon_heller@hotmail.com> wrote in message news:<bdv712$oki$1@hercules.btinternet.com>... > > > >><eholbrook@austin.rr.com> wrote in message > >>news:874r24dalp.fsf@vole.holby-net... > >> > >>>I'm looking for a DIMM format FPGA board like Pilchard or the AcB from > >>>(now defunct?) Nuron. I've done several web searches, but found > >>>nothing that both fits the bill, and is from a company that is > >>>apparently alive. I've found a couple of things that are close to what > >>>i want (from mite.cz, and sunrise-systems.de), but they don't return > >>>emails, so i figure they're dead, too. > >>> > >>>Has anyone heard of something like this, or do i need to design/build > >>>it myself? > >> > >>I was thinking of developing one. How about us collaborating? > >> > >>Leon > > > > > > > > From what I hear, SRC Computers holds patents in this area and is not > > licensing to anyone right now. > > > > www.srccomp.com > > What! > > maybe I read it too fast maybe I just can't read patents or maybe > I just don't understand, but don't they basically claim that they > have patented programble logic memory mapped on a microprocessor? > > I would have guessed that that is widely used and has been for some > time :) > > -Lasse I think your reading it right, I would have thought it was widely used as well.Article: 57701
Hello all, I would like to know a couple of things if anyone could help or point me to a file etc. I'm using Webpack from Xilinx, and a Spartan XC2S100 and I've been messing around with writing simple project to get familiar with VHDL and programming the board. I'm curious to know if I have to instantiate a global clock buffer each time I sythesis my design, or if I simply make sure that my clock goes to a GCK pin is that enough? Also I'm a little confused as to what constraints are and how they might help my designs. For example if I have a 30 MHz clock going to a GCK pin do I have to put constraints on it or are constraints primarily used for very complex designs? Sorry if this seems like small question, but it is somewhat confusing from the documents that I have read, and since I haven't had any problems with any of my projects (without using any constraints) I was not all that worried. Now that I'm getting into bigger designs I figured that it was time to start figuring this out. Any and all help is greatly appreciated. Thanks JasonArticle: 57702
"John_H" <johnhandwork@mail.com> wrote in message news:<1GEKa.20$%E1.13818@news-west.eli.net>...
> "Jay" <yuhaiwen@hotmail.com> wrote in message
> news:bde3rr$rs8gp$1@ID-195883.news.dfncis.de...
> <snip>
> > How can I simulate this modules? in testbench I tried to initiate the
> > clkout, but failed.
> </snip>
>
> If you're doing RTL simulation from your original code, you need to
> initialize all your variables for simulation such as
>
> initial
> mydesign.clkout <= 1'b0;
>
> Alternatively, post place and route simulation can give you proper
> initializations as long as you bring out the global set/reset signal (.GSR)
> when generating the verilog file from the Xilinx tool. Then, the "initial"
> block doesn't initialize the individual RTL registers but is used to drive
> the .GSR for a short time at the start of the simulation, initializing all
> the register primitives to the power-on values. I don't recall if memories
> still need manual initialization or not (since they aren't cleared by a
> reset but are loaded with the programming file).
>
> The advantage to post place and route simulation is that some of your
> registers may power up logic high (when an FDS or FDSE primitive is used to
> implement the synthesized logic) and an incorrect initial state can alter
> your device's performance.
I change the code to
reg clkout;
wire GSR;
always@(posedge clkin)
begin
if(GSR == 1)
clkout <= 0;
else
clkout <= ~clkout;
end
thus in testbench I can give the clkout a initial value.
the simulation can work now.
but I still a little confuse about what you say:
the .GSR can "initializing all the register primitives to the power-on values."
how can it achieve this?
Do I miss someting important?
Article: 57703such a application 40MHz clkin, 20MHz clkdv output and 30MHz clkfx output use clk0 feedback to clkfb can both the clkdv and clkfx's de-skew be guaranteed?Article: 57704
Hi everyone,
Iam an student having doubt in LVDS communication,
Let say xilinx vertex FPGA is used for this pupose.
I have LVDS transmitter and receiver, No AC coupling is been used
between them.
Let say transmitter is in one board and receiver is in another board
connected through backplane (no AC coupling),
I am not recoevring the clock at the receiver, clock (77.77MHz) given to
both transmitter and receiver through single source.
Do i need to use any scrambling or encoding techniques before
transmitting the bit stream over LVDS to remove DC offset for better BER?
Thanks in Advance,
Article: 57705Looking at the Lattice parts, the Mach 4A3 or Mach 4000 would be candidates. I like the 4000, but there is almost no stock in the supply chain yet. Arrow has only a couple parts moving and Avnet has virtually none. Does not seem to have many designs going with it yet. Another problem with the 4000 is lack of packages. I really need a PQ208 but there are none in the 4000 at all. Very few choices and little or no stock even on those. The 4A3 is a possibility. There are 10 times as many parts moving through the dists and the family has 8 different devices with lots of packages. But the Icc is much higher on that series than the 4000. The factory tells me that the 4000 will be more expensive than the 4A as well. I guess if you want to design for the long term future it's probably best to pick a new family like the 4000. But you never know until later if that new family makes it or not in the market. Chris.Article: 57706
Steve Lass <lass@xilinx.com> writes: > Jim Granville wrote: > >> Can we get a quick summary of what's removed, and what legacy >> versions of SW are needed to support which family ? >> > The current software (version 5.1i, 5.2i, 6.1i) supports Virtex, > Virtex-E, Virtex-II, Virtex-II Pro, Spartan II, Spartan IIE, and > Spartan-3. > ISE Classics (version 4.2i) supports XC4000E, XC4000L, XC4000EX, > XC4000XL, XC4000XLA, Spartan, and SpartanXL. > > Contact the hotline if you need software for: > 3.1i supporting XC3000A, XC3000L and XC5200. > XACT 6 supporting XC2000, XC3000, and XC4000, XC4000A and XC5200. This sounds like I better terminate my Xilinx software subscription, and use the free versions instead. I recently changed my PC to a new one, and tried to install the licensed version of ISE 4.2, because I need Spartan and Spartan XL. It was a pain to make it work again because one design uses FPGA express, and it always complained about the license being invalid. The only solution was, as a Xilinx FAE told me, to use use tool to change the volume serial number of my hard disk to the one that the old PC had. Fortunately I didn' have to reregister Windows XP again. ThomasArticle: 57707
Thanks Peter, and sorry xilinx, affiliates, etc, my first comments on ml300, well I am little to fast to get critical when things dont work. I found some linux stuff (.h files, .so files, python, etc) still looking for the c compiler, (on the microdrive). if the EDK 'obsoleted' TFT is 'supposed' to work, I will give it a try. no problems. and montavista, guess it makes sense to ask for ver 3.0 ml300 microdrive has 2.1 Professional installed. thanks, and I do my homework better now e.g. when attempt to start c compiler on linux I will not yiell that C compiler isnt there (in 5 minutes) but keep searching for the compiler. ok, search is in progress :) Peter Ryser <ryserp@xilinx.com> wrote in message news:<3F036954.D30250BE@xilinx.com>... > Antti, > > the Linux demo shipping with ML300 comes with X Windows and a ton of servers > and applications. If for some reason your board came with just a very simple > command line version of Linux you can get the full MicroDrive image from the > ML300 lounge accessible from http://www.xilinx.com/ml300. > > If you want to start your own development with Linux on Virtex-II Pro please > contact MontaVista and ask them for MontaVista Linux 3.0 for ML300. They will > be able to give you more information on the content and the pricing of their > product. > > V2PDK is still supported by Xilinx. However, it is in the process of being > replaced with EDK. The V2PDK design for the ML300 is currently ported over to > V2PDK and you should be able to download it from the ML300 lounge in the near > future. A first version of the port will not support all peripherals that > have been available in V2PDK but will give enough functionality to boot > Linux. > > The TFT in EDK works as it is the same as in V2PDK.Article: 57708
christoph.grundner@agfa.com (Christoph Grundner) wrote in message news:<8a172a75.0307030527.40c28b2d@posting.google.com>... > Hi there > > i'm currently trying to configure Alteras JAM Player for a Mitsubishi > M16 Controller to program multi vendor device JTAG chains. Input files > are either *.jam (JAM file) or *.jbc (JAM-ByteCode file). > Is there a (preferably free) Xilinx tool to produce either one of > these file types? Where can i download the tool? impact generates JAM files, well called STAPL but it is the same thing. there are some problems though most of the files generates will not work with non-patched JAM player :( anttiArticle: 57709
"tk" <tokwok@hotmail.com> wrote in message news:<be09aq$804$1@hkueee5.eee.hku.hk>... > Hi, > > I've written a very simple application (hello world :) for the Linux in > ML300 using > ELDK's ppc_4xx cross compiler. > > http://lists.linuxppc.org/linuxppc-embedded/200305/msg00033.html > > I think it will be great if Xilinx can issuse some reference about how the > Linux demonstrating platform can be built. It will be useful for building > a customerized embedded Linux platform. hi tk, well xilinx just promised that an EDK project capable of minimal linux boot will be made (available) - so at least there is hope. I read your posting, but,,, I have no problems writing C programs for ML300 and merging them with reference bitstreams, the results also work :) but to compile for the linux on microdrive, i would need to 1) get the header files 2) compile 3) copy the executable back but the linux file system is so far unaccesible for me, eg the microdrive seems to have hidden linux partition (not visible on w2k host computer) and I havent managed to get the enet networking so the microdrive linux works, but I have no means to get a compiled program into it. ok, I need to plug in the network cable and see if I get it running anttiArticle: 57710
"Subroto Datta" <sdatta@altera.com> ha scritto nel messaggio news:ca4d800d.0307031507.7de6a279@posting.google.com... > Quartus II software version 3.0 is now available on the PC, Solaris, > Red Hat Linux, and HP-UX operating systems. Customer CD shipments will > be made from July 11 - July 21. The Web Edition is available for > download now. Windows9x is no more supported?Article: 57711
hi antti, seems good for you : ) i just download compiled programs from a Linux PC to the ML300 (microdrive) through network i'm sure the built-in embedded Linux demo has full network support just plug in the network cable and it will be ok !! cheers, tk "Antti Lukats" <antti@case2000.com> wrote in message news:80a3aea5.0307040020.222ea437@posting.google.com... > "tk" <tokwok@hotmail.com> wrote in message news:<be09aq$804$1@hkueee5.eee.hku.hk>... > > Hi, > > > > I've written a very simple application (hello world :) for the Linux in > > ML300 using > > ELDK's ppc_4xx cross compiler. > > > > http://lists.linuxppc.org/linuxppc-embedded/200305/msg00033.html > > > > I think it will be great if Xilinx can issuse some reference about how the > > Linux demonstrating platform can be built. It will be useful for building > > a customerized embedded Linux platform. > > hi tk, > > well xilinx just promised that an EDK project capable of minimal > linux boot will be made (available) - so at least there is hope. > > I read your posting, but,,, I have no problems writing C programs > for ML300 and merging them with reference bitstreams, the results > also work :) > > but to compile for the linux on microdrive, i would need to > 1) get the header files > 2) compile > 3) copy the executable back > but the linux file system is so far unaccesible for me, eg > the microdrive seems to have hidden linux partition (not visible > on w2k host computer) and I havent managed to get the enet networking > so the microdrive linux works, but I have no means to get a compiled > program into it. ok, I need to plug in the network cable and see if > I get it running > > anttiArticle: 57712
Mark Sandford wrote: > Try http://www.Google.com > > SP <nowhere@nowhere.com> wrote in message news:<Xns93ADB437CEF1nowherenowherecom@216.109.160.14>... > >>Hello, >> >>I am looking for an ARM (preferably StrongARM) w/ FPGA development board. >>StrongARM preference is for mainly for Linux. Any other supported processor >>will do as well. >> >>Thanks a lot! >>-Sumeet > Take a look at Altera's Excalibur, it has ARM9 hard core + peripherals and FPGA on the same die. http://www.altera.com/products/devices/arm/kits/exc-dev_kits_boards.html -KR-Article: 57713
I got a call from Insight. Of course I can get samples of the ESJ-part immediately. The Problem was, that I didn't ask for ESJ-Parts. They assumed I know what to ask for. Thanks to Peter for clarifying this. -Manfred Kraus mkraus_at_cesys_dot_comArticle: 57714
Manfred Kraus <news@cesys.com> wrote: : I got a call from Insight. Of course I can get samples of the ESJ-part : immediately. : The Problem was, that I didn't ask for ESJ-Parts. They assumed I know what : to ask for. The problem is also, that distributors often ask for an exact number, while the user mostly needs _any_ part with only few constraints. That way, you have to prepare a lot of fallback fits, and ask the distributor for each. If they could cope with wildcards in the part number, things would be easier... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 57715
yuhaiwen@hotmail.com (Yu Haiwen) wrote in message news:<4c1bc2c3.0307031906.4b53145@posting.google.com>... > such a application > 40MHz clkin, 20MHz clkdv output and 30MHz clkfx output > use clk0 feedback to clkfb > > can both the clkdv and clkfx's de-skew be guaranteed? Howdy Yu, What exactly do you mean by the "clkfx de-skew" portion of your question? Considering that there is no fixed phase relationship between asynchronous clocks (like your 30 MHz and 40 MHz), what good would the de-skew be? If you post a more complete description of your application, it would likely result in multiple responses, possibly each outlining a different way to meet your requirements. Good luck, MarcArticle: 57716
> hi antti, > > seems good for you : ) > > i just download compiled programs from a Linux PC to the ML300 (microdrive) > through network > > i'm sure the built-in embedded Linux demo has full network support > just plug in the network cable and it will be ok !! > lucky you! there are no linux PCs in our office and a corporate router may filter some stuff out, so plugging in, doesnt work 100% I can ping from ml300/linux, start FTP to location outside our network but thats not very comfortable using commandline ftp on ml300 and 3rd party ftp server as intermediate mailbox to copy files is not fun. our network gurus know almost nothing about linux etc, well work in progress what is good news that I did receive a working example for EDK incl DDR (and ethernet) - so web server from that example does work and I can access it from corporate network also. too bad the microdrive linux partition is not accessible at all :( it is there I know, 800MB are vanished (drive properties says 200MB for 1GB microdrive) tnx for help anttiArticle: 57717
Rene Tschaggelar wrote: > > There is no SOPCBuilder as it should be according to the pdf. > I browswed the SOPC Builder solutions in the knowledge base. Thanks this far for the messages. The SOPC builder appears to be correctly installed. There is no java running, at least it was not detectable. The is no other cygwin either. From the taskmanager it appears the perl.exe is somehow failing. It comes upon the SOPC button and goes right away. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 57718
Quartus II 2.2 SP2 is the last version that supports Windows 98. - Subroto Datta Altera Corp. "Valeria Dal Monte" <aaa@bbb.it> wrote in message news:GbbNa.145196$Ny5.4076538@twister2.libero.it... > > "Subroto Datta" <sdatta@altera.com> ha scritto nel messaggio > news:ca4d800d.0307031507.7de6a279@posting.google.com... > > Quartus II software version 3.0 is now available on the PC, Solaris, > > Red Hat Linux, and HP-UX operating systems. Customer CD shipments will > > be made from July 11 - July 21. The Web Edition is available for > > download now. > > Windows9x is no more supported? > > >Article: 57719
Hi guys. I'm working on a project using a HW platform with an XC2V300FG676-5. In my design I used Dual Ports BRAM produced by Coregen 4.2i (in Fndtn 4.2i). In simulation of the logic I faced the following problem: I wrote data on Port#A but when tried to read them back using port#B I realized that have been altered. Xilinx claims in Answer Record 10462 that this condition has to do with conflict resolution over the BRAM (same Read address on Port#B with write address on port#A). The answer they provide does not help me at all because I have alot and complicated logic in order to avoid hits over same address. Does anybody knows if this condition affects only simulation? Thanks in advanced NapArticle: 57720
so good that Xilinx sent you the example i'm interested in it, can u send me (email: h0013252@eee.hku.hk) a copy ? i'm now finding out how to build (glue all the IP cores needed) an embedded system environment for the MontaVista Linx (Pro 3.0) to work on, do you know any reference about that (so as to build an embedded Linux similar to the one on ML300) ? > I can ping from ml300/linux, start FTP to location outside our network > but thats not very comfortable using commandline ftp on ml300 and 3rd > party ftp server as intermediate mailbox to copy files is not fun. for my case, it's rather convenient for me, i just mount a network drive from other Linux PC on ML300/Linux seems that thare are programs running under M$ Windows can access Linux partition but i will suggest you put the files in the FAT partition, then access the files in Linux by mounting the FAT partition (it's "/dev/xsysace/disc0/part1" in my case) cheers, tk "Antti Lukats" <antti@case2000.com> wrote in message news:80a3aea5.0307040614.743f3071@posting.google.com... > > hi antti, > > > > seems good for you : ) > > > > i just download compiled programs from a Linux PC to the ML300 (microdrive) > > through network > > > > i'm sure the built-in embedded Linux demo has full network support > > just plug in the network cable and it will be ok !! > > > > lucky you! there are no linux PCs in our office and a corporate router > may filter some stuff out, so plugging in, doesnt work 100% > > I can ping from ml300/linux, start FTP to location outside our network > but thats not very comfortable using commandline ftp on ml300 and 3rd > party ftp server as intermediate mailbox to copy files is not fun. > > our network gurus know almost nothing about linux etc, well work in progress > > what is good news that I did receive a working example for EDK incl > > DDR (and ethernet) - so web server from that example does work and > I can access it from corporate network also. > > too bad the microdrive linux partition is not accessible at all :( > it is there I know, 800MB are vanished (drive properties says 200MB > for 1GB microdrive) > > tnx for help > anttiArticle: 57721
nshimizu@bosei.cc.u-tokai.ac.jp (Naohiko Shimizu) wrote in message news:<bcbvf6$2i9u$1@news.cc.u-tokai.ac.jp>... > Hi, > For under graduate project, my students Mr.Iida wrote a PDP11/40 > compatible CPU and now it boot Unix from an IDE hard drive. > We named the CPU as POP11/40 (PDP11 On Programmable chip). I could any downloads to be synthesized ? are they available at all? anttiArticle: 57722
Scrambling or encoding (like 8b10b) are used primarily for two reasons - to
provide DC balance, and to provide enough signal transition density for
clock recovery.
DC balance is required whenever AC coupling is used between a transmitter
and receiver. When the signal is AC coupled, a long sequence of the same bit
will introduce a large DC offset at the receiver end (the AC coupling
capacitor will charge up). To avoid this, it is necessary to encode the bit
stream to ensure that there is statistically a 50/50 balance between 0's and
1's. This can be done by scrambling, where you XOR the datastream with a
pseudo-random bit sequence (i.e. SONET scrambling), or you use some encoding
scheme like 8b10b which provides DC balance. Encoding (like 8b10b) decreases
your effective bandwidth (since 2 extra bits are required for each 8 bits
transmitted), but guarantees DC balance over a small number of bits. SONET
scrambling does NOT reduce bandwidth, but only provides a statistical
likelihood of DC balance given a "typical" datastream. In any event, since
you say your data is NOT AC coupled, then you do not need to provide
scrambling or encoding for this purpose.
Signal transition density is required whenever you are attempting to do
clock recovery. Most clock recovery circuits are based around a PLL that is
tracking the bitrate of the incoming datastream. Each time the receiver sees
a transition on the incoming data, it updates the frequency of its tracking
PLL so that it can stay in sync with the bitrate clock. If there are no
transitions for a certain period of time, then the PLL free runs based on
the last information it had about the incoming bit rate. For a small number
of bits, the free running PLL will still be mostly in sync with the incoming
data; it needs to stay close enough so that it will not mistake one bit for
the previous or next one (when a transition finally occurs). If the
datastream does not have a rich enough density of transitions, the free
running PLL will occasionally slip, gain or misinterpret a bit, ultimately
causing bit errors. Both scrambling and encoding provide "rich" transition
densities (8b/10b gaurantees a maximum run length, and scrambling provides
the statistical likelihood that there will be sufficient transitions).
Again, since you are not doing clock recovery, you do not need to use
encoding or scrambling.
That being said, this is still not a trivial system. Simply sampling a
datastream with a clock that is identical to the transmitting clock does not
guarantee an error free communication channel. In your case, you are using
the same 77.77MHz clock to drive both the transmitter and the receiver -
that allows for the possibility of proper communication, but there is a lot
more that is required. In order to sample the incoming data properly, you
must guarantee that you are meeting the setup and hold time requirements of
the sampling flops at the receiver.
Xilinx Virtex family parts give you a number of tools that make it possible.
Using the IOB flops in the transmitter, Xilinx guarantees a relationship
between the incoming clock at the transmitter and the data output at the
pins of the transmitter, ASSUMING you are using the "standard clock
deskewing" using the DLL or DCM (clkin via an IBUFG to the DCM, CLK0 of the
DCM to a BUFG, and the output of the BUFG driving the CLKFB of the DCM as
well as the clock of the IOB flops). This is the parameter "Tickofdcm".
Similarly, if you are using the standard clock deskewing in the receiver and
the IOB flops for sampling the data, then Xilinx states the required setup
and hold times "Tpsdcm" and "Tphdcm".
It is up to you to design a system around these timings. You must trace the
complete path from the starting point (in this case the 77.77MHz oscillator)
through both paths:
Jitter of the oscillator
Oscillator to transmitter FPGA board delay
Tpsdcm inside FPGA
transmitter FPGA to connector board delay
backplane board delay
connector to reciever board delay
This must be compared to the other path
Jitter of the oscillator (yes, this counts twice)
Oscillator to receiver FPGA board delay (since you MUST have only one
oscillator, one or the other clock paths will have to go through the
backplane)
You must prove that under all conditions of process temperature and voltage
(i.e. MIN and MAX delay conditions), these delays result in a relationship
between the clock and data at the receiver FPGA that meet both Tpsdcm and
Tphdcm. At 77.77MHz, this IS possible with careful board design, but it is
not trivial...
Avrum
<Guest> wrote in message news:ee7e73f.-1@WebX.sUN8CHnE...
Hi everyone,
Iam an student having doubt in LVDS communication,
Let say xilinx vertex FPGA is used for this pupose.
I have LVDS transmitter and receiver, No AC coupling is been used
between them.
Let say transmitter is in one board and receiver is in another board
connected through backplane (no AC coupling),
I am not recoevring the clock at the receiver, clock (77.77MHz) given to
both transmitter and receiver through single source.
Do i need to use any scrambling or encoding techniques before
transmitting the bit stream over LVDS to remove DC offset for better BER?
Thanks in Advance,
Article: 57723
A follow up:
Someone sent this solution to me and said it would provide no assymetrical
delays and would be better than a long elsif chain. Does anyone else have
any experience with this? It seems to me that a good fitter would render the
same solution.
Hi,
A clean way of doing this is:
CASE fastclkcnt IS
WHEN 2 =>
mrasnext <= '0';
mcasnext <= '1';
mwenext <= '0';
mdqmnext <= '1';
WHEN 4 =>
mrasnext <= '0';
mcasnext <= '1';
mwenext <= '0';
mdqmnext <= '1';
WHEN 12 =>
mrasnext <= '0';
mcasnext <= '1';
mwenext <= '0';
mdqmnext <= '1';
WHEN OTHERS =>
END CASE;
like this you make a decoder-mux arrangement
equal to all signals, so no strugle with assimetric
delays. (a long elseif chain is not a good solution).
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