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"Peter Alfke" <peter@xilinx.com> wrote: > The LVDS outputs from Virtex2 can output up to 800 Mbps, and are heading > towards 1Gbps. Peter, excuse my ignorace. What mechanism do you use to achieve this on a V2? Two SRL16's driving a DDR IOB at 400Mhz? Have people implemented significant designs running at these frequencies internally or is it more common to use multiple data paths to slow it down to the 200 range as a desirable maximum? In other words, what can you consistently/reliably achieve for a non-trivial design? I've only worked in the sub-200Mhz range so far, so I don't have a tangible sense of whether or not there's a "wall" you hit around a certain frequency where everything becomes exponentially more difficult. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 56726
"Vishker" <vishker@yahoo.com> wrote in message news:9ea7e3a3.0306041058.6d799d58@posting.google.com... > Can we generate Post P&R Verilog or VHDL netlist from ISE that can be > synthesiable ? I used ngd2ver but the output verilog netlist contains > lots of statements that are not synthesizable. Same is the case with > VHDL. > > Thanks > > -Vs I've got no idea why anyone would like to do this. In software terms, this sounds like taking assembler code resulting from compilation, insert it in your source code again, and try to recompile/optimize it again like a kind of recycling strategy? Perhaps you believe to have found an easy path to convert a Xilinx design (of which you may not have the design HDL code) into another FPGA technology through synthesis? This won't work however. Again, I can't think of any good reason for what you're doing. Post-layout (timing) simulation is the only goal of these files, in conjunction with SDF timing info. Regards, JaapArticle: 56727
Hello, I am looking for a compact (say 3x3") board that has both RISC processor (preferably ARM or PPC) and a decent FPGA chip. The only one I could find is this one: http://www.sunrise-systems.de/SA1110-E.htm Has anyone used this? Are there other options? Basically, I'm looking for something that resembles Intrinsyc's cerfcube with an integrated FPGA chip. Thanks, Bram StolkArticle: 56728
In article <20030612221310.691e2ac2.b.stolk@chello.nl>, Bram Stolk <b.stolk@chello.nl> wrote: >Hello, > > >I am looking for a compact (say 3x3") board that has both >RISC processor (preferably ARM or PPC) and a decent >FPGA chip. > >The only one I could find is this one: >http://www.sunrise-systems.de/SA1110-E.htm > >Has anyone used this? >Are there other options? > >Basically, I'm looking for something that resembles >Intrinsyc's cerfcube with an integrated FPGA chip. How MUCh processor and FPGA do you need? And how tight the coupling? If you only need a little of both, Charmed Labs (www.charmedlabs.com) has an FPGA card (Spartan II 50, although they have a SII 150 board in progerss) which fits in a GameBoy Advanced (16 MHz ARM). -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 56729
A question concerning mixed (analog and digital) signals connected to fpga's: One end of a bidirectional mixed signal bus (0-5V) is connected to a muxed adc input and directly connected to spartan2 pins. The spartan2 should drive the bus low or high or tristate; no inputs are used. In this situation the spartan2 gets voltage levels (for long time intervals) which are not allowed on inputs because of violated rise/fall timings. Is this direct connection allowed if the spartan pins are not configured as inputs, or should i use a buffer like a 74hct244 ? Thanks for any advice. MIKEArticle: 56730
M.Randelzhofer <mrandelzhofer@uumail.de> wrote: : A question concerning mixed (analog and digital) signals connected to : fpga's: : One end of a bidirectional mixed signal bus (0-5V) is connected to a muxed : adc input and directly connected to spartan2 pins. The spartan2 should drive : the bus low or high or tristate; no inputs are used. : In this situation the spartan2 gets voltage levels (for long time intervals) : which are not allowed on inputs because of violated rise/fall timings. Is : this direct connection allowed if the spartan pins are not configured as : inputs, or should i use a buffer like a 74hct244 ? You can't probaly disconnect the input buffer. So this input buffer can get into the linear region for substained periods, drawing considerable current. I haven't seen anything mentioned in the data sheet about that, but if possible, don't do that. But a (CMOS) buffer in between doesn't solve the problems, as it may get into the linear region too. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 56731
Uwe, Because Spartan 2* has HSTL and SSTL in/out standards, we expect the IOs to sometimes be exactly at Vcco/2 forever. So they are designed not to have "large currents" and to tolerate this condition forever. The rise and fall tiem restrictions are for good engineering practices, not for any reliability or functional reasons. Austin *Also applies to Virtex, Virtex E, Virtex II, Virtex IIP, Virtex IIP-X, Spartan 2, Spartan 3 Uwe Bonnes wrote: > M.Randelzhofer <mrandelzhofer@uumail.de> wrote: > : A question concerning mixed (analog and digital) signals connected to > : fpga's: > > : One end of a bidirectional mixed signal bus (0-5V) is connected to a muxed > : adc input and directly connected to spartan2 pins. The spartan2 should drive > : the bus low or high or tristate; no inputs are used. > > : In this situation the spartan2 gets voltage levels (for long time intervals) > : which are not allowed on inputs because of violated rise/fall timings. Is > : this direct connection allowed if the spartan pins are not configured as > : inputs, or should i use a buffer like a 74hct244 ? > > You can't probaly disconnect the input buffer. So this input buffer can get > into the linear region for substained periods, drawing considerable > current. I haven't seen anything mentioned in the data sheet about that, but > if possible, don't do that. But a (CMOS) buffer in between doesn't solve the > problems, as it may get into the linear region too. > > Bye > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 56732
Martin, you may want to scan some Virtex2 App Notes. Here is a one-year-old one that also discusses clock recovery at 840 Mbps. http://www.xilinx.com/xapp/xapp265.pdf In the meantime, we have collected more data and designs, and I can connect you to a Xilinx applications engineer with extensive experience in the field of digital video (if you send me e-mail at peter@xilinx.com) You obviously will not run your whole design at 840 MHz clock rate. But with a 4-to-1 serializer you should not have any problems on the transmitting side. And even the receiver can be done, albeit with more "work". Peter Alfke ================= Martin Euredjian wrote: > > "Peter Alfke" <peter@xilinx.com> wrote: > > > The LVDS outputs from Virtex2 can output up to 800 Mbps, and are heading > > towards 1Gbps. > > Peter, excuse my ignorace. What mechanism do you use to achieve this on a > V2? Two SRL16's driving a DDR IOB at 400Mhz? Have people implemented > significant designs running at these frequencies internally or is it more > common to use multiple data paths to slow it down to the 200 range as a > desirable maximum? In other words, what can you consistently/reliably > achieve for a non-trivial design? I've only worked in the sub-200Mhz range > so far, so I don't have a tangible sense of whether or not there's a "wall" > you hit around a certain frequency where everything becomes exponentially > more difficult. > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu"Article: 56733
Austin Lesea wrote: > > Uwe, > > Because Spartan 2* has HSTL and SSTL in/out standards, we expect the IOs to > sometimes be exactly at Vcco/2 forever. So they are designed not to have "large > currents" and to tolerate this condition forever. The rise and fall tiem > restrictions are for good engineering practices, not for any reliability or > functional reasons. > > Austin > > *Also applies to Virtex, Virtex E, Virtex II, Virtex IIP, Virtex IIP-X, Spartan 2, > Spartan 3 Is this true of all interface modes, or do you need to select one of the differential ones ? eg I would expect the Digital modes to have a faster/simpler CMOS buffer structure, whilst the Differential ones have a (slower) comparitor, ( which I think is actually Rail-Rail from earlier posts ?) Another danger, besides the threshold region current peak, is what I call transistion oscillation : the CMOS buffer chain is not linear-stable, and a slow edge can cause oscillations - at very high frequencies, and these can impact 'unrelated' logic. An ideal comparitor is rail-rail, plus valid with a single IP outside the rails (for overshoots), and includes some small hysteresis, to avoid linear-region oscillations. How close are the spartan 2* IPs to that ? Double edging can still occur, if driven from a high source impedance, or at very slow edges if the ground bounce exceeds the hysteresis. - jgArticle: 56734
"Austin Lesea" <Austin.Lesea@xilinx.com> schrieb im Newsbeitrag news:3EE8F43E.1032A7C2@xilinx.com... > Uwe, > > Because Spartan 2* has HSTL and SSTL in/out standards, we expect the IOs to > sometimes be exactly at Vcco/2 forever. So they are designed not to have "large > currents" and to tolerate this condition forever. The rise and fall tiem > restrictions are for good engineering practices, not for any reliability or > functional reasons. > > Austin > > *Also applies to Virtex, Virtex E, Virtex II, Virtex IIP, Virtex IIP-X, Spartan 2, > Spartan 3 > > Uwe Bonnes wrote: > > > M.Randelzhofer <mrandelzhofer@uumail.de> wrote: > > : A question concerning mixed (analog and digital) signals connected to > > : fpga's: > > > > : One end of a bidirectional mixed signal bus (0-5V) is connected to a muxed > > : adc input and directly connected to spartan2 pins. The spartan2 should drive > > : the bus low or high or tristate; no inputs are used. > > > > : In this situation the spartan2 gets voltage levels (for long time intervals) > > : which are not allowed on inputs because of violated rise/fall timings. Is > > : this direct connection allowed if the spartan pins are not configured as > > : inputs, or should i use a buffer like a 74hct244 ? > > > > You can't probaly disconnect the input buffer. So this input buffer can get > > into the linear region for substained periods, drawing considerable > > current. I haven't seen anything mentioned in the data sheet about that, but > > if possible, don't do that. But a (CMOS) buffer in between doesn't solve the > > problems, as it may get into the linear region too. > > > > Bye > > -- > > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- > Hello Austin thanks for this information, this will simplify my design. Is there any appnote or webcase which covers all such unorthodox fpga usage ? In the 1992 databook (ok this was yesterday) was an application brief called "Additional Electrical Parameters". Still valid or updated material available ? Thanks again for the fast response. MIKEArticle: 56735
As Austin said, there is no structural integrity = reliability problem. You can park the inputs anywhere you want for how long you want ( between Vcco and Grnd). The input buffers are small, and so is their cross-current. Obviously, you might get pulses, although we have a slight hysteresis on all inputs. Your internal logic will just ignore it, if you configured it right. I take it, that IP means " input". New acronym to me. We use IP for Intellectual Property (patents and things). Peter Alfke, Xilinx ============================== Jim Granville wrote: > > Austin Lesea wrote: > > > > Uwe, > > > > Because Spartan 2* has HSTL and SSTL in/out standards, we expect the IOs to > > sometimes be exactly at Vcco/2 forever. So they are designed not to have "large > > currents" and to tolerate this condition forever. The rise and fall tiem > > restrictions are for good engineering practices, not for any reliability or > > functional reasons. > > > > Austin > > > > *Also applies to Virtex, Virtex E, Virtex II, Virtex IIP, Virtex IIP-X, Spartan 2, > > Spartan 3 > > Is this true of all interface modes, or do you need to select one of > the > differential ones ? > > eg I would expect the Digital modes to have a faster/simpler CMOS > buffer > structure, whilst the Differential ones have a (slower) comparitor, > ( which I think is actually Rail-Rail from earlier posts ?) > > Another danger, besides the threshold region current peak, is > what I call transistion oscillation : the CMOS buffer chain is > not linear-stable, and a slow edge can cause oscillations - at very > high frequencies, and these can impact 'unrelated' logic. > > An ideal comparitor is rail-rail, plus valid with a single IP outside > the rails (for overshoots), and includes some small hysteresis, > to avoid linear-region oscillations. > > How close are the spartan 2* IPs to that ? > > Double edging can still occur, if driven from a high source impedance, > or > at very slow edges if the ground bounce exceeds the hysteresis. > > - jgArticle: 56736
"M.Randelzhofer" wrote: > > Is there any appnote or webcase which covers all such unorthodox fpga usage > ? > In the 1992 databook (ok this was yesterday) was an application brief called > "Additional Electrical Parameters". > Still valid or updated material available ? Hi, I wrote that in 1988, right after I joined Xilinx. It refers to XC3000, and is thus obsolete, but the basic facts stay the same. In the meantime, the devices have become so much more complex that there is no way to have an exhaustive list of "little things that are left out of the data sheet". Also, IC manufacturers have this fixation that everything documented in the data sheet must be tested and guaranteed. Laudable idea, but it acts as a hindrance to documenting uncritical and untested parameters... Peter AlfkeArticle: 56737
I am trying to use FIFO structures 256x16 LPM based. First, I have probed
lpm_fifo module, but the number of EABs when I use 2 fifos was bigger than
double of 1 fifo, why?
Later, I am trying to use CSFIFOs: in a module with 2 csfifo instantiations
I can not do it with Leonardo, I think the EDIF file is not good for
MaxplusII, why?, but directly from MaxplusII it goes fine.
When I add more logic to the same module with 2 csfifo in Maxplus it gives
errors about not connected nodes in csfifos, why?
The definitions and instantiation I have are:
`ifdef exemplar
module csfifo (data, wreq, rreq, clock, clockx2, clr, sclr,
q, full, empty);
parameter lpm_width = 16,
lpm_numwords = 256;
input [lpm_width-1:0] data;
input wreq, rreq, clock, clockx2, clr, sclr;
output [lpm_width-1:0] q;
output full, empty;
endmodule
`endif
module cyclefifos (data, wreq, rreq, clk, clr, sclr,
q1, full1, empty1,
q2, full2, empty2);
input [15:0] data;
input wreq, rreq, clr, sclr;
output [15:0] q1, q2;
output full1, empty1, full2, empty2;
input clk;
reg [1:0] count;
wire clk1;
reg clk2;
always @(posedge clk) begin
count = count + 1;
if (count) clk2 = ~clk2;
end
assign clk1 = clk;
csfifo fifo1 (.data(data),
.wreq(wreq), .rreq(rreq),
.clock(clk2), .clockx2(clk1),
.clr(clr), .sclr(sclr),
.q(q1),
.full(full1), .empty(empty1));
defparam fifo1.lpm_width=16;
defparam fifo1.lpm_numwords=256;
// exemplar attribute fifo1 noopt true
csfifo fifo2 (.data(data),
.wreq(wreq), .rreq(rreq),
.clock(clk2), .clockx2(clk1),
.clr(clr), .sclr(sclr),
.q(q2),
.full(full2), .empty(empty2));
defparam fifo2.lpm_width=16;
defparam fifo2.lpm_numwords=256;
// exemplar attribute fifo2 noopt true
endmodule
Article: 56738Is there any way I can capture the vga display from a computer different than the one that generated it? I have a standalone board (not a computer) that has a vga connector for debugging purposes. I would like to save a snapshot of its output on my computer, but since its being generated external to my computer, how can I grab it? Thanks!Article: 56739
Ben Nguyen wrote: > > Is there any way I can capture the vga display from a computer different > than the one that generated it? > > I have a standalone board (not a computer) that has a vga connector > for debugging purposes. I would like to save a snapshot of its output > on my computer, but since its being generated external to my computer, how > can I grab it? > > Thanks! Use a camera ? :)Article: 56740
"Ben Nguyen" <benn686@hotmail.com> wrote in message news:e604be8.0306121741.7328ecf0@posting.google.com... > Is there any way I can capture the vga display from a computer different > than the one that generated it? You can digitize the signal, but much easier is to read it out of video memory on the computer generating it. -- glenArticle: 56741
Just like the TI DSP or some simple DSP. I heard that someone had develop TMS320 3x core.But I can't find it. -- Thanks and Best RegardsArticle: 56742
Hi, For under graduate project, my students Mr.Iida wrote a PDP11/40 compatible CPU and now it boot Unix from an IDE hard drive. We named the CPU as POP11/40 (PDP11 On Programmable chip). Without MMU/EIS it uses only about 1700 logic cells with Altera, and with MMU/EIS it needs about 3600 logic cells. Description language of CPU is SFL and we converted to Verilog with sfl2vl. Now I placed simulation package for Icarus Verilog v0.7 on my web site. http://shimizu-lab.dt.u-tokai.ac.jp/ -------------- simulation log --------------- POP11/40 Simulation Start with disp mode= 0 Copyright 2003 Naohiko Shimizu, Yoshihiro Iida, Tokai University, Japan @rkunix.40 mem = 436 login:root #ls bin dev etc lib mnt mnt2 rkunix rkunix.40 tmp unix usr usr2 # --------------------------------------------- POP-11/40 Simulation package for Icarus Verilog Copyright (c) 2003 Naohiko Shimizu, Yoshihiro Iida, Tokai University, Japan All rights reserved. POP11/40 is a PDP11/40 compatible processor with IDE HDD interface. CPU was written with SFL and converted to Verilog with sfl2vl. When fitting to Altera FPGA, POP11/40 needs about 3600 logic cells Contents: README: this file sim-pop11: Icarus Verilog simulation script. unix: Unix V6 drive image bmem: initial boot loader reside on memory. console.in: console input strings. '7f' will terminate simulation. Makefile: makefile to run simulation AncientUnix.pdf: Unix V6 license file If you did not install Icarus Verilog at /usr/local, you may need to edit `sim-pop11'. Makefile has four simulation entries: sim-help: ./sim-pop11 +help=1 ;show help messages sim: ./sim-pop11 ;full simulation sim-regs: ./sim-pop11 +disp=2 ;full simulation with register dump sim-short:./sim-pop11 +stop=100 +disp=2 ;limited cycle simulation Full simulation takes very long time, about 140 minutes with 64 bit mode Opteron 1.4GHz and Icarus Verilog v0.7. ---------------------------------->--------------------------->> Naohiko Shimizu Department of Communications Engineering, School of Information Technology and Electronics, Tokai University 1117 Kitakaname Hiratsuka 259-1292 Japan TEL.+81-463-58-1211(ext. 4084) FAX.+81-463-58-8320 http://shimizu-lab.dt.u-tokai.ac.jp/ <<--------------------------------<-----------------------------Article: 56743
> Also, IC manufacturers have this fixation that >everything documented in the data sheet must be tested and guaranteed. >Laudable idea, but it acts as a hindrance to documenting uncritical and >untested parameters... I've seen lots of data sheets with "typical" numbers. There is another great footnote I see reasonably often called "Guaranteed by design". -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 56744
Hi John, You should have a look at the Nios kit from Altera. It is possible to get this kit at a discounted prize of 495$ from any Altera distributor (I prefer EBV in Europe since i acctually work there) until the end of june (so hurry). The kit has SDRAM ethernet mac and soforth so I would be easy to build your own CPU/motherboard. (You get the Nios Risc cpu any way) The kit has everything you need to start building your application powercables download cable and more. Preferbly is the Cycklone kit if you need lots of Logic, if you need realy high preformance I would suggerst the Stratix version. Just my 0.02$ Cheers Fredrik TheCppMaster@aol.com (John) wrote in message news:<a25b4de5.0306112212.13b03932@posting.google.com>... > Hello, > I'm a bit new to FPGAs. I am in the process of learning VHDL and I am > interested in developing my own RISC CPU. My ultimate goal is to get a > full system running capable of I/O with standard PC components (ide, > usb, ethernet, PS2, video, etc). I'm hoping to eventually load an OS > on top of my chip and run my own programs. I've done most of the work > on the OS and applications already. I'm now turning towards the > hardware (i need to get that developed before I can implement the > lowest level of the software). I am on somewhat of a budget (this > project is just for fun) so I'm looking to spend at most about $500 > for a board and FPGA. Which FPGA do you recommend? Xilinx seems to > have the most options (the Spartan series has lots of boards for it > and it looks to be pretty affordable). What board do you recommend > (short of a custom) that will offer the best fit for the job (similar > to a PC motherboard). All help is greatly appreciated! > > ThanksArticle: 56745
eternal_nan@yahoo.com (Ljubisa Bajic) writes: > Hi All, > > You are right, the signalling used in DVI is not exactly lvds, it is > current mode, but, as Peter Alfke mentioned in the other thread on > this subject, the v2 differential drivers are highly programmable and > I think that with some tweeking they can be made to output a signal > that is acceptable by an DVI receiver chip. As far as the data rate > concerns Martin E. had, v2's SERDES is more than capable of handling > the data rates that are neccessary for DVI links (upto 3Gbits/s as far > as I know should be fine with a v2). Is that data rate not for the MGT blocks on V2*Pro*? 840Mbps is the max for basic V2 AFAIK. Ditto the configurability of the differential drivers I think also? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 56746
On Thu, 12 Jun 2003 20:25:21 +0000 (UTC) nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) wrote: > >Basically, I'm looking for something that resembles > >Intrinsyc's cerfcube with an integrated FPGA chip. > > How MUCh processor and FPGA do you need? And how tight the coupling? > If you only need a little of both, Charmed Labs (www.charmedlabs.com) > has an FPGA card (Spartan II 50, although they have a SII 150 board in > progerss) which fits in a GameBoy Advanced (16 MHz ARM). Hi Nicholas, Your Charmed Labs reference is a real gem! It looks like an excellent product for FPGA novices, and is really affordable. The only downside I see is the rather old ARM7 of the GBA, which I believe does not have an MMU? If the gameboy advance would have StrongARM or Xscale, it would be the perfect product I think. I want to run a real linux on the arm, not a mmu-less linux. Thanks again for the link. BramArticle: 56747
"Ben Nguyen" <benn686@hotmail.com> wrote in message news:e604be8.0306121741.7328ecf0@posting.google.com... > Is there any way I can capture the vga display from a computer different > than the one that generated it? > > I have a standalone board (not a computer) that has a vga connector > for debugging purposes. I would like to save a snapshot of its output > on my computer, but since its being generated external to my computer, how > can I grab it? > Being that this is a FPGA group, I would suggest a FPGA and 3 dacs. RalphArticle: 56748
Peter Alfke wrote:
> I take it, that IP means " input". New acronym to me.
> We use IP for Intellectual Property (patents and things).
LOLO
AQIC
I82Q
B4IP
Article: 56749Hi, I am using a Virtex-II Pro (XC2VP30-FG676) and need to estimate the power consumed by this chip for different stages: (Note that I don't have an eval board or the prototype board yet) 1) Normal operation, DONE with XPower (~1.2W, with blah, blah logic) 2) Blank Image, DONE (~605mW, the h*ll of a lot and is only what I've got in there, the QUIESCENT POWER is massive) 3) When is not configured, how can I do this? I'd use a uP to fetch data from Flash and 'upload' different images to the FPGA, I'd like to know what happens when is powered up but there is nothing on it. Thanks in advance Ulises Hernandez ECS Technology Ltd. www.ecs-tech.com
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