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"Jim Ranlett" <ballsofsteel@rcsis.com> wrote in message news:53de32df.0305211648.7e8fcb54@posting.google.com... > I want to implement a state machine in a small PLD or FPGA using some > sort of HDL like AHDL, WinCUPL, etc. However, I don't want to supply > an external clock to the part. I'd like to know if it is possible to > use an inverter inside the CPLD, feeding back the output of the > inverter to the input of the inverter, thus creating a "clock". Then, > I want to attach that "clock" to the part's global clock net and use > that clock as the clock for my state machine. > > Is something like this possible? > > What I'm really trying to do is implement an asynchronous state > machine that changes state only when its inputs change, without regard > to clocks. I don't have a clock to supply to the system. What I'm > finding, though, is most HDLs assume state machines are synchronous > and expect a clock. (and reset, for that matter.) > > If I have to use a clock to implement the state machine, I would of > course have to synchronise the asynchronous inputs with the state > machine clock. Simple enough, but I'd really rather not have to > supply an external clock to the system if at all possible. > > I'm not limiting myself to any particular part of language, but I'd > like to try to keep to what I'm familiar with (AHDL, WinCUPL, etc.) > Other parts and HDL suggestions are welcome, especially those that > might have Async State Machine constructs. > > FYI, I expect the state machine to have 4 inputs, 4 outputs (the > outputs are NOT the state bits but different), and 13 defined states > (implying 4 state bits). > > (It seems that most HDLs default to D flipflops as the state bits, and > D-flops need a clock. Is there anyway to default to, say, a JK flop > and not require a clock, but derive next state equations for the J & K > inputs? A compiler that does this would be great, as I expect the > equations to be rather cumbersome for me to realize manually.) > > Thanks for any suggestions. > > Sincerely, > Jim Ranlett This tells about how to create an internal clock: Steve http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&oe=UTF-8&threadm=3D0EB699 .78E095E0%40earthlink.net&rnum=2&prev=/groups%3Fq%3Dinternal%2Boscillator%2B group:comp.arch.fpga%2Bauthor:alfke%26hl%3Den%26lr%3D%26ie%3DUTF-8%26oe%3DUT F-8%26selm%3D3D0EB699.78E095E0%2540earthlink.net%26rnum%3D2 Search - Internal oscillator in CPLD? in Comp.arch.fpgaArticle: 55876
You can't use the Byteblaster. Bothe devices, EPC1441 as well as EPC 1 are EPROM based, don't offer a JTAG port and hence are not programmable using a download cable. You can program those PROMs using a Altera Programmer PL-?? or any other programmer, BP Microsystems, Data I/O etc. Or you can buy an EPC2. Thats more expensive but can be programmed via Byteblaster.Article: 55877
hi, i am wondering if someone can help me in the following handel-c query. what's the proper method to initialize the large size ROM in handel C. I want to transfer LUT data from a data file to the ROM and also don't want to waste a clock cycle for each value. Also is there any way to dump the large data (say 64k) in the ROM without having to initalize in actual handel C code vijArticle: 55878
Phil, O'il agree with ya there. (Folks are far too serious about this....must be the end of the spring quarter/semester, and all of the academics are bored?) Austin Phil Hays wrote: > > Austin Lesea wrote: > > > But why to they call it "field" when no one programs them while on the > > farm? > > What about in the oil fields? Or does that count? > > -- > Phil HaysArticle: 55879
Yu Haiwen, To simulate jitter, use the smallest period as a clock that can result from the peak to peak jitter. For example, if the clock is 300 MHz, with a period of 3.33 ns, and the jitter is 200 ps peak to peak, then the smallest period one can have is 3.33 - (1/2* .2) = 3.23 ns. See http://www.xilinx.com/support/techxclusives/slack-techX21.htm Then use the largest period. Thsi checks both setup, and hold problems. For skew, you must add delays into the simulation for the elements that are not part of the simulation circuit (may not be possible with some tools). Skew of some items are already modeled (ie the trace report shows the skew along the BUFG tree to various CLBs and IOBs). Austin Yu Haiwen wrote: > > Hi, > > I'm designing a clock gen module with virtex-II DCMs. > I can get the recommend timing parameters from datasheet, such as > frequency, period jitter, phase skew, and lock time. > For some parameters like frequency and lock time, it's easy to verify > when I do post-PAR simulation. > But for the others like jitter and skew, how can I simulate them to > get the exactly value for my application? > My work environment is ISE 5.1i + Modelsim SE. > > Thanks.Article: 55880
Marius, Superb link,required reading. Austin Marius Vollmer wrote: > > Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> writes: > > > Hal Murray <hmurray@suespammers.org> wrote: > > > > : Is the cost of fab lines following Moore's law? I suspect so, but > > > > Please, > > > > let's call it "Moore's observation". It's not a law! > > And it's wrong, too! :-) Here is a very interesting article: > > http://www.firstmonday.dk/issues/issue7_11/tuomi/ > > -- > GPG: D5D4E405 - 2F9B BCCC 8527 692A 04E3 331E FAF8 226A D5D4 E405Article: 55881
Hello, > I want to implement a state machine in a small PLD or FPGA > using some sort of HDL like AHDL, WinCUPL, etc. However, I > don't want to supply an external clock to the part. If your intent is to use an oscillator in the PLD itself, you would have to consult individual device datasheets. For example, the Xilinx Spartan and Spartan-XL (and XC4000, for that matter...) have a primitive called OSC4 that allows you to access the internal oscillator that is used during configuration. There are several frequencies available, but they are all plus or minus 50%... To use it, you'd need to use the correct schematic library element or -- if using an HDL -- instantiate the OSC4 unisim library component. > I'd like to know if it is possible to use an inverter inside > the CPLD, feeding back the output of the inverter to the input > of the inverter, thus creating a "clock". While this is possible, I don't think you want do to this. The power consumption is high. As someone else pointed out, you will have no control over the frequency, and it will be high (hundreds of megahertz). You'd likely have to divide it down so that you avoid running your design that fast... Additionally, it will vary from part to part, and as a function of temperature and supply voltage. > What I'm really trying to do is implement an asynchronous state > machine that changes state only when its inputs change, without > regard to clocks. I don't have a clock to supply to the system. What you have described is called a fundamental mode sequential circuit. At a basic level, an SR-latch is a fundamental mode sequential circuit. It changes "state" based on changes in the input signals. There is no "clock". The design and analysis of these types of circuits are tedious and complicated. Which is why people generally use a different design method for what are called pulse mode sequential circuits. If you want to learn more about fundamental mode sequential circuits, you might try Chapter 7 of Logic Design Principles by Edward McCluskey. > What I'm finding, though, is most HDLs assume state machines > are synchronous and expect a clock. I think what you are seeing is that most people writing with HDLs are targeting PLDs for implementation. The synthesis and implementation (timing analysis) tools are really geared around pulse mode sequential circuits -- those built using D flip flops -- because these D flip flops exist as primitives in the PLD devices. So code is written in a style that will infer D flop flops. Hope this helps, EricArticle: 55882
I think this is a language issue more than anything else. By that I mean nobody programs an x86 system with VHDL or Verilog (or schematics) although they could. However people are starting to program FPGAs in C, C++ and Java. There are timing issues in traditional processors. Load/Store operations, predictive branches, pipeline flushing, multiple ALUs and more. If a programmer had to understand all the nuances of each processor, programming traditional processors would be just as hard as programming FPGAs. What is different is that compiler writers and processor designers get together and try to understand what tradeoffs it takes to make everything work together. FPGA designers have not done this yet. They look at lots of static designs and try and make the underlying infrastructure as efficient as possible for those static designs. There is no easy way to do partial reconfiguration. The underlying configuration mechanism is so messy it is a nightmare to document and a headache to support. There is really no hooks put into a FPGA for updating single LUTs or routing resources. You have to update a whole column of bits across a huge chip. That is a one time loading model not a programming model. The good news is that with the Power PC and internal programming port FPGA designers will start to get more customer requests to be able to update the resources in some kind of coherent manner. I figure it will take another 2 or 3 device generations before we see parts that will work closely with C/C++ compiler technology. It's just a matter of time Ray, it's just a matter of time..... Steve "Ray Andraka" <ray@andraka.com> wrote in message news:3ECCCA61.5F70B588@andraka.com... > Perhaps, but it is different from the more traditional software in that there > are concurrency and timing issues that do not apply for traditional software. > The design flow is hardware, the result is perhaps software. For that reason, > it does make sense to differentiate it. I am constantly fighting the problems > introduced by people treating the FPGA contents as software when they do their > designs, and we see a fair amount of the results of that mentality here too. If > for no other reason than to avoid that leap, I think it is prudent to call it > something other than software. > > Steve Casselman wrote:Article: 55883
"Jim Ranlett" <ballsofsteel@rcsis.com> wrote in message news:53de32df.0305211648.7e8fcb54@posting.google.com... < snip > > What I'm really trying to do is implement an asynchronous state > machine that changes state only when its inputs change, without regard > to clocks. I don't have a clock to supply to the system. < snip > Greetings, Jim. For an asynchronous state machine to work, can you guarantee that the four inputs never change at (approximately) the same time? One of several reasons why synchronous state machines are used is that multiple input changes can be resolved on the same clock. If the events are asynchronous, the inputs would first be sampled with the system clock so that all bits - state machine bits and outputs - see the same input values so they can acto on those values over one clock period. If the inputs are asynchronous and *not* sampled, one state bit might think the input is zero and another state bit thinks it's a one. This leads to major confusion. If you can guarantee that only one input changes at a time (in-to-out time is smaller than the time between input changes) then an asynchronous state machine is possible, though still difficult. To discern between the "previous" and "next" states without confusion, either a clean synchronous approach or a "gray" coding scheme where only on bit changes for one input change would be needed. If the 13 states were all in sequence, you couldn't use a simple gray sequence because any true gray sequence is an even number of states. I did an asynchronous state machine in my early engineering days with a simple little ROM. A more experienced engineer said "it'll never work" but it did. Maybe I was lucky, because ROMs could produce glitches transitioning between bits of the same logic value. It's these kind of nuances you might have to watch out for. Good luck, - John_HArticle: 55884
Hi Harris, What you can do is use FPGA Editor to make such changes. You don't have to re-run par even. Just make the change and re-generate the bit file and you're good to go. Regards, Wei Alphaboran wrote: > Hello all, > > I have an already implemnted design and I want just to make a copy of it. > The only change I want is the value of some register (constant value), I am > thinking to change these values in my code and select an exact guided PAR > using the old ncd file. Is this the way to work or must I take further > actions? The problem is that there is a lot of floorplanning done and I > don't want to start over again doing that (keep the same PAR). > > Thanks a lot, > HarrisArticle: 55885
The issue isn't so much a slow link, the issue is dynamic graphic
intensive displays such as the waveform display in modelsim do not fare
well across VNC regardless of the network speed. I find myself forcing
refresh way to often on these apps. Not to say it isn't useful, it is
just that it is not as good as running on the same machine for
thosetype of things. I do use VNC, and I use it a lot.
Colin Marquardt wrote:
> Ray Andraka <ray@andraka.com> writes:
>
> > VNC is fine for text stuff. It leaves quite a bit to be desired
> > for looking at simulation traces though.
>
> For pure text stuff, nothing beats screen
> (http://www.math.fu-berlin.de/~guckes/screen/).
>
> On a slow link, one might try TightVNC (http://www.tightvnc.com/).
>
> Supposedly, NX from http://www.nomachine.com/ is also good, you can
> get the non-GUI stuff under the GPL license (it's not very obvious
> from their website).
>
> HTH,
> Colin
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55886Hi, we need help to accomplish a partial reconfiguration project. We use a Virtex FPGA on an XESS XSV300 development board. We use the SelectMAP method to configure the FPGA. The full bitstream is downloaded without any problem and the design is working properly. When we try to download the partial bitstream for some reason during reconfiguration the FPGA asserts the BUSY signal and the reconfiguration stops. As a result the previous design remains unaltered. We have followed all necessary steps specified by the Modular Design flow. Also at the BitGen Options we have set the Persist option at Yes and the ActiveReconfig:Yes. The Configuration clock is about 1 MHz and according to Xilinx papers there should be no problem with the BUSY signal. When we initiate the reconfiguration process we do not assert the /PROGRAM signal. We should finally mention that at this stage we have tried to keep things as simple as possible (no communication between the reconfigurable part and the rest of the FPGA and the circuit is a simple combinatorial design). Any suggestions on what goes wrong?Article: 55887
If you hold the INIT or PROGRAM pins low during power up does it matter if the power takes an extraordinarily long time to stabilize? ie. 400ms. Does INIT or PROGRAM need a falling edge? I was planning on just holding one or the other low during voltage stabilization and then releasing them after power is up. Does it matter if I use INIT or PROGRAM? Is one better than the other to use for what I need to do here? TIA, MichaelArticle: 55888
Also, I'll be using slave serial mode. Michael Bills wrote: > If you hold the INIT or PROGRAM pins low during power up does it matter > if the power takes an extraordinarily long time to stabilize? ie. 400ms. > > Does INIT or PROGRAM need a falling edge? I was planning on just > holding one or the other low during voltage stabilization and then > releasing them after power is up. Does it matter if I use INIT or > PROGRAM? Is one better than the other to use for what I need to do here? > > TIA, > Michael >Article: 55889
I agree with this stance. It's certainly not software. Gateware is a reasonable name for it, but it seems awkward. Software implies a certain flexibility and organization which is not generally applicable to programmable logic. When referring to the design process, I strictly call it hardware design. When referring to the object which is downloaded to the FPGA, I call it a bitfile. When referring to a board or system, I'll lump the configuration in with the firmware moniker. If you hear me refer to it as software, the light is green to jolt me with a cattle prod. Jake Ray Andraka <ray@andraka.com> wrote in message news:<3ECCCA61.5F70B588@andraka.com>... > Perhaps, but it is different from the more traditional software in that there > are concurrency and timing issues that do not apply for traditional software. > The design flow is hardware, the result is perhaps software. For that reason, > it does make sense to differentiate it. I am constantly fighting the problems > introduced by people treating the FPGA contents as software when they do their > designs, and we see a fair amount of the results of that mentality here too. If > for no other reason than to avoid that leap, I think it is prudent to call it > something other than software. > > Steve Casselman wrote: > > > I have always called it software. Since 1986. FPGAs are a kind of computer > > chip with a very strange programming model. The programming model was > > created by hardware engineers who were concerned about current spikes during > > programming. They were not concerned about reprogramming the device so much > > as just programming it the first time. They did not really care about > > programming parts of the device although that is starting to become more > > important as you get really large devices with embedded processors and > > internal programming ports. > > > > In the end it is software. It is based on sram it is updatable at any time. > > It can be stored on a disk or delievered over a network. > > > > It is software.. > > > > Steve > > > > "Joe Frese" <joefrese@hotmail.com> wrote in message > > news:c176b8c2.0305211126.6e642649@posting.google.com... > > > I've got a question of terminology for the group: is FPGA design > > > generally classified as hardware, firmware, or neither? Most of the > > > designs I've worked on have served to interface firmware with > > > hardware. It seems that firmware engineers like to think of FPGA > > > designs as more firmware, and that hardware engineers like to think of > > > FPGA designs as more hardware. As an FPGA developer, though, I'm of > > > the mind that the unique design considerations of the technology > > > justify a new and separate category . . . > > > > > > A coworker suggested the term "coreware," but apparently that's a > > > registered trademark of LSI Logic. Is there another term with the > > > -ware suffix commonly used to refer to code (VHDL, Verilog, or > > > otherwise) intended to be implemented in an FPGA? > > > > > > Joe > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 55890
Hi Ray, > I wasn't referring to the CAE tools as much as to all the other stuff you need > on the computer to do business. These include the CAE stuff of course, but also > a word processor (shouldn't be too much a problem, but might be compatability > issues with cusotmers), Matlab (needed for DSP apps), something to write PDF > files (Adobe Acrobat), a spreadsheet (Excel)(used for various things in the > course of a design), and in the case of a consulting business like mine, it also > includes quickbooks... I get your point, but your argument is starting to be a misconception. A few months back, after a defrag, the Windows 2000 partition on my dual-boot system refused to boot for some reason, and I decided to try to live the Linux Way 100% for a few weeks before trying hard to repair the problem. Initially it definitely wasn't easy but after a few days of Googling, downloading and in some cases compiling I got to pretty much 100% of the functionality I had under W2K. In your case, if you install either StarOffice or OpenOffice you'll have a fully-fledged word processor, an Excel-compatible spreadsheet, plus something that shows, reads and writes Powerpoint. Matlab runs on Linux, and the PDF printer driver comes for zilch with most distibutions as well. You've got ModelSim running better on Linux than on Windows, and Synplify and Precision are both available on Linux as well. As for your quickbooks, there's MoneyDance and GNUCash, I guess. Of course, this would all be a switch of choice: you would have to really want to invest time in relearning to use these tools. Likewise, I tried doing the above about two years ago, and at that time you would absolutely be right - but the landscape has changed considerably in the meantime. > The point is there is an awful lot of 'standard' stuff out there that is much more > hassle to get working under Linux than on an windoze machine... Find a spare PC, download a Stage1 livecd from Gentoo, follow the installation instructions, let the box sit in a corner a few days to finish compiling, and you'll be amazed ;-) Best regards, BenArticle: 55891
Hi I'm looking for project of nois generator in Xilinx. Kind regards.Article: 55892
I'm trying to implement two lpm_fifo 256x16 (4Kbit each one) in a Flex10k20 which has 6 EABs (12Kbit), when I synthesize only one lpm_fifo it fits on 2 EABs (correct) but when I try to synthesize two fifos in the same design MaxPlus says that it doesnt fit in that part because it need 8 EABs and it's needed a bigger device part. Which is the cause? Is it an error of MaxPlus or is there any limitation to instance several lpm blocks? Thank you. Dany.Article: 55893
I just found out that Altera have recently aquired a second DSP IP company, Siroyan, following closely after their aquisition of BOPS. Both companies developed high performance, scalable, synthesizable, VLIW DSP cores. How long before they snap up Improv? Anyone know what they are up to?Article: 55894
On a sunny day (Thu, 22 May 2003 13:30:50 +0200) it happened Mario Trams
<Mario.Trams@informatik.tu-chemnitz.de> wrote in
<baicda$7l6$1@narses.hrz.tu-chemnitz.de>:
>Robert wrote:
>
>
>> For me the biggest disadvantage in Webpack is that it lacks FPGA Editor.
>> Also Core Generator is not included.
>> The full comparison is here:
>>
>> http://www.xilinx.com/ise/devsys_feature_guide.pdf
>
>And another disadvantage is that the big devices are not supported ;-)
>
>Mario
>
A third disadvantage is that a 2 MB pdf that is unreadable on a 19 inch
monitor is used, for something that can be done in a 4 kB text file or small
html table if formatting MUST be.
This makes me wonder if the 90 MB webpack with 90 million code lines ????
could be reduced to 900 kB source and the uploaded as open source GPL for
a Linux version.
That could then have a non GUI interface, a makefile, a decent directory
structure that holds the HDL source files in a separate place, uses /tmp for
temp files, erases the temp files after use.
Then since there are some great programmers someone could perhaps feel
inspired to tackle improving things.
Will save Xilinx in the end on programmers, improve the product (like
Netscape Mozilla for example).
Of cause it should be in C not C++.
WOAAAAAAAAA
With Icarus verilog a huge part is already in the open source, I really
like that program.
So I think this is a valid proposition.
The other thing that irritates me about the win webpack is the fact that
the windows clog up the screen, you have to move things around to see the
errors, many error reports make no sense (or are plainly wrong), so a more
precise error reporting is a first requirement.
So then also a manual like the very good manual for libc (libc.info) with
a description of each function of the soft, each error report and how
and what to do with it.
And the design philosophy.
int main()
{
if(! do-it() )
{
printf("main(): You screwed up!\n");
exit(1);
}
exit(0);
}
int do-it()
{
if(! not my_sub() )
{
printf("do-it(): failed because of my-sub()\n");
return 0;
}
return 1;
}
int my_sub()
{
if(a != b)
{
printf("my_sub(): error: a is not equal b!\n");
return 0;
}
return 1;
}
along those lines anyways.
Jan
Article: 55895You have to be more specific. What kind of noise spectrum, what frequencies? And what is the application? Peter Alfke ========== Klix wrote: > > Hi > > I'm looking for project of nois generator in Xilinx. > > Kind regards.Article: 55896
For an example of a truly asynchronous state machine, see the Phase/Frequency detector circuit in the 4046 PLL chip. The Motorola datasheet has a state diagram for it, & some also have the schematic (built purely from NAND gates). As others have noted, such circuits are a bear to analyse. ballsofsteel@rcsis.com (Jim Ranlett) wrote: :I want to implement a state machine in a small PLD or FPGA using some :sort of HDL like AHDL, WinCUPL, etc. However, I don't want to supply :an external clock to the part. I'd like to know if it is possible to :use an inverter inside the CPLD, feeding back the output of the :inverter to the input of the inverter, thus creating a "clock". Then, :I want to attach that "clock" to the part's global clock net and use :that clock as the clock for my state machine. : :Is something like this possible? : :What I'm really trying to do is implement an asynchronous state :machine that changes state only when its inputs change, without regard :to clocks. I don't have a clock to supply to the system. What I'm :finding, though, is most HDLs assume state machines are synchronous :and expect a clock. (and reset, for that matter.) : :If I have to use a clock to implement the state machine, I would of :course have to synchronise the asynchronous inputs with the state :machine clock. Simple enough, but I'd really rather not have to :supply an external clock to the system if at all possible. : :I'm not limiting myself to any particular part of language, but I'd :like to try to keep to what I'm familiar with (AHDL, WinCUPL, etc.) :Other parts and HDL suggestions are welcome, especially those that :might have Async State Machine constructs. : :FYI, I expect the state machine to have 4 inputs, 4 outputs (the :outputs are NOT the state bits but different), and 13 defined states :(implying 4 state bits). : :(It seems that most HDLs default to D flipflops as the state bits, and :D-flops need a clock. Is there anyway to default to, say, a JK flop :and not require a clock, but derive next state equations for the J & K :inputs? A compiler that does this would be great, as I expect the :equations to be rather cumbersome for me to realize manually.) : :Thanks for any suggestions. : :Sincerely, :Jim RanlettArticle: 55897
Problem is I need 100% compatibility to the MS office stuff, most of my
customers use it and expect me to be able to read/write without hiccups. The
free pdf writer doesn't do so well with graphics, for that the distiller is the
preferred, and for the financial, quickbooks wasn't my choice, it is my
accountant's preference (plus I now have 9 years of business records in
quickbooks, so any new system would have to be able to read quickbooks files).
Yes, there are equivalent functions available for Linux, but not exact
equivalents. I do have a Linux machine running here, so far only for a backup
on a different OS to help guard against a fast moving virus.
Ben Twijnstra wrote:
> Hi Ray,
>
> > I wasn't referring to the CAE tools as much as to all the other stuff you
> need
> > on the computer to do business. These include the CAE stuff of course,
> but also
> > a word processor (shouldn't be too much a problem, but might be
> compatability
> > issues with cusotmers), Matlab (needed for DSP apps), something to write
> PDF
> > files (Adobe Acrobat), a spreadsheet (Excel)(used for various things in
> the
> > course of a design), and in the case of a consulting business like mine,
> it also
> > includes quickbooks...
>
> I get your point, but your argument is starting to be a misconception.
>
> A few months back, after a defrag, the Windows 2000 partition on my
> dual-boot system refused to boot for some reason, and I decided to try to
> live the Linux Way 100% for a few weeks before trying hard to repair the
> problem. Initially it definitely wasn't easy but after a few days of
> Googling, downloading and in some cases compiling I got to pretty much 100%
> of the functionality I had under W2K.
>
> In your case, if you install either StarOffice or OpenOffice you'll have a
> fully-fledged word processor, an Excel-compatible spreadsheet, plus
> something that shows, reads and writes Powerpoint. Matlab runs on Linux, and
> the PDF printer driver comes for zilch with most distibutions as well.
> You've got ModelSim running better on Linux than on Windows, and Synplify
> and Precision are both available on Linux as well. As for your quickbooks,
> there's MoneyDance and GNUCash, I guess.
>
> Of course, this would all be a switch of choice: you would have to really
> want to invest time in relearning to use these tools. Likewise, I tried
> doing the above about two years ago, and at that time you would absolutely
> be right - but the landscape has changed considerably in the meantime.
>
> > The point is there is an awful lot of 'standard' stuff out there that is
> much more
> > hassle to get working under Linux than on an windoze machine...
>
> Find a spare PC, download a Stage1 livecd from Gentoo, follow the
> installation instructions, let the box sit in a corner a few days to finish
> compiling, and you'll be amazed ;-)
>
> Best regards,
>
> Ben
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55898
There are a couple of people who insist on calling FPGA whatever-ware
'software' who should be jolted with that there cattle-prod! Better yet, I think
those people should be made to clean up messes left by people who attempt
FPGA designs as software projects with no inkling of what hardware is, much
less what their code is going to create.
Jake Janovetz wrote:
> I agree with this stance. It's certainly not software. Gateware is a
> reasonable name for it, but it seems awkward. Software implies a
> certain flexibility and organization which is not generally applicable
> to programmable logic. When referring to the design process, I
> strictly call it hardware design. When referring to the object which
> is downloaded to the FPGA, I call it a bitfile. When referring to a
> board or system, I'll lump the configuration in with the firmware
> moniker. If you hear me refer to it as software, the light is green
> to jolt me with a cattle prod.
>
> Jake
>
> Ray Andraka <ray@andraka.com> wrote in message news:<3ECCCA61.5F70B588@andraka.com>...
> > Perhaps, but it is different from the more traditional software in that there
> > are concurrency and timing issues that do not apply for traditional software.
> > The design flow is hardware, the result is perhaps software. For that reason,
> > it does make sense to differentiate it. I am constantly fighting the problems
> > introduced by people treating the FPGA contents as software when they do their
> > designs, and we see a fair amount of the results of that mentality here too. If
> > for no other reason than to avoid that leap, I think it is prudent to call it
> > something other than software.
> >
> > Steve Casselman wrote:
> >
> > > I have always called it software. Since 1986. FPGAs are a kind of computer
> > > chip with a very strange programming model. The programming model was
> > > created by hardware engineers who were concerned about current spikes during
> > > programming. They were not concerned about reprogramming the device so much
> > > as just programming it the first time. They did not really care about
> > > programming parts of the device although that is starting to become more
> > > important as you get really large devices with embedded processors and
> > > internal programming ports.
> > >
> > > In the end it is software. It is based on sram it is updatable at any time.
> > > It can be stored on a disk or delievered over a network.
> > >
> > > It is software..
> > >
> > > Steve
> > >
> > > "Joe Frese" <joefrese@hotmail.com> wrote in message
> > > news:c176b8c2.0305211126.6e642649@posting.google.com...
> > > > I've got a question of terminology for the group: is FPGA design
> > > > generally classified as hardware, firmware, or neither? Most of the
> > > > designs I've worked on have served to interface firmware with
> > > > hardware. It seems that firmware engineers like to think of FPGA
> > > > designs as more firmware, and that hardware engineers like to think of
> > > > FPGA designs as more hardware. As an FPGA developer, though, I'm of
> > > > the mind that the unique design considerations of the technology
> > > > justify a new and separate category . . .
> > > >
> > > > A coworker suggested the term "coreware," but apparently that's a
> > > > registered trademark of LSI Logic. Is there another term with the
> > > > -ware suffix commonly used to refer to code (VHDL, Verilog, or
> > > > otherwise) intended to be implemented in an FPGA?
> > > >
> > > > Joe
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55899Ray Andraka wrote: > Problem is I need 100% compatibility to the MS office stuff, most of my > customers use it and expect me to be able to read/write without hiccups. The > free pdf writer doesn't do so well with graphics, for that the distiller is the > preferred... > Oddly enough, awhile back I had a problem with a customer where some were using PCs and some Macs, and the Mac users were having a problem reading the graphics in a document written with MS Word on a PC. So I read it into Linux, converted it to PDF with Linux tools and sent a perfect document with perfect graphics back to the Mac users. So much for the MS standard. -- My real email is akamail.com@dclark (or something like that).
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