Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
"LIJO" <lijo_eceNOSPAM@hotmail.com> wrote in message news:<b9vke7$nsqva$1@ID-159866.news.dfncis.de>... > hi all, > can anyone tell me which state machine is good (Moore or Mealy).. Why? > > rgds, I would recommend to read the following two excellent papers from Sunburst Design Web site: http://www.sunburst-design.com/papers/CummingsSNUG1998SJ_FSM_rev1_1.pdf and http://www.sunburst-design.com/papers/CummingsSNUG2000Boston_FSM_rev1_2.pdf Regards, AlexanderArticle: 55726
I would like to ask what are the restrictions of ModelSim XEII Starter and what FPGA chips does it support. Any pointers are appreciated. Thanks. Regards, IsabelArticle: 55727
"Isabel" <hmip0@ie.cuhk.edu.hk> schrieb im Newsbeitrag news:3EC64A12.1010000@ie.cuhk.edu.hk... > I would like to ask what are the restrictions of ModelSim XEII Starter > and what FPGA chips does it support. Any pointers are appreciated. Up to 500 lines VHDL, it will run at normal (=maximum) speed. Up to 2000 (?) lines it will run with 10% of the speed, then it will drop to 1% or less. AFAIK all chips are supported. -- MfG FalkArticle: 55728
Greg, thanks for your explanation and the link. I was only looking for literature of the devices I'm actually using. But there is a lot more info on a little bit older devices than Cyclone. I expect the output buffer of the Cyclone are simmilar with the of Stratix. About simulation: I would like to simulate my load, but I've only SPICE and no tool for ISIS modles. But I think there are no SPICE models available (for both A and X), right? Martin -- -------------------------------------------------------- JOP - a Java Processor core for FPGAs now on Cyclone: http://www.jopdesign.com/cyclone/ "Greg Steinke" <gregs@altera.com> schrieb im Newsbeitrag news:5c1de958.0305161617.221ec4ec@posting.google.com... > Martin, > As my colleague has pointed out, the change in the slew rate is very > much dependent on your load and so should be simulated with IBIS or > SPICE. We (and other FPGA companies) do publish tables of IO adders > for various IO standards, slew rates, and drive strengths. These are > used to determine the tCO of the device for different cases, although > assuming a standard load such as 10 pF for LVTTL. While this can give > you an idea of the tCO difference between fast and slow slew rate, > analog simulation is necessary for full understanding. There is a > difference between edge rate and tCO variation (for example a 2 ns > delay does not mean that the edge rate is 2 ns longer) but this can > help you determine if the tCO of the device with slow slew rate on > will meet your requirements. > > For example, page 4-57 of the Stratix Handbook shows the IO adders for > various IO standards when fast slew rate is used, while 4-59 shows the > IO adders when slow slew rate is used. The Stratix handbook is > available here: > http://www.altera.com/literature/lit-stx.html?xy=dev_sdh > > Also please note that Quartus II software will show different input > and output buffer delays depending on what IO standard is used, but > again assuming the standard load for that IO standard. > > Sincerely, > Greg Steinke > gregs@altera.com > > > "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:<c2Kta.61402$e8.646243@news.chello.at>... > > Greg, > > thanks for the information. It would be nice if the change of the slew rate > > could be stated in the datasheet. You don't always want to run a simulation > > (with tools you don't have access to) to get a simple information like: > > When I turn the slow sr on, do I meet my timing e.g. for an async. ram? > > > > Sorry for my ignorance about the IBIS models on the web. > > > > MartinArticle: 55729
Peter, on my actual board the trace length from the FPGA to the SRAM are under 10 mm (the RAMs are on the back side of the board under the FPGA pins). With so short traces I think I've only the capacitive load. But it really depends on the slew rate. If you can slow it down to e.g. 2 ns you can still treat it as a lumped system for traces up to 5 cm. According to Johnson, High-Speed Digital Design: Length of rising edge l = Tr/D Tr rise time, D delay time (140-180 ps/inch on FR4 PCB), Circuits smaller than l/6 are lumped circuits. Martin -- -------------------------------------------------------- JOP - a Java Processor core for FPGAs now on Cyclone: http://www.jopdesign.com/cyclone/ "Peter Alfke" <peter@xilinx.com> schrieb im Newsbeitrag news:3EC582A6.915B3981@xilinx.com... > I agree with Greg ( isn't that nice, X and A agreeing?) but let me add > something that again applies to X and A and others: > At the modern transition times, many if not most interconnects must be > seen as transmission lines, and not as lumped capacitive loads. So, a > long trace is not a large capacitive load, but rather a 50 Ohm (?) > transmission line = a resistive load, without any (!) capacitance and > the edge rate remains pretty steep. But you better terminate that > transmission line somewhere, or you get very bad signal integrity... > Just my $ 0.02 worth. > > Peter Alfke, Xilinx Applications > ===================== > Greg Steinke wrote: > > > > Martin, > > As my colleague has pointed out, the change in the slew rate is very > > much dependent on your load and so should be simulated with IBIS or > > SPICE. We (and other FPGA companies) do publish tables of IO adders > > for various IO standards, slew rates, and drive strengths. These are > > used to determine the tCO of the device for different cases, although > > assuming a standard load such as 10 pF for LVTTL. While this can give > > you an idea of the tCO difference between fast and slow slew rate, > > analog simulation is necessary for full understanding. There is a > > difference between edge rate and tCO variation (for example a 2 ns > > delay does not mean that the edge rate is 2 ns longer) but this can > > help you determine if the tCO of the device with slow slew rate on > > will meet your requirements. > > > > For example, page 4-57 of the Stratix Handbook shows the IO adders for > > various IO standards when fast slew rate is used, while 4-59 shows the > > IO adders when slow slew rate is used. The Stratix handbook is > > available here: > > http://www.altera.com/literature/lit-stx.html?xy=dev_sdh > > > > Also please note that Quartus II software will show different input > > and output buffer delays depending on what IO standard is used, but > > again assuming the standard load for that IO standard. > > > > Sincerely, > > Greg Steinke > > gregs@altera.com > > > > "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:<c2Kta.61402$e8.646243@news.chello.at>... > > > Greg, > > > thanks for the information. It would be nice if the change of the slew rate > > > could be stated in the datasheet. You don't always want to run a simulation > > > (with tools you don't have access to) to get a simple information like: > > > When I turn the slow sr on, do I meet my timing e.g. for an async. ram? > > > > > > Sorry for my ignorance about the IBIS models on the web. > > > > > > MartinArticle: 55730
"Isabel" <hmip0@ie.cuhk.edu.hk> wrote in message news:3EC64A12.1010000@ie.cuhk.edu.hk... > I would like to ask what are the restrictions of ModelSim XEII Starter > and what FPGA chips does it support. Any pointers are appreciated. Go to http://www.xilinx.com/xlnx/xil_tt_home.jsp , then click on ModelSim Xilinx Edition II, then clik on FAQ and then look at Q6.Article: 55731
I am working on a new design that will go to production (hopefully) by Q4. If I can get even small quantities of the XC3S400-4FG456C before the end of the year, I would be able to use this new part. I have been told that the XC3S1000 is sampling now and I can expect to get a few of those by summer for my prototypes. But I would have to have the XC3S400 for any production. I can't ship a different size FPGA since we will have to support it indefinitely and we would be using the XC3S400 in production for cost. Anyone heard what the schedule on the XC3S400 part is? I have a request in to a disti for dates on samples and production, but I don't expect to hear back for a week or more. I am wondering if anyone else has gotten an answer to the same question. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55732
I have written a core in XDL. I want to use the PAR tools. I've never been able to figure out how to route from an output pin to an input pin and make sure it goes through "a specific wire", but I want to. If you figure it out, let me know at dereckaf@yahoo.com Thanks DereckArticle: 55733
Hi, I've been using Xilinx Project Navigator in ISE 5.2i, and it doesn't seem to be able to control some of the more advanced features in the tool flow (timing driven packing in the mapper for example). Is the Project Navigator intended to be a tool for the less experienced Xilinx user only, or are there any expert/power users out there using it? - SheldonArticle: 55734
In article <62f02004.0305171606.2a363808@posting.google.com>, Sheldon D. <sd_email03@yahoo.com> wrote: > >I've been using Xilinx Project Navigator in ISE 5.2i, and it doesn't >seem to be able to control some of the more advanced features in the >tool flow (timing driven packing in the mapper for example). I'm not sure which specific feature you mean, but you can get to a lot of things from the process window. You can right click and get "properties" for almost every process, some of which are extensive. -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 55735
Try Edit->Preferences->Processes, select Advanced "Sheldon D." <sd_email03@yahoo.com> 写入消息新闻 :62f02004.0305171606.2a363808@posting.google.com... > Hi, > > I've been using Xilinx Project Navigator in ISE 5.2i, and it doesn't > seem to be able to control some of the more advanced features in the > tool flow (timing driven packing in the mapper for example). Is the > Project Navigator intended to be a tool for the less experienced > Xilinx user only, or are there any expert/power users out there using > it? > > - SheldonArticle: 55736
I always assumed that there was no difference between the two, but I have been told that they are handled differently by the simulator. I've never bothered tracking that down. I personally prefer to use assign whenever possible. I have worked places where always blocks were completely forbidden (assign, functions and instantiated flops only) because of potential inter-module race conditions under esoteric circumstances. There is no physical significance to a reg other than it is a way to allocate memory to a variable for simulation. Bruce "geeko" <jibin@ushustech.com> wrote in message news:b9na79$l03s4$1@ID-159027.news.dfncis.de... > Hi all > I have some questions about the modelling of combinational logic > using verilog . an AND gate can be modelled using the wire construct as > shown below . > > > module ( a, b, y); > input a, b; > output y; > wire a, b, y; > assign y = a & b; > endmodule > > > The same circut can also be modelled with a reg construct . > > > > module ( a, b, y); > input a, b; > output y; > reg y; > wire a, b; > always @ ( a or b) > y = a & b; > endmodule > > > Which description is considered as the best.What exactly the physical > significance of a reg constuct > > cheers > > > > > >Article: 55737
Hey, Xilinx has the user-friendly webpack for designing circuits without the basic need of learning a programming language. I'm looking for other useful types of circuits with similar tools since I have no time or desire to learn a more or less complex language. Do you know of other circuits with simple GUI's? I'm interested in anything from simple logic circuits to more complex microprocessors. Feel free to flame me for being lazy :-) But it also costs alot for the company to send electronic designers on programming courses...Article: 55738
Hello everyone, We are working on a project in which we have to detect the automatic meter reading measured by an energy metering ic, store it in eeprom and send it either through infrared media or power line modem to a user who wishes to find out his electricity bill for a particular month in a particular year. For this we want to know how to interface an enrgy metering ic like ADE7757 with a cpld like Xilinx Coolrunner etc. Also how to interface a cpld with eeprom as well as real time clock. if you have an answer to this, please let us know, or you can send us the links where we can get the information. Thank you.Article: 55739
Hal Murray wrote: > [TQFP/BGA to DIP adapter cards] > PCBExpress offers solder masks and a toaster oven recipe. Does anyone in Europe offer this mini-solder mask service?Article: 55740
hi, do you know if there is a vhdl description or any other (synthesizable) describtion of the SID chip (6581/6582) ?? thanks and byeArticle: 55741
"Daniel Fichtner" <daniel2323de@yahoo.de> wrote in message news:cd8e70cd.0305180532.1801e4b0@posting.google.com... > hi, > > do you know if there is a vhdl description or any other (synthesizable) > describtion of the SID chip (6581/6582) ?? > > thanks and bye Try http://www.opencores.orgArticle: 55742
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> writes:
> Hal Murray <hmurray@suespammers.org> wrote:
>
> : Is the cost of fab lines following Moore's law? I suspect so, but
>
> Please,
>
> let's call it "Moore's observation". It's not a law!
And it's wrong, too! :-) Here is a very interesting article:
http://www.firstmonday.dk/issues/issue7_11/tuomi/
--
GPG: D5D4E405 - 2F9B BCCC 8527 692A 04E3 331E FAF8 226A D5D4 E405
Article: 55743On some telecom devices boards I have found some CPLDs EPM7032QI44-15, unfortunately on the site of the Altera it is not it traces of it. Are these CPLDs compatible JTAG? Byez.Article: 55744
> > do you know if there is a vhdl description or any other (synthesizable) > > describtion of the SID chip (6581/6582) ?? > > > > thanks and bye > > Try http://www.opencores.org And ... ? Just a 6502 there.Article: 55745
> For this we want to know how to interface an enrgy metering ic like > ADE7757 with a cpld like Xilinx Coolrunner etc. Also how to interface > a cpld with eeprom as well as real time clock. This sounds as if you should be using a microcontroller instead of a CPLD. It does not seem you have been doing a lot of research on your own. Most of what you are asking for should be covered in application notes available from the device vendors..Article: 55746
> Then it is a pain. If it has an assembler OR it has a c compiler, then > it is really much more fun. The good old xr16 and gr0040/gr1040 are among the smallest C programmable FPGA CPUs, coming in at about 1/4 to 1/3 of the LUT count of MicroBlaze. Jan Gray, Gray Research LLC FPGA CPU News: www.fpgacpu.org [alas, too busy to update it lately]Article: 55747
"lc" <cupido@kkk.mail.ua.pt> wrote in message news:<1053038695.922327@newsfront2>... > Hello, > > What would be the simplest and smallest CPU core for an FPGA ? > I saw a lot of cores that mimic existing controllers > but I would not mind to have something simpler. > Low LE count is my goal. > > Anybody had similar objectives? Any ideas ? > Would somebody point me in the right direction ? > Hmmm, is 30% of Spartan II-50 to big ? Check out: http://www.opencores.org/projects/minirisc Could be even made smaller if you take out WDT and timer/counter ... Regards, rudi ------------------------------------------------------- www.asics.ws -- Solutions for your ASIC/FPGA needs --- ---------------- FPGAs * Full Custom ICs * IP Cores --- * * * FREE IP Cores --> http://www.asics.ws/ <-- * * * > Thanks. > > Luis Cupido. > > P.S. - The application is logic intensive (a very large correlator) > however the system output happens only once every second. > Using logic for the output processing become tremendously big, > a total waist of resources for something that happens only once > every second.Article: 55748
Is there a good way to do clock recovery (from, say, an 8B/10B data stream) on a 300Mbps data using a Xilinx without the use of any external PLL or analog components? -KevinArticle: 55749
In comp.arch.fpga Tim <tim@rockylogic.com.nooospam.com> wrote: : Hal Murray wrote: :> [TQFP/BGA to DIP adapter cards] :> PCBExpress offers solder masks and a toaster oven recipe. : Does anyone in Europe offer this mini-solder mask service? http://www.schablone.de Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z