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ron wrote: > I'm using Virtex FPGA and I want to implement a gated clock. How do I go about this? Easiest way: use the gate signal as a clock enable to the flipflops. -- Phil HaysArticle: 54251
rathanon99@yahoo.com (ron) wrote in message news:<c661162.0304050134.50813aa8@posting.google.com>... > I'm using Virtex FPGA and I want to implement a gated clock. How do I go about this? If you use a real gated clock ie CK & EN, the wire output will make for a very poor clock, its not worth it unless you really know what you are doing. Instead add an extra data hold state on the Flop node for each and every case, so if (!EN) Din = Q; else // rest of Din....Article: 54252
Kevin Brace wrote: > > Scott, > > If you already have a separate synthesis tool or a schematic tool, you > can use ISE Classic which is a backend only tool (Doesn't come with a > synthesis tool which might be a problem.) that supports most XC4000 > series FPGAs. > > Kevin Brace (If someone wants to respond to what I wrote, I prefer if > you will do so within the newsgroup.) > > Scott wrote: > > > > Well I'm desiging a 4 bit ALU, I'm using the XC4010XL FPGA, which is fairly > > outdated and is why I needed to use 2.1, because the webpack doesnt support > > that chip. > > Here is a link for the classic tools. Please keep in touch to let us know how well this works for you. http://www.xilinx.com/ise_classics/index.htm -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54253
My previous post should read _8_ 9x9 multipliers, _4_ 18x18 or 1 36x36 multiply per MAC block in Stratix/Stratix GX/Cyclone (thanks Pete for pointing this out). To instantiate multipliers, use the lpm_mult component. Quartus will automatically map each of your multipliers into DSP blocks or into LABs, depending on the size of your multiplier and the number of multipliers in your design, or you can explicitly tell it to use dedicated hardware through the DEDICATED_MULTIPLIER_CIRCUITRY property. Also, it's worth pointing out that the M512 (in Stratix) and M4K (in Stratix and Cyclone) memory blocks can be used to implement "soft" multipliers. These multipliers significantly increase the number of multiplies you can perform in a device, and are fast (similar to DSP block speed). These can be instantied through the MegaWizard (the ALTMEMMULT component). Quartus automatically figures out whether to use M512 or M4K memory blocks depending on the size of your multiplier, and the memory usage in your part. A couple references for those interested in reading more: http://www.altera.com/products/devices/stratix/features/stx-sof_multipliers.html http://www.altera.com/corporate/news_room/releases/products/nr-stx_dsp_multipliers.html AN246 describes how you can use soft multipliers in Stratix, looking specifically at FIR filter applications: http://www.altera.com/literature/an/an246.pdf Regards, Paul Leventis Altera Corp. > FYI, Altera's Stratix and Stratix GX devices come with a number of DSP > blocks. Each can be configured as 4 9x9 multipliers, 2 18x18, or 1 36x36. > Each also incorporates two adder/subtractor/accumulator units, and can do > various permutations of multiply and add operations, with optional > accumulate and pipelining. They are most definitely appropriate for a > function such as this. > > You can read up more at http://www.altera.com/products/devices/stratix.Article: 54254
praveenkumar1979@rediffmail.com (praveen) wrote in message news:<ff8a3afb.0304030223.27adcdcf@posting.google.com>... > Hello sirs/friends, > I didnot understand how will i pipeline parity checker. Can please > tell in detail. > how will i find parity, whether xor all 36 bits in one shot or is > there any efficient way of finding the parity? > should i have parity generator and parity generator as separate > module. > what is function of dataflow logic in PCI core? > > waiting for your reply > praveen A pipelined parity checker is a 36-bit input register, 36-bit XOR combinatorial logic, and a register on the XOR output. The registers can be free-running (no clock-enable), and should run on the PCI clock. The parity combinatorial logic depends on both your chip (FPGA? ASIC? CPLD?) and your synthesis tool. In theory, if you use an FPGA with 4-input LUTs, you need only 3 levels of logic for 36-bit parity (each LUT can be 4-input XOR). 3 levels of logic is easily fast enough for 33-MHz PCI, as long as you make sure the interconnects are not too slow (in most modern FPGAs, as well as most ASICs, routing delays are larger than logic delays). I'd suggest that you start with the simplest approach - write the parity logic as a simple HDL equation (VHDL: for x in 0 to 35 loop result := result xor latched_input(x) ; of course you can write result := latched_input(35) xor latched_input(34) xor... but this is too much writing for a lazy guy like me), run it through your tool-chain and see what you get. If the results are poor, try different styles until you get a good result - each tool-chain may require a different programmint style.Article: 54255
nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) wrote in message > > Chip on board has been quite common for years in some high volume > apps. When those virtual pets/tomogochi thingies first came out, I > picked one up to "dissect" [1]. The chip was about 3mm on a side or > so, chip on board under a blob of expoxy. The coolest part was the > LCD connection, which were two zebra-connectors. > > > [1] well, actually, it was vivisection, we kept it on as long as > possible. :) I like to do the same thing ! Here in Asia all kids have mobile phone, so accessories for them are really popular. Recently I picked up a little clear plastic figure (teddy-bear) about 1 inch high. Inside was a small PCB with a chip under some epoxy (didn't pop the epoxy yet) in the middle and 3 different color LEDs (also directly on the PCB with some clear epoxy on top) around the chip. On the other side of the PCB (which is about 1/3 inch in diameter) is a button battery cell. A piece of copper wire is used as an antenna. Whenever you use your cell phone, the entire thing lights up, in some sort of "chasing pattern". Really bright and nice ! (Actually any RF signal strong enough sets this little thing off, even my desk neon light does it sometimes !). Cheers ! rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores --> http://www.asics.ws/ <--- ----- ALL SPAM forwarded to: UCE@FTC.GOV -----Article: 54256
eternal_nan@yahoo.com (Ljubisa Bajic) wrote in message news:<9b0afb2c.0304041927.e174b@posting.google.com>... > > And finally, from another posting in the same thread: > >> 4. Still have a job, too. How many positions are open for ASIC >> designers? Are you one of the very lucky, very few, still employed? > Talk about poison. > It sounds almost as if Austin is deriving joy out of pointing out that > lots of our coleagues out there are jobless. I think that is just not > nice, and it is mainly seeing this posting that motivated me to write > my 'poisonous' posting. Just for the record, I know many people > (ex-coworkers or friends) in all facets of electronics that have lost > their jobs recently. I do not think ASIC designers are any more > affected than anyone else (except, perhaps experienced analog ic > designers). In either case, as you said, there is no reason to insult > each other. > > As far as your observation about the reduced number of ASIC starts, > wouldn't you say it is plausable that many companies are implementing > anything they can in FPGAs due to the economic uncertainty and unclear > market outlook? I would expect a large number of these will be > converted to ASICs when the outlook becomes clearer and at that point > Xilinx and Altera will lose some sales. Of course, I could be wrong. > As history books teach us, every recession ends up sooner or later. The economy comes back to prosper. The same history books point out - it never returns the same as it was before the crisis. After all, Hegel figured it out almost 200 years ago, didn't he ? After a big crisis changes tend to be more radical. It's common to think that as a result of the deep crisis of the 70's major parts of the Western economy made a transfer from industrial age to the post-industrial one. The current crisis of the electronic industry is pretty deep by any standards. We just can't assume that after return of prosperity the industry will look the same as in the hot days of the internet boom. May be we will see a transition from the industrial age (high volumes, low variety products) to the post-industrial endless customization ? Then the future of ASIC industry is not very bright for the obvious reasons. On the other hand, it is possible that the current state was more like pre-industrial period and the industrial revolution is just coming. In that case we can expect most of the core development work done by very few huge corporations. Their standard products would be reused like a Lego over and again by the minor industry player. In this scenario the future of the ASIC developers is not very bright either, apart, of coarse, of the relatively few lucky ones which got the job in the big shop. Most FPGA developers would survive better in this situation.Article: 54257
I have the opportunity to buy a full-blown Xilinx Foundation version 1.5 for $20 or so. My employer is willing to purchase the latest version of Foundation for $2500, but every dollar counts so I don't want to do it unnecessarily. Would it be a poor investment of my time to mess with the older software, i.e. is the newer version so much better and more feature-packed that it's not worth trying to save money in this way? I think the Xilinx FPGA devices I'd be using would be covered by the old software. One thing I'm not sure about is the DDS core they offer with Foundation. I'd like to use it, but I don't know whether it was in 1.5.Article: 54258
In article <Fc_ja.6390$Sd.6126@fed1read01>, Just Me <phony@nowhere.cc> wrote: >I have the opportunity to buy a full-blown Xilinx Foundation version 1.5 for >$20 or so. My employer is willing to purchase the latest version of >Foundation for $2500, but every dollar counts so I don't want to do it >unnecessarily. Would it be a poor investment of my time to mess with the >older software, i.e. is the newer version so much better and more >feature-packed that it's not worth trying to save money in this way? I think >the Xilinx FPGA devices I'd be using would be covered by the old software. >One thing I'm not sure about is the DDS core they offer with Foundation. I'd >like to use it, but I don't know whether it was in 1.5. Foundation 1.5 is so old as to be a useless fossil, and if you ARE using parts which are covered by 1.5, frankly there is something wrong with your design. If you want to experiment, download the "free beer" Webpack from Xilinx, it supports the smaller sized versions of all the latest parts. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 54259
On Sun, 06 Apr 2003 14:19:14 -0400, Just Me wrote: > I have the opportunity to buy a full-blown Xilinx Foundation version 1.5 > for $20 or so. My employer is willing to purchase the latest version of > Foundation for $2500, but every dollar counts so I don't want to do it > unnecessarily. Would it be a poor investment of my time to mess with the > older software, i.e. is the newer version so much better and more > feature-packed that it's not worth trying to save money in this way? I > think the Xilinx FPGA devices I'd be using would be covered by the old > software. One thing I'm not sure about is the DDS core they offer with > Foundation. I'd like to use it, but I don't know whether it was in 1.5. Version 1.5 is completely useless, buy the latest version. Not only doesn't 1.5 support any of the current devices but it's also much buggier than the current version. Xilinx made a major transition from the old XACT toolset to the Foundation series at that time. As the rev number 1.5 indicates it's the first generation of the foundation tools. The current version is 5.2, it's a much more mature toolset now.Article: 54260
Leon Heller wrote: > > "Leon Heller" <leon_heller@hotmail.com> wrote in message > news:b4huqe$ks4$1@venus.btinternet.com... > > I've searched the Xilinx web site but can't seem to find the Excel > > spreadsheets for the Spartan-IIE pinouts. I've previously downloaded them > > for the Spartan-II, but can't remember where they came from, which would > > help. > > Someone from Xilinx very kindly provided me with these. It looks like they > are not available via the web site. If anyone else needs them, I can email > it to them. Odd. I seem to recall that they used to make these available on the web site, but maybe I am remembering an FAE posting here that they would look into doing that. In any event, I would appreciate copies of the files. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54261
Kevin, Because Xilinx did the same thing a year and a half ago. Basically, both used OEM'd synthesis tools for their 5V FPGAs. Altera used Leonardo, Xilinx used Foundation. Both have terminated their OEM agreements. Xilinx currently has -zero- synthesis tools for their 5V FPGAs. And no intention to get them. At last with Altera, you can still use Max+II. $.02, SH On Fri, 04 Apr 2003 23:10:17 -0600, Kevin Brace <kev0inbrac1eusen2et@ho3tmail.c4om> wrote: >Paul, > >I don't mean to start an A vs. X argument here, if you don't like what >Altera did to you, why not switch to Xilinx?Article: 54262
I was reading the thread on the possibly new Spartan-3 parts and saw the link that mentions support in the new 5.2 Web pack tools. This document clearly says, "The Spartan-3 family and all its devices are now available in ISE 5.2i" and further lists "3S50, 3S200, 3S400, 3S1500, and 3S2000". I have searced the Xilinx web site and their search engine finds no mention of Spartan-3 parts, other than the reference in the Webpack release doc. The Webpack does not have a chip editor. Anyone know of any other source of info on these parts? Should they be considered to be way in the future rather than something to be considered in a near future design? I would love to get a cheap part that does not have the startup current problem! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54263
Just a comment here: Forget all about Xilinx 4000's and Spartans. They have NO synthesis support from Xilinx. Ain't going to happen. You said "one of my courses". You're teaching. Money is an issue, eh? Swich over to a modern, supported part. Save yourself money in the long run. BTDT, SH On Fri, 4 Apr 2003 15:57:36 -0500, "Scott" <scott_howes@hotmail.com> wrote: >Yeah I am sort of considering doing that, it's just learning and figuring >out what software I'm going to use to program the design and to deign the >ALU. All I'm planning on doing is having 2 four bit numbers as inputs and >the output will be displayed on a seven segment display or something. It is >meant to be a simple exersise in one of my courses to introduce us to >FPGA's. > >> What exactly are your I/O requirements. Could you get a PQFP socket, >> wirewrap, and a Spartain part from digikey? >> >> -- >> Nicholas C. Weaver nweaver@cs.berkeley.edu >Article: 54264
In addition to what the others have said, there is one more problem. Xilinx will NOT issue you a new run-time license. Period. So it's 100% useless. (Download webpack) On Sun, 6 Apr 2003 11:19:14 -0700, "Just Me" <phony@nowhere.cc> wrote: >I have the opportunity to buy a full-blown Xilinx Foundation version 1.5 for >$20 or so. My employer is willing to purchase the latest version of >Foundation for $2500, but every dollar counts so I don't want to do it >unnecessarily. Would it be a poor investment of my time to mess with the >older software, i.e. is the newer version so much better and more >feature-packed that it's not worth trying to save money in this way? I think >the Xilinx FPGA devices I'd be using would be covered by the old software. >One thing I'm not sure about is the DDS core they offer with Foundation. I'd >like to use it, but I don't know whether it was in 1.5. >Article: 54265
Hi,
I seem to have solved the problem. My clock is being switched on
external to the FPGA at power up of the board. I am not sure, but it
appears that the clock being switched on is generating some transients that
keep the system from locking. (Note: the oscillator is not being switched
on/off, just a series switch. The clock is being distributed as an ECL
signal and being converted to LVTTL external to the FPGA.) The solution is
to replace the
rst=>zero
line with
rst =>delayed_zero
where delayed_zero is generated by a counter that starts at start-up and
generates a zero after about 160 milliseconds.
This seems to work consistently. Also, U7's clock is now connected to
buf_clk which may help a little bit.
"Theron Hicks" <hicksthe@egr.msu.edu> wrote in message
news:3E8F3C72.1DA07CF5@egr.msu.edu...
> Hi,
> I appear to have a problem with a dll in a Spartan2E. I am
> attempting to use a 102.4MHz clock to get timing results at a
> granularity of a 409.6MHz clock. To do so I am using a lowspeed DLL to
> double the clock and a high speed DLL to generate a pair of 204.8MHz
> clocks with a 180 degree delay between them. The system uses two
> counters with each counter being clocked 180 degrees out of phase with
> the other at 204.8 MHz. The resulting counts are then added to get an
> effective 409.6MHz clock resolution.
>
> The code below is a fragment of the full system with only the DLL
> related signals being shown. Does anyone see any problems with the code
> implementation, etc?
>
>
>
> u2: clkdllhf PORT MAP (
> clkin=>buf_clk2x,
> clkfb=>clk0_out,
> rst=>d_locked_not,
> clk0=>clk0,
> clk180=>clk180,
> locked=>dll_running
> );
>
> fast_lock<=dll_running;
>
> d_locked_not<=not(d_locked);
>
> u1: clkdll PORT MAP (
> clkin=>buf_clk,
> clkfb=>buf_clk2x,
> rst=>zero,
> clk0=>open,
> clk180=>open,
> clk2x=> clk2x,
> locked=>locked
> );
>
> slow_lock<=locked;
>
> u4: ibufg port map(
> i => clk,
> o => buf_clk
> );
>
> u3: bufg PORT MAP(
> i =>clk2x,
> o =>buf_clk2x
> );
>
> u5: bufg PORT MAP(
> i =>clk0,
> o =>clk0_out
> );
>
> u6: bufg PORT MAP(
> i =>clk180,
> o =>clk180_out
> );
>
> u7: SRL16 port map(
> D => locked,
> CLK => buf_clk2x,
> A0 => one,
> A1 => one,
> A2 => one,
> A3 => one,
> Q => d_locked
> );
>
> u8: SRL16 port map(
> D => reset_counter,
> CLK => buf_clk2x,
> A0 => one,
> A1 => one,
> A2 => zero,
> A3 => zero,
> Q => reset_counter_delayed
> );
>
Article: 54266You can get Synplify Pro synthesis for your class needs for a very low price. HDL Analyst is a great visualization tool for teaching the connection between RTL code and the produced logic. http://www.synplicity.com/training/university/index.html XC4000 parts are supported. - Ken Scott wrote: > Yeah I am sort of considering doing that, it's just learning and figuring > out what software I'm going to use to program the design and to deign the > ALU. All I'm planning on doing is having 2 four bit numbers as inputs and > the output will be displayed on a seven segment display or something. It is > meant to be a simple exersise in one of my courses to introduce us to > FPGA's. > > >>What exactly are your I/O requirements. Could you get a PQFP socket, >>wirewrap, and a Spartain part from digikey? >> >>-- >>Nicholas C. Weaver nweaver@cs.berkeley.edu >> > >Article: 54267
John Larkin <John.Larkin> writes: > why not just use a linear LDO (LM1117 or whatever) from +5 or +3.3? > That's a lot cheaper and simpler. Because there's not much 5V available. I'm not sure about the LM1117, but the MAX1818 that Xilinx recommends (due to its current limiting behavior) seems to be made of 100% unobtanium.Article: 54268
rickman <spamgoeshere4@yahoo.com> writes:
> I was reading the thread on the possibly new Spartan-3 parts
Possibly? Definitely. So new, in fact, that they haven't yet been
announced, other than in the 5.2i release notes.
> The Webpack does not have a chip editor. Anyone know of any other
> source of info on these parts?
I expect you'd get the editor in the free 60-day trial version of 5.2i:
http://www.xilinx.com/ise_eval/
> Should they be considered to be way in
> the future rather than something to be considered in a near future
> design?
I imagine that Xilinx has learned from past mistakes, but when they
announced the Spartan 2 family, it took about a year before parts were
available to anyone but the big customers, IIRC.
Also note that generally not all of the sizes of a new family become
available at the same time. Perhaps two or three sizes would ship
first, with more trickling out later.
> I would love to get a cheap part that does not have the startup
> current problem!
Wouldn't we all.
Article: 54269
Even if you do happen to be using a device supported by 1.5, the speed files have
been superceded several times over, some for the better, some for the worse. At
this point, I'd take any timing results from that old version with a grain of
salt. As I recall, it is the SRL16's and the BRAM that got slower since that
release, but my memory ain't what it once was either.
Spam Hater wrote:
> In addition to what the others have said, there is one more problem.
>
> Xilinx will NOT issue you a new run-time license. Period.
>
> So it's 100% useless.
>
> (Download webpack)
>
> On Sun, 6 Apr 2003 11:19:14 -0700, "Just Me" <phony@nowhere.cc> wrote:
>
> >I have the opportunity to buy a full-blown Xilinx Foundation version 1.5 for
> >$20 or so. My employer is willing to purchase the latest version of
> >Foundation for $2500, but every dollar counts so I don't want to do it
> >unnecessarily. Would it be a poor investment of my time to mess with the
> >older software, i.e. is the newer version so much better and more
> >feature-packed that it's not worth trying to save money in this way? I think
> >the Xilinx FPGA devices I'd be using would be covered by the old software.
> >One thing I'm not sure about is the DDS core they offer with Foundation. I'd
> >like to use it, but I don't know whether it was in 1.5.
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 54270Hi folks, I'm looking into getting a laptop primarily for admin stuff, but it would be nice to be able to use it for demos etc, which means using the Xilinx parallel cable to program my boards etc. Most miniature laptops these days don't have an LPT port, so I'm wondering if anybody knows whether you can use after-market USB->LPT adaptors with the Xilinx parallel cable and programming software? Anybody had success in this regard? Can you tell me which USB->LPT adaptor you used? Thanks, JohnArticle: 54271
Is there some type of standard test other than hobby projects that could serve to test for example circuit designs ability or sales/marketing skill prior to taking a job? I feel I could do both equally well provided I get paid enough to try hard. ( I suppose the experienced specialists bored with work probably have the same attitude -dont care what I do provided I regularly get paid enough?)Article: 54272
Hello Sirs/Friends Any idea about Prefetching???? for example Master initiate a read (burst read ,prefetech buffer 4 double word) at location 30000000 ,so data from 30000000 to 30000010 is fetched ? IS this true ? next address is whether 30000004 or 30000014? If it is 30000004 then data from 3000004 to 30000014 is fetched?Is this true? IF target side prefetch is disabled?what will happen? only one data is passed to the initiator side?Is this true? why bus parking done only for AD,C/BE and PAR?why other signal donot need parking what is use of signal being of sustained tristate type? waiting for reply praveenArticle: 54273
"John Williams" <jwilliams@itee.uq.edu.au> wrote in message news:b6qmgt$jfn$1@bunyip.cc.uq.edu.au... > Hi folks, > > I'm looking into getting a laptop primarily for admin stuff, but it > would be nice to be able to use it for demos etc, which means using the > Xilinx parallel cable to program my boards etc. > > Most miniature laptops these days don't have an LPT port, so I'm > wondering if anybody knows whether you can use after-market USB->LPT > adaptors with the Xilinx parallel cable and programming software? > > Anybody had success in this regard? Can you tell me which USB->LPT > adaptor you used? Haven't tried them, but I *think* they will work. They should just look like any other LPT port. Slightly offtopic, but I'd like a laptop marketed specifically to EE's: * Hot-swappable digital I/O blocks, optoisolated * Support for every major interface ever made * Digital oscilloscope * DMM * Function generator * Frequency counter * Spectrum analyzer * EPROM/MCU/CPLD programming socket * (+-)12/5/3.3 power supply when on wall power * Swappable DSP/FPGA module with access to PCI bus and memory * Integrated camera/scanner * Analog part parameterizer: snap in a component and the parameters are inserted into PSPICE * Part simulator: within limits simulates behavior of a component in-circuit Ahh...we can only wish. Of course this "laptop" would be nearly two feet square and weigh 86 pounds. -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 54274
Hal Murray <hmurray@suespammers.org> wrote: :>This works as long as funding continues to increase. My point :>(perhaps poorly stated) is that funding can not continue to increase, :>as the world market for electronics becomes saturated. ... : Is the cost of fab lines following Moore's law? I suspect so, but Please, let's call it "Moore's observation". It's not a law! Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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