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My two cents ;-) ... matt@ettus.com (Matt Ettus) wrote in message news:<e8fd79ea.0304031738.3c3bb265@posting.google.com>... > Thanks to everyone for the responses. We've decided for now to go > with the Cyclone part, EP1C6, since it has more pins in the PQFP > package. > > It seems to me that the non-BGA packages seem to be heavily > deemphasized. I think that this is bad for many reasons: > > - protos harder to make and cost more 1. Consider _buying_ a prototype board, Parallax (makers of the Basic Stamp) are now offering a Stratix board for $395. 2. There are socket solutions available (Emulation Technology I think) but I haven't looked into it price-wise. 3. If you work with contract mfgrs, I have found them willing to put BGAs only onto first article boards for a nominal charge. > - must use more board layers > - rework difficult if not impossible You can go the socket/adapter route for a cost. > - probing is much harder I have had very good success with a built-in logic analyzer (Xilinx ChipScope, haven't used Altera SignalTap yet). And I would say that the BGA via is about as accessible as a PQFP pin, on the other hand I will concede that a test clip makes a lot of difference. > I hope that large PQFPs will be around for many years to come. > > Matt -rajeev-Article: 54201
I'm using the XL mainly because it is convient and I have ax Xess development board that is designed for it....but I could use the Spartan I suppose. > > Why specifically the XL? Could you use a Spartain 1? > -- > Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 54202
In article <v8rmpv5vivi8b8@corp.supernews.com>, Scott <scott_howes@hotmail.com> wrote: >I'm using the XL mainly because it is convient and I have ax Xess >development board that is designed for it....but I could use the Spartan I >suppose. Life will be SO much happier for you if you use a currently supported part. What exactly is your project trying to do? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 54203
Praveen See if you can get hold of the book "PCI System Architecture" by Tom Shanley and Don Anderson. -rajeev- ------------------ praveenkumar1979@rediffmail.com (praveen) wrote in message news:<ff8a3afb.0304030426.5543d6d5@posting.google.com>... > Hello Sirs/Friends > I have some doubt in PCI specification > 1.why bus parking done only for AD,C/BE and PAR?why other signal donot > need parking <...>Article: 54204
Given enough clock cycles you could do a 256 point FFT in any FPGA that
has enough memory to hold 256 complex points. For 16 bits I and Q, an
XC2S15 could do a 256 point FFT, and if you crank up the clock it would
still return a reasonable performance.
vt313@comsys.ntu-kpi.kiev.ua wrote:
> Aldec provides FFT core for 256 points which needs
> 500 CLB slices + Memory.
> If your Spartan has enough memory resources-
> you would do.
>
> I have similar a core as well.
> A.Sergyienko
>
> Jerzy wrote:
> >
> > Hi
> > I'd like to know if is there any possibility to make usable IPCore
> > from Xilinx FFT 256pt, for Spartan?
> > Spartan IIe has similiar resources as virtex.
> > Or could You give me advice where I can find core this class?
> >
> > Greatings
> >
> > Jerzy Gbur
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 54205It is a fiarly simple little project. It is just designing and implementing a four bit Arithmetic Logic Unit using an FPGA. So what it will do is take in a four bit number and add, subtract multiply etc, and produce the output. But since I am fairly new in the world of FPGA's I thought it best to use parts and programs that I have read about in text books (in other words outdated stuff :). But now I see that I may have to resort to newer versions and parts maybe. Scott "Nicholas C. Weaver" <nweaver@ribbit.CS.Berkeley.EDU> wrote in message news:b6km4i$1iur$1@agate.berkeley.edu... > In article <v8rmpv5vivi8b8@corp.supernews.com>, > Scott <scott_howes@hotmail.com> wrote: > >I'm using the XL mainly because it is convient and I have ax Xess > >development board that is designed for it....but I could use the Spartan I > >suppose. > > Life will be SO much happier for you if you use a currently supported > part. > > What exactly is your project trying to do? > -- > Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 54206
In article <v8rogj4ej6gf4b@corp.supernews.com>, Scott <scott_howes@hotmail.com> wrote: >It is a fiarly simple little project. It is just designing and implementing >a four bit Arithmetic Logic Unit using an FPGA. So what it will do is take >in a four bit number and add, subtract multiply etc, and produce the output. >But since I am fairly new in the world of FPGA's I thought it best to use >parts and programs that I have read about in text books (in other words >outdated stuff :). But now I see that I may have to resort to newer >versions and parts maybe. The Spartan I is basically teh same as the old 4000 series, in 3.3V. The Spartan II/Virtex1 family (and E variants) are far more advanced, with embedded memories and other features which you could always ignore. Also, does it have to work outside simulation and static timing analysis? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 54207
Yeah, it has to work outside of simulation analysis, that is why it is convient to use XC4000 because I have that particular chip already. > > The Spartan I is basically teh same as the old 4000 series, in 3.3V. > The Spartan II/Virtex1 family (and E variants) are far more advanced, > with embedded memories and other features which you could always > ignore. > > Also, does it have to work outside simulation and static timing > analysis? > -- > Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 54208
In article <v8rpq1cgni6f6c@corp.supernews.com>, Scott <scott_howes@hotmail.com> wrote: >Yeah, it has to work outside of simulation analysis, that is why it is >convient to use XC4000 because I have that particular chip already. What exactly are your I/O requirements. Could you get a PQFP socket, wirewrap, and a Spartain part from digikey? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 54209
Yeah I am sort of considering doing that, it's just learning and figuring out what software I'm going to use to program the design and to deign the ALU. All I'm planning on doing is having 2 four bit numbers as inputs and the output will be displayed on a seven segment display or something. It is meant to be a simple exersise in one of my courses to introduce us to FPGA's. > What exactly are your I/O requirements. Could you get a PQFP socket, > wirewrap, and a Spartain part from digikey? > > -- > Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 54210
Wow, why all this poison ? There can be no debate about the well-known fact that the number of new ASIC designs is decreasing, while FPGA starts are increasing. And this has to do with the very high NRE cost for state-of-the-art ASICs. $30,000 per mask, and 30 masks for a state-of-the-art process. Including extreme levels of verification, this ends up as several million dollars. Plus risk, plus inflexibility... So if you want the highest ASIC performance and the lowest chip price, you have to pay a lot of money up-front, even after you have completed your design and done all the verification. We at Xilinx know that, because that's what we have to do and pay to get our FPGAs into production. Remember, from our point of you, we make custom chips ! Our advantage is that we can amortize the NRE over millions of devices. The trend is clear, and the wind is in favor of the FPGA. That does not mean that ASICs will die immediately. But the argument in favor of ASICs gets more and more difficult to make. ASICs are for extremely high volume, or extreme speed, or extremely low power. More and more of the other designs will be implemented in FPGAs, which are getting bigger, faster, and cheaper every day. We obviously like this trend, others may dislike it, but let's not insult each other. Facts are facts. Peter Alfke, Xilinx Applications =================== Ljubisa Bajic wrote: > > I absolutely agree with Rudi. > As someone who has done high-speed board design, fpga based logic design > and full custom ic design, I must say that most of what you wrote in the above > article strikes me as bordering on nonsense. > I have enjoyed your tutorials on signal integrity and find most > of your postings in this group very usefull, so I am amazed at how > willing you are to abandon reason and truth in favour of Xilinx marketing. > I hope they pay you REALLY well ... > > Ljubisa Bajic, > VLSI Design Engineer, > Oak Technology, Teralogic Group > > --------------My opinions do not reflect those of my employer.------------- > > Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3E887532.31FE90B4@xilinx.com>... > > Nicholas, > > > > The original question was "why would anyone spend $4,000." > > > > Good question. No one does. Well almost no one. I suppose the 'monster' > > FPGAs (like the 2V8000, or the 2VP100) will always command a premium until > > they, too, are mainstream - just a question of demand). > > > > 1M+ gates up until now has certainly been much less than $4,000 (even in small > > quantities). > > > > Now we are talking about even less money for 1M+ gates in 90 nm. > > > > ASICs are all but dead except for those really big jobs that can afford the > > $80M++ price tag to develop them. Or those jobs where low current is required > > (ie cell-phones). > > > > Even televisions don't sell enough to afford some of the new ASIC pricetags. > > Think about it. An "appliance" doesn't sell in large enough volume to have > > its own ASIC. > > > > The recent EETimes article on IP at these geometries was especially telling. > > Integration of IP at 130 nm and 90nm is a hightmare......etc. etc. etc. The > > 80M$ figure above was from that article. > > > > So 'cheap' ASICs are stuck at 180nm (and above). But with 90nm FPGAs we are > > three or more techology steps ahead (.15, .13, .09), and that makes us a > > better deal. > > > > Austin > > > > "Nicholas C. Weaver" wrote: > > > > > In article <3E886139.96955371@xilinx.com>, > > > Austin Lesea <Austin.Lesea@xilinx.com> wrote: > > > >Really? > > > > > > > >Have just annouced 90nm shipped samples. > > > > > > > >http://biz.yahoo.com/prnews/030331/sfm087_1.html > > > > > > > >so I would suspect that you might want to get in touch with another > > > >distributor.... > > > > > > > >Might find 1+ million gates for a whole lot less.... > > > > > > Thats "250,000 quantities at (the end of?) 2004". :) > > > > > > -- > > > Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 54212
Austin Lesea wrote > I think you can make a good educated guess at what the core voltage is > for 90 nm, however. Just wondering - is 0.6V the absolute minimum core voltage? I should remember the physics, but ...Article: 54213
There are two techniques here. DA can be implemented in RTL HDLs by describing
the LUT as a ROM containing the sums of each of the 16 possible sums of the 4
coefficients multiplied by one bit. The easiest way to do this is use a
function to assign the ROM values using 4 coefficients as the argument. This
can be done strictly in generic RTL and is portable. Our IP does a structural
instantiation of primitives in order to also assign placement, whch saves us
lots of time (it also lets us directly replace the LUTs with SRL16s). The LUT
values are loaded using a function that reads coefficients and generates the LUT
values on the fly.
The SRL16 as a reprogrammable LUT is a bit more problematic for RTL
implementation, as many of the synthesis tools either don't handle it or are
fussy about how it is handled. An inferred SRL16 also can't be assigned an
arbitrary initial value, it has to start with all 0's, which is no good if you
want the filter to start up without having to load it right off. You can
describe the SRL16 behavior as a shift register and a 16:1 mux, which is
synthesizable, but good luck getting the tools to infer an SRL16. As I
mentioned before, this feature is unique to Xilinx. The Xilinx Unisim library
is consistent across the Xilinx families, so there is no real harm in
instantiating the SRL16 primitives. If you want to use this feature, you are
locked into xilinx anyway...putting the same function into an FPGA without the
SRL16 will take up 16 D-flip-flops plus 11 LUTs for each SRL16 instance. That
is hardly an efficient structure.
The fact is that if you want to get an efficient use of the FPGA, no matter what
brand you choose, you need to tailor your design at the architectural level to
take advantage of features of the selected device. This goes way beyond simple
RTL optimizations. If you insist on absolute code portability, you also need to
be willing to pay the price. In the case of reprogrammable FIR filters, DA
filters can get very expensive for reprogrammability without the SRL16
capability. Even with small distributed RAMs, you wind up having to insert
muxes on each address line, which alone gives you a 5x growth for 4 LUTs.
Arash Salarian wrote:
> Thanks for your reply Ray and also Nicholas,
>
> Yet, I have some few questions remaining. How should we use this technique
> in practice, in HDLs? Take VHDL for example, how whe should write the code?
> And how to simulate it? From what Ray said I understand that there may be a
> way to write DA+SLR16 without explicit usage of Xilinx primitives. Obviously
> it should be like writing a code that a good synthesizer would ultimately
> optimize down to a single Xilinx LUT. So, now the question will be how to
> code such a LUT in a VHDL model that would feature all what we need (SLR16
> mode, multiplexer in the output, implementation in a single xilinx LUT) and
> what synthesizer would be able to synthesize it correctly? And what about
> the simulation: can we use the same model for RTL simulations? And how much
> would be the code portable to different synthesize/simulation/verification
> tools? What will happen if we use the code for a FPGA family that do not
> have this feature? Would it function correctly (now obviously with penalties
> for speed/space)?
>
> Best Regards
> Arash
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3E8CAA0D.DC4695B4@andraka.com...
> > For a discussion on Distributed Arithmetic (DA), see the DA tutorial page
> on my
> > website. It is basically a method to take advantage of the LUT structure
> of an
> > FPGA to get more multiplies per unit area. It is traditionally bit
> serial, but
> > can also be parallelized to compute as many bits in parallel as you are
> willing
> > to pay for in area, all the way up to a full parallel implementation. It
> is
> > basically a rearrangement of the partial products in a sum of products to
> reduce
> > the hardwre.
> >
> > SRL16 mode is a Xilinx exclusive feature that allows the LUT to be used as
> an
> > addressable shift register. It is essentially a 16 bit serial-in parallel
> out
> > shift register with a 16:1 selector to select one of the 16 shift register
> taps
> > as the output. When the data is not being shifted in, it behaves exactly
> like a
> > LUT so that the data currently inside is addressed with the 4 LUT inputs.
> >
> > The SRL16s are useful for delay queues, in which case the address is
> generally
> > fixed and data is shifted in on every clock. For DA applications,
> normally one
> > uses LUTs containing all the possible sums of 4 constants times the 4 1
> bit
> > inputs (see my website). A drawback to DA in the traditional sense is
> that the
> > coefficients are fixed since they are set at compile time. By replacing
> them
> > with SRL16's you can provide an ability to reload the coefficients without
> > having to reconfigure the FPGA. It requires some sort of loader circuit
> to
> > obtain the new data from somewhere (a memory or from some host processor),
> as
> > well as something to compute the LUT contents, which have 16 entries for
> each
> > set of four coefficients (this can be precomputed or computed inside the
> FPGA).
> > Support for SRL16's in other than a simple delay queue is somewhat sparse
> in the
> > synthesis tools, so we just instantiate the SRL16's. Instantiation has an
> added
> > advantage of letting you do the floorplanning in the code. The SRL16 is
> unique
> > to Xilinx, so even if the code were written without primitives, it
> wouldn't be
> > very portable. SRL16s can also be used for reorder queues by modulating
> the
> > address lines while data is shifting in.
> >
> > Arash Salarian wrote:
> >
> > > Hi,
> > >
> > > I've seen in many posts, ppl are talking about using distributed
> arithmetics
> > > and SLR16 in xilinx devices; mostly in Ray posts. I tried to find
> something
> > > to read about it using google but I had no chance. So basically I have
> only
> > > some guesses in my mind but no documents in hand. I've only a limited
> > > background about Xlinx devices and all I know is that the LUTs can be
> put in
> > > a SLR16 mode that would let us feed in a 16 bit value and then again by
> > > changing the mode back to normal, we'll have a LUT based on this value.
> > > So, what is this DA+SLR16 all about? Where and when should (or
> shouldn't) we
> > > use this technique? Where the LUTs' content come from? How should we
> store
> > > them (in BlockRAM?) How it's done in real practice, i.e. how we can code
> it
> > > in HDLs? Can we write a module in a HDL using this technique and yet
> > > preserve the portability (to other devices without such a feature, like
> > > Altera's)? How about simulations?
> > >
> > > Best Regards
> > > Arash
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 54214
Hi all:
We designed a PCB(4 layers) for Altera EP20K400EBC-652-1X and found
that it ran O.K. in some "tiny" projects but failed in the big project
. In the big project(80% LEs used), the circuit ran O.K. for a few
seconds and then failed. The result was getting worse and worse. I am
sure IC is O.K. because it runs O.K. in another PCB made by GALAXYFAREAST.
I also compiled a tiny project to check every IO on the PCB and it ran
as expected. Any hints will be much appreciated.
Thanks in advance
Note: EP20K400E is configured by JTAG or PS modes(PC -> IC)
Article: 54215Tim, No, one can make zero threshold devices. Now they are pretty leaky, but they are also fast.... Just when everyone says, "CMOS is dead..." we solve the big issue that was hanging over us, and CMOS is alive again. How many times can it continue to do this? If cats have nine lives, CMOS may have 9 times 9..... The finFET, the vertical post FET, metal gate, hi-k gate, atomic layer gates, salicided taps, deep V-groove isolation trenches, stressed silicon, SOI, ...it just gets more and more exotic. Sure, looking out there today, 65nm and below looks impossible, grim, difficult, etc. But that is what everyone said about 0.25u when I first joined Xilinx! I was in a meeting where the fab said "we have 19 steps in the process that we have no idea how to do them yet..." I asked someone, "does that worry you?" They answered, "19? Why that is an all time record. Record Low. No problem." Will we someday see the end of CMOS as we know it? I would argue that today's CMOS doesn't look at all like it did 10 years ago, maybe even 5 years ago. It keeps coming back to life with new features, rules, devices, processes, etc..... Austin Tim wrote: > Austin Lesea wrote > > > I think you can make a good educated guess at what the core voltage is > > for 90 nm, however. > > Just wondering - is 0.6V the absolute minimum core > voltage? I should remember the physics, but ...Article: 54216
Jerry, You don't need to give yourself that much performance margin. While the Cyclone timing models are still preliminary, core timing tends to be pretty stable. It's the PLL and IO timing that tends to gate finality of the timing model, as these structures are electrically more complex (analog) and thus are more dependent on silicon characterization and hence take longer to finalize. When providing preliminary timing models, our goal is to be as close to final device performance as possible, but we try to err on the side of being pessisimistic -- we'd rather give our users a pleasant surprise! BTW, which version of Quartus did you use, and which speed grade, for that 63 Mhz result? Regards, Paul Leventis Altera Corp. "jerry1111" <jerry1111@wp.pl> wrote in message news:b6jn8h$sbc$1@nemesis.news.tpi.pl... > > First question is whether either of the matrices is a constant, or if not if it is > > They are changing, because I want to use fpga as 'matrix co-processor'. I have to > make 9 matrix multiplies and some addition in one algorithm pass, so I'll include > some logic on higher address bits of matrix-ram. There are operations like A*B*C and > A*B*A(transposed) so this logic will prevent copying matrix data between ram blocks. > I think such copy-preventing will save me quite a lot of time. > Nios will be using off-chip ram mostly, in-chip ram will be used generally for math data > only (to speed-up things). Quartus shows that Nios will run for 63MHz in EP1C6, but Cyclones > are quite new - I think good idea is to give at least 20% margin for fmax. Everything shows > that I have >2000 LCes spare for matrices and 2 PI regulators (PI is small problem...), > so it should fit into chip. > > I'll post results to this newsgroup, and (if I had enough time) maybe some 'opencore' code > will be made? Who knows :-) > > > -- > jerry > > "The day Microsoft makes something that doesn't suck is probably > the day they start making vacuum cleaners." - Ernst Jan Plugge > >Article: 54217
On Fri, 04 Apr 2003 16:17:06 -0800, Austin Lesea wrote:
>Just when everyone says, "CMOS is dead..." we solve the big issue that was
>hanging over us, and CMOS is alive again. [chop]
>Sure, looking out there today, 65nm and below looks impossible, grim,
>difficult, etc. But that is what everyone said about 0.25u when I first
>joined Xilinx! [chop]
>Will we someday see the end of CMOS as we know it? I would argue that
>today's CMOS doesn't look at all like it did 10 years ago, maybe even 5
>years ago. It keeps coming back to life with new features, rules, devices,
>processes, etc.....
I have said since 2000 that Moore's law ends in 2005,
not for technical reasons, but for economic ones. In concrete
terms, we are now close enough to that threshold that I predict
the industry will burn so much money trying to make 65 nm fab
lines work, and the market for the resulting chips will be weak
enough, that those fabs will never turn a profit. The industry
as a whole will therefore not be financially willing or able to
make a serious attempt at any following generations, or if they
try, it will be at a _much_ slower pace than we are used to.
- Larry
Article: 54218I didn't mean to sound like the flu coming around.. Just pointing out that this is coming around and may cause a problem to a concept I am working on ... no disrespect intended. So please don't shot the messenger .. and I didn't junk the Spartan if you might have noticed was just a coment .. It is just easier to design around something when its know about. I much prefer Xilinx and the start-up 'warning' in the data sheet to having to harass apps engineers who may or may not know what you are talking about especially if the app note doesn't seem to work properly. Simon "Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message news:3E8DA9B2.E3F95A63@xilinx.com... > Simon, > > Like a bad cold? As you know, we designed out the power up issues in VII and > subsequent products, and improved it > substantially in 300mm SIIE. > > One caution, and I will raise it again: we have built 'zillions of Spartan II, > IIE now (and IIE is all on 300 mm fab now). > > What that means is that we KNOW what it does, and we KNOW the abs max, and abs > min numbers over PVT. > > Clever circuits that don't have access to all process corner material, and are > verified over all temperatures and voltages > aren't worth the paper (or html) they are on (in). > > You base your PDS (power distribution system) design on a few samples (from the > same wafer, no doubt) and you will be very unhappy when you get surprised by > what the next lot does to you....when it gets cold....or hot....or ramps on > 'funny'....or..... > > Austin > > Simon wrote: > > > This is an interesting discussion.. seems the Xilinx Spartan 2 current has > > flowed to Altera. > > I've also got a board with a space constraint.. I'ts still in the discussion > > phase so I havn't got a total fix yet.. but Cyclone or Spartan is the > > choice.. Cyclone because theres a rummor it can program its own config flash > > :-) > > > > But I have a question .. mainly for Martin because of the great work he did > > in the PSU evalutaion. (thanks for that by the way). > > > > When looking at the app note and then at Linear Tec's web site I noticed the > > LTC3251, 500mA switched cap. > > It has a peak current of 800mA so not much more but the current is delivered > > from a low ESR cap. > > > > How does that concept grab you ? > > Do you think it might be better / worse / same ? > > > > Arrow think its about US$2.01 > > > > Simon > > > > "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message > > news:ujYia.147215$Xa3.1268939@news.chello.at... > > > > I would like to thank all for their good ideas and help. > > > > > > > > I've tested some of the suggested ideas and wrote a little summary with > > > some > > > > osci plots. You can find them at: > > > > http://www.jopdesign.com/cyclone/powerup.jsp > > > > > > > > > > I've added plots for the darlington regulator circuit. > > > > > > Martin Schoeberl > > > > > > >Article: 54219
We once put down PBGA's using a toaster over.. but only to pre-heat the boards.. and we did calibrate the dial slightly too :-) The chip was soldered using a pace hot air PGA re-work tool and a lot of patients Another thought.. for prototypes.. if you don't consider removal a high priority conductive glues with a stencil ? never tried it but is worth a consideration Simon "Peter Wallace" <pcw@karpy.com> wrote in message news:pan.2003.04.04.15.24.49.392069.9156@karpy.com... > On Thu, 03 Apr 2003 20:22:22 -0800, Nicholas C. Weaver wrote: > > > In article <e8fd79ea.0304031738.3c3bb265@posting.google.com>, Matt Ettus > > <matt@ettus.com> wrote: > >>Thanks to everyone for the responses. We've decided for now to go with > >>the Cyclone part, EP1C6, since it has more pins in the PQFP package. > >> > >>It seems to me that the non-BGA packages seem to be heavily > >>deemphasized. I think that this is bad for many reasons: > >> > >>- protos harder to make and cost more - must use more board layers - > >>rework difficult if not impossible > >>- probing is much harder > >> > >>I hope that large PQFPs will be around for many years to come. > > > > Don't count on it by much. Pin bandwidth is a precious comodity, and a > > PQFP-style package's bandwidth is a function of SQRT of board footprint, > > while BGAs are linear in the size. > > > > Do you know if anyone's succeeded in Toaster-oven-soldering of BGA > > packages? > > Dont know about toaster ovens but I've done 516 pin ones with a Granger > hot air gun, No solder paste needed as the balls provide enough solder. > you do need lots (and lots) of flux and some scheme of keeping the BGA > aligned as you heat it (from behind) My guess is that toaster oven > scheme would work if done in a similar fashion... > > PCWArticle: 54220
"slamwu" <slamwu@alumninet.nctu.edu.tw> wrote in message news:b6l5rd$2eg1$1@netnews.NCTU.edu.tw... > Hi all: > We designed a PCB(4 layers) for Altera EP20K400EBC-652-1X and found > that it ran O.K. in some "tiny" projects but failed in the big project > . In the big project(80% LEs used), the circuit ran O.K. for a few > seconds and then failed. The result was getting worse and worse. I am > sure IC is O.K. because it runs O.K. in another PCB made by GALAXYFAREAST. > I also compiled a tiny project to check every IO on the PCB and it ran > as expected. Any hints will be much appreciated. > Thanks in advance > Note: EP20K400E is configured by JTAG or PS modes(PC -> IC) Check to make sure you have enough power to the board, and enough capacitors very close to the FPGA. The more switching you do, the more transient loads you get.... -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 54221
Let's talk again on 12-31-2005. The stories about the death of CMOS are "slightly exaggerated". Those of us who have been around a few years remember the stories about the wavelength of light limiting us to one micron, or 0.5 micron, or 0.25, or... In 1960 I listened to a renowned physicist "proving" that integrating multiple transistors was economically impossible, the defect density would kill it. Now we can put 600 Million transistors on a chip since defect densities are below 1 per square centimeter. Given a challenge, engineers always find a way to advance the technology. Maybe we will go optical, or molecular, or organic, or all of the above, or something totally different. I am sure that there will be progress in the same general direction, but of course different. It's never a straight line. Computers are still crude, telephones are still unfriendly, cars are still dumb, the human brain is still unchallenged ( except for playing chess). Peter Alfke ================================= Larry Doolittle wrote: > > On Fri, 04 Apr 2003 16:17:06 -0800, Austin Lesea wrote: > >Just when everyone says, "CMOS is dead..." we solve the big issue that was > >hanging over us, and CMOS is alive again. [chop] > >Sure, looking out there today, 65nm and below looks impossible, grim, > >difficult, etc. But that is what everyone said about 0.25u when I first > >joined Xilinx! [chop] > >Will we someday see the end of CMOS as we know it? I would argue that > >today's CMOS doesn't look at all like it did 10 years ago, maybe even 5 > >years ago. It keeps coming back to life with new features, rules, devices, > >processes, etc..... > > I have said since 2000 that Moore's law ends in 2005, > not for technical reasons, but for economic ones. In concrete > terms, we are now close enough to that threshold that I predict > the industry will burn so much money trying to make 65 nm fab > lines work, and the market for the resulting chips will be weak > enough, that those fabs will never turn a profit. The industry > as a whole will therefore not be financially willing or able to > make a serious attempt at any following generations, or if they > try, it will be at a _much_ slower pace than we are used to. > > - LarryArticle: 54222
On Fri, 04 Apr 2003 17:48:55 -0800, Peter Alfke wrote:
>Let's talk again on 12-31-2005.
I'd be glad to. ;-)
>Given a challenge, engineers always find a way to advance the
>technology. Maybe we will go optical, or molecular, or organic, or all
>of the above, or something totally different.
This works as long as funding continues to increase. My point
(perhaps poorly stated) is that funding can not continue to increase,
as the world market for electronics becomes saturated. Europeans,
Japanese, and Americans probably are close to their limit for how
many dollars per year they spend on gadgets. After India and the
Pacific Rim get there too (around 2005), our R&D budgets will
necessarily flatten out, and we won't be able to afford the next
big push to smaller geometries.
- Larry
Article: 54223Hi group, I inherited a design which was simulated using Viewsim commands (I believe it is Foundation 1.5/3.1?). I am converting the "testbench" into full VHDL. At first, I tried to convert to Modelsim do file, but the force statement is just too much. So I am guessing what those Viewsim commands like wfm, smode, bc etc means! Any help is appreciated. Regards, LCArticle: 54224
"Larry Doolittle" <ldoolitt@recycle.lbl.gov> wrote in message news:slrnb8sf90.ddi.ldoolitt@recycle.lbl.gov... > On Fri, 04 Apr 2003 17:48:55 -0800, Peter Alfke wrote: > >Let's talk again on 12-31-2005. > > I'd be glad to. ;-) > > >Given a challenge, engineers always find a way to advance the > >technology. Maybe we will go optical, or molecular, or organic, or all > >of the above, or something totally different. > > This works as long as funding continues to increase. My point > (perhaps poorly stated) is that funding can not continue to increase, > as the world market for electronics becomes saturated. Europeans, > Japanese, and Americans probably are close to their limit for how > many dollars per year they spend on gadgets. After India and the > Pacific Rim get there too (around 2005), our R&D budgets will > necessarily flatten out, and we won't be able to afford the next > big push to smaller geometries. > > - Larry Isn't that what Chinas for ? Simon
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