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Messages from 54425

Article: 54425
Subject: Re: Webpack 5.2 and Win98se
From: Duane Clark <junkmail@junkmail.com>
Date: Thu, 10 Apr 2003 12:26:52 -0700
Links: << >>  << T >>  << A >>
rickman wrote:
> 
> If you read the requirements for any of the current Xilinx development
> products you will find that they only support two versions of Windows,
> 2000 and XP.  This is not a bug and I suspect the only thing about it
> that is not permanent is Win2000 support.  My guess is that they will
> drop that in the next release or two.  At that point I expect I will use
> something else for FPGA development...

Hmm, maybe the long rumored native Linux version will show up before then...

-- 
My real email is akamail.com@dclark (or something like that).


Article: 54426
Subject: Re: Webpack 5.2 and Win98se
From: Steve Lass <lass@xilinx.com>
Date: Thu, 10 Apr 2003 14:16:23 -0600
Links: << >>  << T >>  << A >>
Native Linux (7.3 and 8.0) and Windows2000 will both be supported in our
next major release, which is 6.1i in September.

Duane Clark wrote:

> rickman wrote:
>
>>
>> If you read the requirements for any of the current Xilinx development
>> products you will find that they only support two versions of Windows,
>> 2000 and XP.  This is not a bug and I suspect the only thing about it
>> that is not permanent is Win2000 support.  My guess is that they will
>> drop that in the next release or two.  At that point I expect I will use
>> something else for FPGA development...
>
>
> Hmm, maybe the long rumored native Linux version will show up before 
> then...
>


Article: 54427
Subject: Re: Really long vectors in VHDL
From: Ken McElvain <ken@synplicity.com>
Date: Thu, 10 Apr 2003 20:47:06 GMT
Links: << >>  << T >>  << A >>
With a current version of Synplify generics on black box instantiations
are passed into the edif so you don't need to do the old trick of
generics for simulation and attributes for edif.

Knowing how things work in the compiler I would think that using a 2-d
array for the table would be much more memory efficient.

There has also been a lot of work over the last couple of releases on
decreasing the memory used for large constant tables.  I would recommend
trying the 7.3 beta.   If that doesn't work for you then let me know.

- Ken


Allan Herriman wrote:

> On 10 Apr 2003 09:18:38 -0700, emil.isaakian@l-3com.com (Emil
> Isaakian) wrote:
> 
> 
>>Allan Herriman <allan_herriman.hates.spam@agilent.com> wrote in message news:<gn2q8v4t7vjqjaha7bgnrahikur6bq6fqs@4ax.com>...
>>
>>>On Thu, 03 Apr 2003 09:57:06 -0800, Mike Treseler <tres@fluke.com>
>>>wrote:
>>>
>>>
>>>>Allan Herriman wrote:
>>>>
>>>>>Hi,
>>>>>
>>>>>Does anyone have experience with VHDL tool support for bit vectors
>>>>>(or vectors of other types) that have lots of elements?
>>>>>
>>>>>I'm thinking of using one for a generic or a constant (not a signal)
>>>>>to hold the initialisation value for a Xilinx block ram (18432 bits).
>>>>>
>>>>>I'm interested in both simulation and synthesis.
>>>>>
>>>>
>>>>Initialization for a block RAM occurs when the binary
>>>>image is loaded into into the device. The only way to
>>>>to control this from VHDL source is with device
>>>>specific instances and attributes or by inferring
>>>>a ROM by declaring a constant array of vectors
>>>>of an appropriate size.
>>>>
>>>Not quite the "only way".  In simulation, one needs to use the INIT_XX
>>>generics on the block rams.  The attributes are ignored.
>>>
>>>
>>>>Sim and synth tools can handle vector widths
>>>>of several hundred thousand bits, up to natural'high.
>>>>
>>>Somehow I can't see any tool working with a vector length of 2 ** 31 -
>>>1.  (At least not under versions of Windows that have problems
>>>allocating more than 2Gbyte of ram to a process.)
>>>
>>>I have seen std_logic_vectors of several hundred thousand bits used in
>>>Modelsim quite successfully.
>>>
>>>Does anyone have any other practical experience?  I was rather hoping
>>>someone from Synplicity would reply.  I know they read this news
>>>group.
>>>
>>>Thanks,
>>>Allan.
>>>
>>Hi Allan,
>>I use a package that defines a constant of a subtype made of an array
>>of bitvectors, and strings. This is then passed in to the ram/rom
>>block model as INIT_XX values for synthesis and as generics for
>>simulation, compiled with Synplify_pro and simed with Modelsim 5.6e.
>>I've used this for RAM/ROM values up to 64Kx32 in a VirtexII 6000
>>device. The only catch is that I have an issue where I have to run a
>>perl script to fix the line length issue in the .edf file created by
>>synplify, (500 char line length). It works fine though. If this is
>>what you are trying to do, let me know, I can send you an example.
>>
> 
> That's sounds similar to what I'm doing.
> 
> I never instantiate "bare" block rams.  Instead, I always instantiate
> them via a wrapper component.
> The wrapper takes generics to indicate the desired width of the
> address and data buses, and the fpga family (Virtex-E, Virtex-2,
> etc.), and it works out the most efficient way to achieve the result.
> 
> The wrapper also contains an optional simulation model that simulates
> about 10 times faster than the slow slow slow unisim components.
> 
> I guess you could think about it as a coregen replacement, but faster,
> and with much better integration into my tool flow.
> 
> I'm in the process of adding a generic to the wrapper that will allow
> me to initialise the block rams.
> The init generic is a single bit_vector that describes the entire
> memory array.
> 
> I have written code that turns this generic into generics and
> attributes for the individual block rams.  This is based on code I
> wrote a few years ago, and works well.
> 
> I am having a few problems with Synp... uh, a popular synthesis tool
> though.  It uses about 700Mbyte (before my laptop crashes) during
> compilation / elaboration on a trivial test design that instantiates 3
> ramb4 components, although it does eventually produce the correct
> result if I run it on a machine with a few Gbytes of ram.
> A version of the code without the init generics uses much less ram and
> compiles much faster.
> I don't see this problem with other tools.
> 
> Regards,
> Allan
> 


Article: 54428
Subject: Re: Webpack 5.2 and Win98se
From: Jim Stewart <jstewart@jkmicro.com>
Date: Thu, 10 Apr 2003 13:50:21 -0700
Links: << >>  << T >>  << A >>
Steve Lass wrote:
> Native Linux (7.3 and 8.0) and Windows2000 will both be supported in our
> next major release, which is 6.1i in September.

But what about Win98?  Lots and lots of people use
it and refuse to upgrade.  Couldn't take that
much effort to support it since it apparently
runs now with a minor workaround.




Article: 54429
Subject: Re: Cheap(er) FPGA configuration?
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 10 Apr 2003 13:52:41 -0700
Links: << >>  << T >>  << A >>
Petter Gustad <newsmailcomp4@gustad.com> writes:
> I've been playing with my Altera Stratix NIOS Developer Board and it's
> really neat to write the configuration to the AMD FLASH using tftp
> from my Linux machine :-) It only takes a second or so to upload the
> hexout file.

Does NIOS come with an Ethernet MAC, or is one available that doesn't
cost an arm and a leg?  I was thinking about using a Xilinx part with
Microblaze, but Xilinx wants big bucks for their Ethernet, so I'd have
to try to interface the one from OpenCores.

Article: 54430
Subject: Ethernet MAC (was Re: Cheap(er) FPGA configuration?)
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 10 Apr 2003 14:02:13 -0700
Links: << >>  << T >>  << A >>
I wrote:
> Does NIOS come with an Ethernet MAC, or is one available that doesn't
> cost an arm and a leg?  I was thinking about using a Xilinx part with
> Microblaze, but Xilinx wants big bucks for their Ethernet, so I'd have
> to try to interface the one from OpenCores.

Never mind, I found it myself.  Altera's Ethernet core is even more
expensive that Xilinx's.  The one from OpenCores is looking more attractive
all the time.  Now I just need to build a PHY module for use with the
Burched board.  I think I'll use the Level One (Intel) LXT972.

Article: 54431
Subject: Re: Webpack 5.2 and Win98se
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 10 Apr 2003 14:06:02 -0700
Links: << >>  << T >>  << A >>
rickman <spamgoeshere4@yahoo.com> writes:
> If you read the requirements for any of the current Xilinx development
> products you will find that they only support two versions of Windows,
> 2000 and XP.  This is not a bug and I suspect the only thing about it
> that is not permanent is Win2000 support.  My guess is that they will
> drop that in the next release or two.  At that point I expect I will use
> something else for FPGA development.  I am a long way from moving to
> XP.  

It works OK under Linux using Wine, and Xilinx has promised that they'll
have a native Linux version in 2003, so that should be within the next
265 days.  :-)

Article: 54432
Subject: Re: Webpack 5.2 and Win98se
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Thu, 10 Apr 2003 17:07:45 -0400
Links: << >>  << T >>  << A >>
On Thu, 10 Apr 2003 16:50:21 -0400, Jim Stewart wrote:

> Steve Lass wrote:
>> Native Linux (7.3 and 8.0) and Windows2000 will both be supported in
>> our next major release, which is 6.1i in September.
> 
> But what about Win98?  Lots and lots of people use it and refuse to
> upgrade.  Couldn't take that much effort to support it since it
> apparently runs now with a minor workaround.
 
Are you sure that it can run on 98?. I run the tools on Linux using wine,
the 5.x command line tools still work fine but the graphical tools, like
fpga_editor, don't work at all even though the 4.2 versions worked fine.
What that says to me is that there is some Win2K/XP library dependancy
that slipped into the 5.x release. I haven't tried to debug the wine
problem because the 4.2 version for fpga_editor is compatible with the
ncds produced by 5.2 and the native Linux version is just around the
corner.

Article: 54433
Subject: Re: Webpack 5.2 and Win98se
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 10 Apr 2003 14:08:28 -0700
Links: << >>  << T >>  << A >>
Steve Lass wrote:
> Native Linux (7.3 and 8.0) and Windows2000 will both be supported in our
> next major release, which is 6.1i in September.

Jim Stewart <jstewart@jkmicro.com> writes:
> But what about Win98?  Lots and lots of people use
> it and refuse to upgrade.  Couldn't take that
> much effort to support it since it apparently
> runs now with a minor workaround.

What's the workaround?

Article: 54434
Subject: Re: Balanced Presentation
From: hmurray@suespammers.org (Hal Murray)
Date: Thu, 10 Apr 2003 21:10:27 -0000
Links: << >>  << T >>  << A >>
1) For the first time in history IBM announced that "ASIC's are NOT Dead, yet"
>in EE Time Online yesterday.  What an amazing article!  Think about it....they
>are mounting a defense against FPGAs?
>
>http://www.eedesign.com/story/OEG20030409S0025

Interesting reading. Thanks.


At the end...

  "Despite mask costs, most of the cost is in the design,
     There's a lot of room left for tools to ease design costs."

How big is the design cost if I'm just plugging together a
bunch of "standard" library cells.  CPU, cache, memory interface,
junk IO gear, ...

Are any of the big ASIC houses offering an FPGA block as a "standard"
offering yet?

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 54435
Subject: Re: Webpack 5.2 and Win98se
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Thu, 10 Apr 2003 21:17:03 +0000 (UTC)
Links: << >>  << T >>  << A >>
B. Joshua Rosen <bjrosen@polybus.com> wrote:
: On Thu, 10 Apr 2003 16:50:21 -0400, Jim Stewart wrote:

:> Steve Lass wrote:
:>> Native Linux (7.3 and 8.0) and Windows2000 will both be supported in
:>> our next major release, which is 6.1i in September.
:> 
:> But what about Win98?  Lots and lots of people use it and refuse to
:> upgrade.  Couldn't take that much effort to support it since it
:> apparently runs now with a minor workaround.
:  
: Are you sure that it can run on 98?. I run the tools on Linux using wine,
: the 5.x command line tools still work fine but the graphical tools, like
: fpga_editor, don't work at all even though the 4.2 versions worked fine.
: What that says to me is that there is some Win2K/XP library dependancy
: that slipped into the 5.x release. I haven't tried to debug the wine
: problem because the 4.2 version for fpga_editor is compatible with the
: ncds produced by 5.2 and the native Linux version is just around the
: corner.

Do you run a recent wine? Do you use "winver"="nt40", "winme", "win2k" or
"winxp" ? Do you use native msvcrt? If yes, does the native msvcrt dll fit
to the winver version? 

I can install and run webpack 5.2 with a recent wine and use the
graphical tools. I have run the 5.1 fpga_editor from the 60 day demo,
webpack 5.2 doesn't come with that tool.

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 54436
Subject: Re: Webpack 5.2 and Win98se
From: Jim Stewart <jstewart@jkmicro.com>
Date: Thu, 10 Apr 2003 14:19:48 -0700
Links: << >>  << T >>  << A >>
Eric Smith wrote:
> Steve Lass wrote:
> 
>>Native Linux (7.3 and 8.0) and Windows2000 will both be supported in our
>>next major release, which is 6.1i in September.
> 
> 
> Jim Stewart <jstewart@jkmicro.com> writes:
> 
>>But what about Win98?  Lots and lots of people use
>>it and refuse to upgrade.  Couldn't take that
>>much effort to support it since it apparently
>>runs now with a minor workaround.
> 
> 
> What's the workaround?

 From an earlier post today, sorry, I don't have time
to sort out the attribution...

> if you start project navigator with _pn.exe, direct from ..Xilinx\bin\nt it
> will work on W98 (xst,map, par are working impact wont with wdm driver, use
> old .vxd),  make a shortcut on the desktop.


Article: 54437
Subject: Re: Cheap(er) FPGA configuration?
From: kempaj@yahoo.com (Jesse Kempa)
Date: 10 Apr 2003 15:02:24 -0700
Links: << >>  << T >>  << A >>
"Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:<ezbla.141931$fH1.1241184@news.chello.at>...
> > I've been playing with my Altera Stratix NIOS Developer Board and it's
> > really neat to write the configuration to the AMD FLASH using tftp
> > from my Linux machine :-) It only takes a second or so to upload the
> > hexout file.
> 
> That's the same way I do with my ACEX/Cyclone boards. If you have a working
> Ethernet connection with your FPGA it's really more fun. But I'm using
> Windows and had to write a few lines of Java for the tftp (For interest send
> me a mail).
> 
> Martin
> 
> --------------------------------------------------------
> JOP - a Java Processor core for FPGAs now
> on Cyclone: http://www.jopdesign.com/cyclone/

I'm really happy to see that others find the tftp support in the
reference design as cool as I do - no more downloads at 115,200 UART
speeds :)

In case you guys did not already know, the bash/cygwin environment
that ships with the Nios kit also has tftp built in... for those using
Windows environments this is helpful. I usually just leave my dev
boards and machines connected to a common ethernet hub and do my
.hexout downloads from the web server, though.

Jesse Kempa
Altera
jkempa @ altera dot com (nospam: remove spaces)

Article: 54438
Subject: Re: Webpack 5.2 and Win98se
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Thu, 10 Apr 2003 18:05:54 -0400
Links: << >>  << T >>  << A >>
On Thu, 10 Apr 2003 17:17:03 -0400, Uwe Bonnes wrote:

> B. Joshua Rosen <bjrosen@polybus.com> wrote:
> : On Thu, 10 Apr 2003 16:50:21 -0400, Jim Stewart wrote:
> 
> :> Steve Lass wrote:
> :>> Native Linux (7.3 and 8.0) and Windows2000 will both be supported in
> :>> our next major release, which is 6.1i in September.
> :> 
> :> But what about Win98?  Lots and lots of people use it and refuse to
> :> upgrade.  Couldn't take that much effort to support it since it
> :> apparently runs now with a minor workaround.
> :  
> : Are you sure that it can run on 98?. I run the tools on Linux using
> : wine, the 5.x command line tools still work fine but the graphical
> : tools, like fpga_editor, don't work at all even though the 4.2
> : versions worked fine. What that says to me is that there is some
> : Win2K/XP library dependancy that slipped into the 5.x release. I
> : haven't tried to debug the wine problem because the 4.2 version for
> : fpga_editor is compatible with the ncds produced by 5.2 and the native
> : Linux version is just around the corner.
> 
> Do you run a recent wine? Do you use "winver"="nt40", "winme", "win2k"
> or "winxp" ? Do you use native msvcrt? If yes, does the native msvcrt
> dll fit to the winver version?
> 
> I can install and run webpack 5.2 with a recent wine and use the
> graphical tools. I have run the 5.1 fpga_editor from the 60 day demo,
> webpack 5.2 doesn't come with that tool.
> 
> Bye
 
I haven't been specifying winver, which seems to be the problem. 
I just added a version section to my config file and set 
"windows" = "win2k" and that fixed the problem. If windows is
set to "win98" it doesn't work. Just to make sure that that
was the only problem I tried both 

"msvcrt"       = "native, builtin"

and 

"msvcrt"       = "builtin, native"

in the config file. That doesn't seem to make a difference.

Thanks for pointing me in the right direction.

Josh

Article: 54439
Subject: How to store data in a 2D array
From: scottiecs@yahoo.com (Scott)
Date: 10 Apr 2003 15:10:22 -0700
Links: << >>  << T >>  << A >>
I have a VHDL program that receives data from hypertermail in ASCII
form and then sends the data right back to hyperterminal.  Basically
I'm just testing to see if my serial UART is actually working(and it
is).  What I would like to do now is store that received data from
hyperterminal in an array to be manipulated, then send the manipulated
data back to hyperterminal.  I am new to programming VHDL and FPGA's
too by the way.  The data is just integer numbers.

Thanks in advance
Scott Sullivan

Article: 54440
Subject: Using DP RAM for message passing
From: bonehead95121@yahoo.com (Thomas Jones)
Date: 10 Apr 2003 15:16:00 -0700
Links: << >>  << T >>  << A >>
Hello,

We have come up with a scheme to use dual-ported RAM for message
passing.  I will present a strawman and invite all to take potshots.

The scheme is thus: It is a strictly simplex communication scheme
utilizing dual-port, synchronous read, synchronous write RAM across a
completely asynchronous interface.  Each process has read/write access
to the RAM.  The message writer writes a message and sets a 'valid'
bit at its In-Pointer location, then advances its In-Pointer.  That is
to say, the message data AND the valid bit are both in the self-same
RAM.

The message reader spins on its Out-Pointer location waiting for the
'valid' bit to be set.  Because of the uncertain nature of potentially
reading and writing the same location at the same time (and the
attendant, as yet unspecified metastability issues) the reader will
not act upon a 'valid' until two consecutive are detected.  It then
invalidates the location and advances its Out-Pointer.

To detect a potential FIFO overrun the message writer reads the
location simultaneously with the write - each port has separate read
and write data busses, so the write merely asserts write-enable AND
read-enable.  If the 'valid' bit is set then an overrun condition is
detected.  Writer processes which can back-pressure their up-stream
logic may also spin lock waiting for the 'valid' bit to drop.

Any thoughts?  Is this doomed for failure?   Are the two consecutive
reads necessary?  sufficient?

Thanks, 
bonehead95121

Article: 54441
Subject: Re: Webpack 5.2 and Win98se
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Thu, 10 Apr 2003 22:22:35 +0000 (UTC)
Links: << >>  << T >>  << A >>
B. Joshua Rosen <bjrosen@polybus.com> wrote:
: I haven't been specifying winver, which seems to be the problem. 
: I just added a version section to my config file and set 
: "windows" = "win2k" and that fixed the problem. If windows is
: set to "win98" it doesn't work. 

: Just to make sure that that
: was the only problem I tried both 

: "msvcrt"       = "native, builtin"

: and 

: "msvcrt"       = "builtin, native"

: in the config file. That doesn't seem to make a difference.

Don't try to run the CPLD chain with builtin msvcrt. It uses the
the C++ stream library with needs not yet implemented MSVCRT internas.
Builtin MSVCRT still has a way to go...

Bye

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 54442
Subject: Re: Balanced Presentation
From: ldoolitt@recycle.lbl.gov (Larry Doolittle)
Date: Thu, 10 Apr 2003 22:40:22 +0000 (UTC)
Links: << >>  << T >>  << A >>
On Thu, 10 Apr 2003 21:10:27 -0000, Hal Murray <hmurray@suespammers.org> wrote:
>
>Are any of the big ASIC houses offering an FPGA block as a "standard"
>offering yet?

No. Altera and Xilinx have too tight a grip on FPGA IP with
their patent portfolio.

     - Larry

Article: 54443
Subject: Re: OK, where does an FPGA newbie start?
From: "Ben Twijnstra" <bentw@SPAM.ME.NOT.chello.nl>
Date: Fri, 11 Apr 2003 01:01:11 +0200
Links: << >>  << T >>  << A >>
Hi Hank,

Did you know that looking at the article on groups.google.com seemed to have
you name in cleartext (i.e. with the dashes removed)?

> I'm a consultant working on a specific project for a customer. They've got
> requirements that're beyond the abilities of individually-packaged  logic
> gates to implement, so FPGA is in my future. I'm going to use this as an
> opportunity to expand my skills on my customer's (partial) dime. Good
advice
> on talking to several vendors. I had hoped to first learn enough about how
> FPGA is done to at least understand what they're telling me when we meet.

Well, I feel like typing, so here's a brief breakdown of FPGA development,
without trying to side with any one party. Any misassumptions and errors
hould be hopefully quickly rectified by our fellow group members.

Programmable logic comes in roughly two flavours: there's the instant-on
FPGAs (QuickLogic, Actel, Altera Max, the smaller Lattice devices, Xilinx
Coolrunner and 9500 series) and the PLDs that are based on SRAM and need to
be booted after power-on (Xilinx, Altera, Lattice).

The instant-on ones either have their configuration fused-in (Actel (OK,
grotesque simplification), QuickLogic) or are using a Flash or EEPROM-like
structure to hardwire the configuration.

The SRAM-based ones have more registers, memory, PLLs, DLLs and other
features but need to configure themselves once they sense that power is OK.
They can do so in a wild variety of schemes I'll not bore you with; suffice
to say is that you'll need at least 1 extra component on your board to make
these beasts come to life.

With all these devices and manufacturers you'll need to get a hold of a
development kit. Most vendors have a free offering with limited
functionality and device support, and a full, paid version.

FPGA configurations, whether for instant-on ones or the self-configuring
ones can be developed in numerous ways. There's the old-fashioned
schematics, and there's hardware description languages such as VHDL and
Verilog that you can use for more complex designs. Hardware description
languages focus on the behaviour of your circuit, and not as much on the
actual implementation of it.

If you want to get ultimately freaky, you can also tap in netlists yourself
using the EDIF format, which is slightly reminiscent of LISP. This road is
not recommended at this stage. Actually, it's never recommended unless
you're in a really tight spot and know exactly what you're doing.

Most of the development kits supply you with some sort of simulation
functionality, in which you can apply stimuli to your design and see what
comes out of it, and what happens in between. Depending on the vendor, and
whether you pay for their kit or not, this simulator will vary in
functionality. (Plug:) The luxury road is taken if you somehow get yourself
a copy of ModelSim, one of the best simulators I've ever used.

Once you think that, after simulation, your design is doing what it should
do, there's the so-called Fitting, or Place&Route stage. Every vendor has
their own software for that (part of the development kit), and this software
will map your design onto an actual device. It will choose a device pinout
(unless you've locked it down), and in the end will tell you hat the maximum
clock frequency is that you can have this device run at to perform stably.

Once you're satisfied with functionality, the pinout and the maximum
frequency you're all set to configure the device itself, its progamming
device, or its programming device's external Flash. All vendors either sell
programming cables or actual device programmers

Basically, without going into any level of detail, that's it. This is called
'the flow'. If you want to know more about the hardware description
lanuages, check out the comp.lang.verilog and comp.lang.vhdl newsgroups.
Verilog is quite popular in the US and Japan, VHDL seems to be the standard
in the rest of the world.

In the end, I would go for the vendor that offers you the best design
support in you region. Try to stick to either VHDL or Verilog, as it will
make your designs more portable between vendor architectures; it's like
programming in C or C++ without an OS-specific framework: your design should
run on any of the vendors' devices.

And of course, if you have any questions, just post them on either of the
newsgroups. There are no stupid questions.

Best regards,



Ben




Article: 54444
Subject: Re: Webpack 5.2 and Win98se
From: Duane Clark <junkmail@junkmail.com>
Date: Thu, 10 Apr 2003 16:03:02 -0700
Links: << >>  << T >>  << A >>
B. Joshua Rosen wrote:
>  
> ... Just to make sure that that
> was the only problem I tried both 
> 
> "msvcrt"       = "native, builtin"
> 
> and 
> 
> "msvcrt"       = "builtin, native"
> 

My very unscientific results on adding a probe in fpga_editor in Wine 
(done several months ago, so things may have changed).

native msvcrt - 42 seconds
builtin msvcrt - 4002 seconds

No, that is not a typo ;)

-- 
My real email is akamail.com@dclark (or something like that).


Article: 54445
Subject: Re: Balanced Presentation
From: "John_H" <johnhandwork@mail.com>
Date: Thu, 10 Apr 2003 23:03:37 GMT
Links: << >>  << T >>  << A >>
Hasn't the cross licensing between Xilinx and IBM resulted in Xilinx access
to the PPC processor core for the Virtex-II Pro series and IBM access to the
FPGA fabric for their ASICs ?


"Larry Doolittle" <ldoolitt@recycle.lbl.gov> wrote in message
news:slrnb9bsnq.jbb.ldoolitt@recycle.lbl.gov...
> On Thu, 10 Apr 2003 21:10:27 -0000, Hal Murray <hmurray@suespammers.org>
wrote:
> >
> >Are any of the big ASIC houses offering an FPGA block as a "standard"
> >offering yet?
>
> No. Altera and Xilinx have too tight a grip on FPGA IP with
> their patent portfolio.
>
>      - Larry



Article: 54446
Subject: vic-20 release on fpgaarcade
From: "MikeJ" <support@{nospam}fpgaarcade.com>
Date: Fri, 11 Apr 2003 00:10:22 +0100
Links: << >>  << T >>  << A >>
A Vic-20 in an fpga released at www.fpgaarcade.com.
builds under xilinx webpack.

Complete implementation of the original vic-20 home computer using Daniel
Wallner's t65 cpu core from opencores.

For those on the cbm group, please note this project has nothing to do with
the excellent Commodore-1 by Jeri Ellsworth and is simply to preserve the
original Vic-20. For this reason, I will not be extending this open source
design or supplying dedicated boards to run it on.

If you don't have a suitable xilinx board lying around, you may be able to
persuade Jeri to include (and charge for) a version of this core that runs
on her board.

Cheers,
MikeJ



Article: 54447
Subject: Re: OK, where does an FPGA newbie start?
From: "Just Some Guy" <phony@nowhere.cc>
Date: Thu, 10 Apr 2003 16:56:48 -0700
Links: << >>  << T >>  << A >>
Thanks for such an extensive reply. Just for those who might stumble across
this thread in the future, let me add some of the resources I've run across
in my research.

Programmable Logic Design Quick Start Handbook:
http://www.xilinx.com/publications/products/cpld/logic_handbook.pdf

Introductory articles on FPGA/CPLD pitched toward a hobbyist audience. Quite
good, and cover some of the same topics that you bring up (though you've
certainly added some). Click on the "Learning the Ropes-FPGA and CPLD"
links.
http://www.dtweed.com/circuitcellar/xcyliaxi.htm

Listing of tutorials on VHDL:
http://www.tutorgig.com/showurls.jsp?group=897&index=0

Xilinx ISE 5 In Depth Tutorial
http://stewks.ece.stevens-tech.edu/CpE487-S03/Xilinx2002/SoftwareDesign/Tuto
rials/ise5tut.pdf

VHDL and Verilog Compared and Contrasted
http://www.angelfire.com/in/rajesh52/verilogvhdl.html

"Ben Twijnstra" <bentw@SPAM.ME.NOT.chello.nl> wrote in message
news:YImla.554$KF1.80422@amstwist00...
> Hi Hank,
>
> Did you know that looking at the article on groups.google.com seemed to
have
> you name in cleartext (i.e. with the dashes removed)?
>
> > I'm a consultant working on a specific project for a customer. They've
got
> > requirements that're beyond the abilities of individually-packaged
logic
> > gates to implement, so FPGA is in my future. I'm going to use this as an
> > opportunity to expand my skills on my customer's (partial) dime. Good
> advice
> > on talking to several vendors. I had hoped to first learn enough about
how
> > FPGA is done to at least understand what they're telling me when we
meet.
>
> Well, I feel like typing, so here's a brief breakdown of FPGA development,
> without trying to side with any one party. Any misassumptions and errors
> hould be hopefully quickly rectified by our fellow group members.
>
> Programmable logic comes in roughly two flavours: there's the instant-on
> FPGAs (QuickLogic, Actel, Altera Max, the smaller Lattice devices, Xilinx
> Coolrunner and 9500 series) and the PLDs that are based on SRAM and need
to
> be booted after power-on (Xilinx, Altera, Lattice).
>
> The instant-on ones either have their configuration fused-in (Actel (OK,
> grotesque simplification), QuickLogic) or are using a Flash or EEPROM-like
> structure to hardwire the configuration.
>
> The SRAM-based ones have more registers, memory, PLLs, DLLs and other
> features but need to configure themselves once they sense that power is
OK.
> They can do so in a wild variety of schemes I'll not bore you with;
suffice
> to say is that you'll need at least 1 extra component on your board to
make
> these beasts come to life.
>
> With all these devices and manufacturers you'll need to get a hold of a
> development kit. Most vendors have a free offering with limited
> functionality and device support, and a full, paid version.
>
> FPGA configurations, whether for instant-on ones or the self-configuring
> ones can be developed in numerous ways. There's the old-fashioned
> schematics, and there's hardware description languages such as VHDL and
> Verilog that you can use for more complex designs. Hardware description
> languages focus on the behaviour of your circuit, and not as much on the
> actual implementation of it.
>
> If you want to get ultimately freaky, you can also tap in netlists
yourself
> using the EDIF format, which is slightly reminiscent of LISP. This road is
> not recommended at this stage. Actually, it's never recommended unless
> you're in a really tight spot and know exactly what you're doing.
>
> Most of the development kits supply you with some sort of simulation
> functionality, in which you can apply stimuli to your design and see what
> comes out of it, and what happens in between. Depending on the vendor, and
> whether you pay for their kit or not, this simulator will vary in
> functionality. (Plug:) The luxury road is taken if you somehow get
yourself
> a copy of ModelSim, one of the best simulators I've ever used.
>
> Once you think that, after simulation, your design is doing what it should
> do, there's the so-called Fitting, or Place&Route stage. Every vendor has
> their own software for that (part of the development kit), and this
software
> will map your design onto an actual device. It will choose a device pinout
> (unless you've locked it down), and in the end will tell you hat the
maximum
> clock frequency is that you can have this device run at to perform stably.
>
> Once you're satisfied with functionality, the pinout and the maximum
> frequency you're all set to configure the device itself, its progamming
> device, or its programming device's external Flash. All vendors either
sell
> programming cables or actual device programmers
>
> Basically, without going into any level of detail, that's it. This is
called
> 'the flow'. If you want to know more about the hardware description
> lanuages, check out the comp.lang.verilog and comp.lang.vhdl newsgroups.
> Verilog is quite popular in the US and Japan, VHDL seems to be the
standard
> in the rest of the world.
>
> In the end, I would go for the vendor that offers you the best design
> support in you region. Try to stick to either VHDL or Verilog, as it will
> make your designs more portable between vendor architectures; it's like
> programming in C or C++ without an OS-specific framework: your design
should
> run on any of the vendors' devices.
>
> And of course, if you have any questions, just post them on either of the
> newsgroups. There are no stupid questions.
>
> Best regards,
>
>
>
> Ben
>
>
>



Article: 54448
Subject: Modular Design: last step to finish
From: "Eduardo Wenzel Brião" <briao@inf.pucrs.br>
Date: Thu, 10 Apr 2003 18:45:40 -0700
Links: << >>  << T >>  << A >>
With help from everybody of this forum, I can to perform Modular Design flow with sequential and asynchronous circuits. But I can solve
just one problem. When I install Bus Macros, according XAPP290 example, I need two kind of VCC and GND signals to feed BM. One
VCC and GND signal for each area group inside of FPGA. I don´t want use IO pins of FPGA to feed bus macros. I wanna create internal
signals. I heard to talk it´s possible to create internal signals (constants) inside LUTs. (To instanciate LUTs inside of VHDL code and
assigning values to them) 
But I can´t perform the flow. When I execute NGDBUILD tool, it issued some errors: 

ERROR:NgdBuild:519 - The EQN value of "()", on the LUT1 symbol 
   "Internal_GND_fixed", is not a valid equation. 
ERROR:NgdBuild:520 - The above-referenced equation has the following error: 
   Unexpected ')'. 

For my Thesis, this problem is the last step with Modular Design flow using partial reconfiguration. I just want to know how creating this
internals signals. My next step is build reconfigurables designs with OCP. 

Do someone know how to create internals signals? How can I using bus macros without auxiliary IO pins? 
I just gratefull about your help. 

Eduardo Wenzel Brião 
Pontifícia Universidade Católica do Rio Grande do Sul - PUCRS 
Porto Alegre city 
Brazil



Article: 54449
Subject: Dynamic Reconfigurable FPGAs
From: "Jihan Zhu" <jihan@itee.uq.edu.au>
Date: Fri, 11 Apr 2003 12:01:50 +1000
Links: << >>  << T >>  << A >>

Hello,



I am wondering if you know any available FPGA devices which are dynamically
reconfigurable. I am doing a project in the area of evolvable hardware and I
am looking to buy a board with dynamic reconfigurable FPGAs.



Thank you in advance for any pointers,



Jihan






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