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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi friends,
I am a developer and supplier of FPGA boards and modules
located in Germany.
At present I plan to develop a hardware-platform for
training/education based on a XILINX FPGA.
For that purpose, I like to discuss what features are
indispensable, important and nice-to-have.
(I also look for partners, that can help with example
designs, tutorials and instructional experiments).
The most important issues are:
- Choice of a appropriate FPGA device
Is it better to choose a device, that is supported by the free
XILINX ISE-WEB-Tools or to choose one with enhanced features like
integrated CPU and RocketIO ?
- Choice of peripheral units
What kind of I/O interfaces are needed with respect to the price / benefit
ratio ?
VGA connector (simple solution based on resistors or with dedicated
Video-DAC ?)
PS2 keyboard interface
analog IN/OUT (speed, resolution, ...)
dedicated Audio and/or Video Codec ?
integrated LCD display (color / black&white, text or graphics, with or
without external controller)
rotary encoder, integrated keyboard, switches, leds, 7_seg displays, ...
memory ? (SRAM, DRAM, DDRSDRAM, EEPROM, ...)?
expansion connector / slot ?
something else ?
- Other details
with or without enclosure ?
with/without flash-memory for stand-alone FPGA configuration
- What kind of documentation/papers are needed ?
VHDL Tutorial, Description of FPGAs, complete schoolbook, ... other ?
lessons with experiments and controlling of learning target ?
Because I already designed a USB 2.0 interface for FPGAs (using Cypress
FX-2)
I think about using this interface to download configuration bitstreams
and to exchange data (FPGA <--> PC). Unfortunately my driver supports W2K
and XP
but not WIN89/SE/ME.
- Is the USB interface widespread enough to use it ?
- Is it a big disadvantage if WIN89 is not supported ?
- Should I include a parallel-download-cable to allow downloading and
debugging using ImPact ?
I think about making the board-schematics / layout and
VHDL-examples/tutorials of the device
available under the terms of a general-public-license. The hardware itself
will be sold at a
very low price.
Any notes, proposals and comments are most welcome .
THANK YOU.
- Manfred Kraus
To reach me use this Email address : "mkraus" AT "cesys" DOT "com"
Article: 54326When I used to live in India, it was very common for established 'brick-and-mortar' shops (as distinct from sidewalk or pushcart vendors) to have prominently displayed signs saying "fixed-rate" -- meaning no haggling. In the developed world, we tend to take fixed pricing for granted in most things: the vendor sets the price, anybody can find out what the price is, then you decide whether or not to buy. Some industries follow a different model: while prices are fixed, multiple pricing plans are offered, and vendors make it difficult to find out the best available price -- for example (in the US anyway) airplane tickets and telephone service. In others, eg used cars, prices aren't fixed, they are pretty much set by whatever you can negotiate. Somewhere along the way, major electronics vendors (very noticeable in FPGAs) have decided that the car pricing model would be better for their business. If they think you'll buy another brand, you'll be offered a sweet deal, whereas if they think they've got you the price goes up. Also the manufacturers control the price, even though you buy from a distributor. The one exception seems to be DigiKey, which seems to act as a broker not a franchised distributor (somebody please tell me why I should care ?) and offers Xilinx parts at a fixed and public price. At the present time I'm being offered Xilinx parts by my friendly distributor for _more_ than DigiKey's price. Figuring there's got to be a lot of margin in here somewhere, I called another distributor -- so far what they've told me is "we'll check with Xilinx and let you know what we can offer you". If anybody has figured out a successful strategy for negotiating FPGA prices, I'd love to hear about it, offline or on. My two cents, -rajeev- ---------------- Nicolas Hervé <nicolas.herve@enssat.fr> wrote in message news:<3E917D5B.3020107@enssat.fr>... > Where can I get the price of fpga chips ? > > Xilinx: Spartan, Virtex-2 and Virtex-2Pro > Altera: Stratix and EscaliburArticle: 54327
I've noticed that some FPGAs show up on eBay. Don't know whether it would be a good or a bad idea to try buying this way, but it's something to consider. "Nicolas Hervé" <nicolas.herve@enssat.fr> wrote in message news:3E917D5B.3020107@enssat.fr... > Where can I get the price of fpga chips ? > > Xilinx: Spartan, Virtex-2 and Virtex-2Pro > Altera: Stratix and Escalibur >Article: 54328
Hi all,
I 'm implementing a SpartanII-based PCB (FPGA : XC2S100-5TQ144) and the
Vccint pins are driven by a 2.5V regulator (MAX1793). Regarding the Vcco
Pins, I tried to use the LVTTL standard (Vcco=3.3V) for IO Banks 2 and 3
and the LVCMOS2 standard (Vcco=2.5 V) for all the other IO Banks. The
regulators that I use are able to cover the power requirements of the FPGA.
However, the PCB does not operate normally. Does anyone know what may be
wrong?
Thank you in advance,
Stamatis
Article: 54329Bob Perlman <bobsrefusebin@hotmail.com> wrote in message news:<u0v49vgmc25pjlscv0velri1isd4ivg3ls@4ax.com>... > Hi - > > Using the falling clock edge may violate the "fully synchronous > design" philosophy of using one edge for everything, but it's a lot > better than trying to engineer on-chip delays that slide the data > relative to the clock. Do a timing analysis to convince yourself that > falling edge clocking will work, being sure to take into account the > effect of things like non-ideal clock duty cycle. If the numbers look > good, use the falling edge. > > If for some reason the falling edge won't work timing-wise, you could > always delay the clock by lengthening its PCB trace. PCB trace delays > are pretty stable; if the trace is stripline (i.e., embedded between > two planes), the delay is a function of the dielectric constant only, > not the trace geometry. But to delay it half a clock cycle would take > about a 3 foot trace in FR-4. That doesn't sound terribly appealing > to me. > > If the data source and destination were in the same chip, be it FPGA > or ASIC, you'd probably use a low-skew clock tree to distribute clocks > to both the driving and receiving registers, instead of using the > source-synchronous scheme you've described. > > Bob Perlman > Cambrian Design Works I agree that at interfaces, using falling edge is not horrible - but since he is using a part with a DCM, why not dial in half a cycle of delay using the fixed phase offset and clock the data in with that? Marc > On Mon, 7 Apr 2003 23:41:10 -0700, "George Fang" <gfang10@cox.net> > wrote: > > >Hi everyone, > > We are doing a project in which a Xilinx FPGA (2v1000-5) interface to a > >high speed chip providing data and clock. The data and the clock arrive at > >the FPGA pins at roughly the same time. The data skew is about 0.7 ns from > >the fastest pins to the slowest pins and the rising edge of the clock comes > >at about the middle of the skew range. The clock cycle is about 13ns. > > My questions is how can we reliably lock the data in to the FPGA. An > >intuitive answer is to use the falling edge of the clock to lock the data > >into registers but I was told by some designer that this does not agree with > >the philosophy of "fully synchronous design", that we should stay with the > >rising edge but use proper constraints to let tool take care of the delay > >matching. > > I tried to specify the relationship between the data and the clock using > >"OFFSET IN BEFORE" and "OFFSET IN AFTER" constraints but the post P&R result > >did not indicate this had any expected effect. The rising edge of the clock > >always comes at the middle of the skew range at the register D pins > >resulting in unreliable data locking. > > Can someone explain the correct way of accomplishing this? Can the tools > >automatically take care of inserting delays to meet setup and hold timing? > >Would it be different if the data source and the design currently in FPGA > >are all in the same ASIC chip? > > > > Thanks in advance for any info. > > > >George > >Article: 54330
Hi - On 8 Apr 2003 07:51:53 -0700, mrand@my-deja.com (Marc Randolph) wrote: >I agree that at interfaces, using falling edge is not horrible - but >since he is using a part with a DCM, why not dial in half a cycle of >delay using the fixed phase offset and clock the data in with that? If clock duty cycle is a problem, sure - use the Virtex DLL's 180-degree output. Bob Perlman Cambrian Design Works > > Marc > > >> On Mon, 7 Apr 2003 23:41:10 -0700, "George Fang" <gfang10@cox.net> >> wrote: >> >> >Hi everyone, >> > We are doing a project in which a Xilinx FPGA (2v1000-5) interface to a >> >high speed chip providing data and clock. The data and the clock arrive at >> >the FPGA pins at roughly the same time. The data skew is about 0.7 ns from >> >the fastest pins to the slowest pins and the rising edge of the clock comes >> >at about the middle of the skew range. The clock cycle is about 13ns. >> > My questions is how can we reliably lock the data in to the FPGA. An >> >intuitive answer is to use the falling edge of the clock to lock the data >> >into registers but I was told by some designer that this does not agree with >> >the philosophy of "fully synchronous design", that we should stay with the >> >rising edge but use proper constraints to let tool take care of the delay >> >matching. >> > I tried to specify the relationship between the data and the clock using >> >"OFFSET IN BEFORE" and "OFFSET IN AFTER" constraints but the post P&R result >> >did not indicate this had any expected effect. The rising edge of the clock >> >always comes at the middle of the skew range at the register D pins >> >resulting in unreliable data locking. >> > Can someone explain the correct way of accomplishing this? Can the tools >> >automatically take care of inserting delays to meet setup and hold timing? >> >Would it be different if the data source and the design currently in FPGA >> >are all in the same ASIC chip? >> > >> > Thanks in advance for any info. >> > >> >George >> >Article: 54332
Any one any tips for using FPGA (possibly Spartan XL) or CPLD (CoolRunner XPLA3 ?)as an interface to an LCD with two backplanes? cheers NormanArticle: 54333
In the TQ144 and in the PQ208 package, all VCCIO Pins are bonded together. You cannot use different VCCIO voltages for each bank with this packages. -Manfred "Stamatis Sotiropoulos" <ssothro@hotmail.com> schrieb im Newsbeitrag news:b6umht$1h4a$1@ulysses.noc.ntua.gr... > Hi all, > I 'm implementing a SpartanII-based PCB (FPGA : XC2S100-5TQ144) and the > Vccint pins are driven by a 2.5V regulator (MAX1793). Regarding the Vcco > Pins, I tried to use the LVTTL standard (Vcco=3.3V) for IO Banks 2 and 3 > and the LVCMOS2 standard (Vcco=2.5 V) for all the other IO Banks. The > regulators that I use are able to cover the power requirements of the FPGA. > However, the PCB does not operate normally. Does anyone know what may be > wrong? > > Thank you in advance, > Stamatis > >Article: 54334
Hi George, you might consider using the Virtex-II DCMs. Either by using the CLK90 or CLK180 outputs for data capture or by adjusting the Phase_Shift value of you FPGA clock. I would prefer the first proposal but which one is better depends on the rest of your design. Greetings - ManfredArticle: 54335
I've finally encountered a design problem where discrete logic isn't going to cut it, and I'll need to use FPGAs. I've been reading up on the topic from various places on the net, but I have a sense that this scattershot approach isn't efficient and that I'd benefit from a more organized methodology. To educate myself and develop skills, what should I start with, and what should I follow on with? I have degrees in EE and Computer Science, but am coming from a virtual zero knowledge point in programmable logic. My particular application is Digital Signal Processing-ish in nature (frequency synthesis, signal correlation, high-speed arithmetic, etc.) if that matters. Thanks for any suggestions.Article: 54336
> > Anybody had success in this regard? Can you tell me which USB->LPT > > adaptor you used? I don't believe any of them will work for this kind of application. Xilinx installs a device driver thats main purpose is to gain I/O port access to the parallel port hardware in order to bit-bang the data lines. USB adapters that I'm familar with work at a completely different level and don't emulate the hardware at all and so won't work. There are PCMCIA parallel port cards available that provide 'normal' hardware, like the Quatech SPP-100.Article: 54337
On 8 Apr 2003 07:55:28 -0700, Emile <banktrade2002@yahoo.com> wrote: >Nicolas Hervé <nicolas.herve@enssat.fr> wrote in message news:<3E917D5B.3020107@enssat.fr>... >> Where can I get the price of fpga chips ? >> >> Xilinx: Spartan, Virtex-2 and Virtex-2Pro >> Altera: Stratix and Escalibur > >This is pricing for a just a few Xilinx devices that we carry - stock >items. You may contact us for more prices. Here's my collection of list prices for Xilinx devices. I haven't checked it in a while, so if anyone has updates I'd like to hear about it. Also, if someone can put together a simlar list for Altera, I'd like to see that too. # Part I/O cells RAM price # Export toggle for XC2Sxx-5: 276.9 MHz XC2S50-5PQ208C 140 1536 32 14.75 XC2S100-5PQ208C 140 2400 40 19.55 XC2S150-5PQ208C 140 3456 48 21.60 XC2S200-5PQ208C 140 4704 56 26.25 XC2S50-5FG256C 176 1536 32 16.65 XC2S100-5FG256C 176 2400 40 24.65 XC2S150-5FG256C 176 3456 48 27.00 XC2S200-5FG256C 176 4704 56 32.45 XC2S100-5FG456C 196 2400 40 31.00 XC2S150-5FG456C 260 3456 48 35.10 XC2S200-5FG456C 284 4704 56 39.10 # Export toggle for XC2SxxE-6: 357 MHz XC2S100E-6PQ208C 146 2400 40 22.75 XC2S200E-6PQ208C 146 4704 56 29.80 XC2S300E-6PQ208C 146 6144 64 41.30 ($17.95 for qty 250K) XC2S100E-6FT256C 182 2400 40 28.75 XC2S200E-6FT256C 182 4704 56 36.25 XC2S300E-6FT256C 182 6144 64 50.75 XC2S400E-6FT256C 182 9600 160 91.52 XC2S100E-6FG456C 202 2400 40 36.10 XC2S200E-6FG456C 263 4704 56 44.45 XC2S300E-6FG456C 329 6144 64 61.55 XC2S400E-6FG456C 329 9600 160 111.10 XC2S600E-6FG456C 329 13824 288 152.90 XC2S400E-6FG676C 410 9600 160 141.90 XC2S600E-6FG676C 514 13824 288 194.70 # Export toggle for XCVxxE-6: 357 MHz XCV300E-6FG256C 176 6144 128 160.00 XCV400E-6FG676C 404 9600 160 269.00 XCV600E-6FG676C 444 13824 288 454.00 # Export toggle for XCVxxE-7: 400 MHz XCV50E-7FG256C 176 1536 64 51.45 XCV100E-7FG256C 176 2400 80 77.70 XCV200E-7FG256C 176 4704 112 134.00 XCV200E-7FG456C 284 4704 112 138.00 XCV300E-7FG256C 176 6144 128 204.00 XCV300E-7FG456C 312 6144 128 236.00 XCV400E-7FG676C 404 9600 160 376.00 # price each for quantity 25-99 # Export toggle for XC2Vxx-4: 653.59 MHz # multipliers XC2V500-4FG456C 264 6144 576 134.00 32 XC2V1000-4FG256C 172 10240 720 177.00 40 XC2V1000-4FF896C 432 10240 720 230.00 40 XC2V1000-4FG456C 324 10240 720 194.00 40 XC2V1500-4BG575C 392 15360 864 353.10 48 XC2V1500-4FF896C 528 15360 864 403.70 48 XC2V3000-4FG676C 484 28672 1728 598.00 96 XC2V4000-4FF1152 824 46080 2160 1975.00 120 XC2V6000-4FF1152C 824 67584 2592 2669.00 144 # price each for quantity 25-99 # Export toggle for XC2Vxx-5: 751.31 MHz XC2V40-5FG256C 88 512 72 46.95 4 XC2V80-5FG256C 120 1024 144 59.45 8 XC2V250-5FG256C 172 3072 432 122.00 24 XC2V250-5FG456C 200 3072 432 132.00 24 XC2V500-5FG256C 172 6144 576 206.00 32 XC2V500-5FG456C 264 6144 576 226.00 32 XC2V1000-5FG256C 172 10240 720 332.00 40 XC2V1000-5FG456C 324 10240 720 364.00 40 XC2V1000-5BG575C 328 10240 720 285.00 40 XC2V1000-5FF896C 432 10240 720 322.00 40 XC2V1500-5BG575C 392 15360 864 495.00 48 XC2V1500-5FG676C 392 15360 864 471.90 48 XC2V1500-5FF896C 528 15360 864 565.40 48 XC2V2000-5FG676I 456 21504 1008 877.00 56 XC2V3000-5FF1152C 720 28672 1728 1184.00 96 XC2V4000-5FF1152C 824 46080 2160 1975.00 120 # price each for quantity 25-99 XC2VP2-FG256 140 2816 216 ? 12 XC2VP2-FG456 156 2816 216 ? 12 XC2VP2-FF672 204 2816 216 ? 12 XC2VP4-FG256 140 6016 504 ? 28 XC2VP4-FG456 248 6016 504 ? 28 XC2VP4-6FF672CES 348 6016 504 350.00 28 XC2VP7-5FG456C 248 9856 792 251.90 44 XC2VP7-6FF672C 396 9856 792 473.00 44Article: 54338
Hi - Sorry - I missed the point that this is Virtex-II, not Virtex. You can fine-tune the DCM output to get pretty much any data-to-clock skew that you want. So you *can* get a reliable on-chip skew, but it's on the clock net, not the data inputs. Bob Perlman Cambrian Design Works On Tue, 08 Apr 2003 15:04:38 GMT, Bob Perlman <bobsrefusebin@hotmail.com> wrote: >Hi - > >On 8 Apr 2003 07:51:53 -0700, mrand@my-deja.com (Marc Randolph) wrote: > >>I agree that at interfaces, using falling edge is not horrible - but >>since he is using a part with a DCM, why not dial in half a cycle of >>delay using the fixed phase offset and clock the data in with that? > >If clock duty cycle is a problem, sure - use the Virtex DLL's >180-degree output. > >Bob Perlman >Cambrian Design Works > >> >> Marc >> >> >>> On Mon, 7 Apr 2003 23:41:10 -0700, "George Fang" <gfang10@cox.net> >>> wrote: >>> >>> >Hi everyone, >>> > We are doing a project in which a Xilinx FPGA (2v1000-5) interface to a >>> >high speed chip providing data and clock. The data and the clock arrive at >>> >the FPGA pins at roughly the same time. The data skew is about 0.7 ns from >>> >the fastest pins to the slowest pins and the rising edge of the clock comes >>> >at about the middle of the skew range. The clock cycle is about 13ns. >>> > My questions is how can we reliably lock the data in to the FPGA. An >>> >intuitive answer is to use the falling edge of the clock to lock the data >>> >into registers but I was told by some designer that this does not agree with >>> >the philosophy of "fully synchronous design", that we should stay with the >>> >rising edge but use proper constraints to let tool take care of the delay >>> >matching. >>> > I tried to specify the relationship between the data and the clock using >>> >"OFFSET IN BEFORE" and "OFFSET IN AFTER" constraints but the post P&R result >>> >did not indicate this had any expected effect. The rising edge of the clock >>> >always comes at the middle of the skew range at the register D pins >>> >resulting in unreliable data locking. >>> > Can someone explain the correct way of accomplishing this? Can the tools >>> >automatically take care of inserting delays to meet setup and hold timing? >>> >Would it be different if the data source and the design currently in FPGA >>> >are all in the same ASIC chip? >>> > >>> > Thanks in advance for any info. >>> > >>> >George >>> >Article: 54339
lishu99@yahoo.com (Lis Hu) wrote in message news:<4faf3f56.0304071140.2c053d3d@posting.google.com>... > Now that Altera has announced discontinuation of LeonardoSpectrum, > I feel even more motivation to explore the alternatives. I plan > to do a signal processing intensive application on a Stratix, > and I wonder if anyone has any advice about the alternatives > to Leonardo. > > Personally, I had a heck of time with the Leonardo GUI crashing and > giving inconsistent results, and have just started scripting it. However, > all of that "bad experience" does not give me confidence about the tool. > > Even though the Altera Reps are starting to say Quartus has VHDL > support, there're constructs that it doesn't support. So as much > as I had hoped that I can use a single tool flow, it is not an option > at the moment. > > Synplify--I heard--is a faster tool? Any benchmarks out there? I would seriously consider using linux for these tools. I have seen improvements of over 10x (yes ! 10x) of the same tool between Windoze and Linux. (I use Redhat 7.3 and 8.0) I've been very happy with Synplify under linux, both gui and scripting work very well. Never saw/tried Leonardo under linux ... Regards, rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores --> http://www.asics.ws/ <--- > Precision RTL --I have never used. Would be interested to hear opinions. > > Thanks, > Lis HuArticle: 54340
I think you 're wrong!. As it is mentioned in the SpartanII datasheet (functional description, page 3, table 3), the TQ144 package has 4 independent IO banks, whereas the PQ208 and VQ100 packages have only one. Is this a datasheet error or not? Regards, Stamatis "Jens Mander" <Jemand@microsoft.com> wrote in message news:b6uph7$969ou$1@ID-22088.news.dfncis.de... > In the TQ144 and in the PQ208 package, all VCCIO Pins are bonded together. > You cannot use different VCCIO voltages for each bank with this packages. > > -Manfred > > > "Stamatis Sotiropoulos" <ssothro@hotmail.com> schrieb im Newsbeitrag > news:b6umht$1h4a$1@ulysses.noc.ntua.gr... > > Hi all, > > I 'm implementing a SpartanII-based PCB (FPGA : XC2S100-5TQ144) and > the > > Vccint pins are driven by a 2.5V regulator (MAX1793). Regarding the Vcco > > Pins, I tried to use the LVTTL standard (Vcco=3.3V) for IO Banks 2 and 3 > > and the LVCMOS2 standard (Vcco=2.5 V) for all the other IO Banks. The > > regulators that I use are able to cover the power requirements of the > FPGA. > > However, the PCB does not operate normally. Does anyone know what may be > > wrong? > > > > Thank you in advance, > > Stamatis > > > > > >Article: 54341
Have you tried to measure the resistance between the VCCOs of different banks with an ohmmeter ? "Stamatis Sotiropoulos" <ssothro@hotmail.com> schrieb im Newsbeitrag news:b6us6c$1qsc$1@ulysses.noc.ntua.gr... > I think you 're wrong!. As it is mentioned in the SpartanII datasheet > (functional description, page 3, table 3), the TQ144 package has 4 > independent IO banks, whereas the PQ208 and VQ100 packages have only one. Is > this a datasheet error or not? > Regards, > Stamatis > > > > "Jens Mander" <Jemand@microsoft.com> wrote in message > news:b6uph7$969ou$1@ID-22088.news.dfncis.de... > > In the TQ144 and in the PQ208 package, all VCCIO Pins are bonded together. > > You cannot use different VCCIO voltages for each bank with this packages. > > > > -Manfred > > > > > > "Stamatis Sotiropoulos" <ssothro@hotmail.com> schrieb im Newsbeitrag > > news:b6umht$1h4a$1@ulysses.noc.ntua.gr... > > > Hi all, > > > I 'm implementing a SpartanII-based PCB (FPGA : XC2S100-5TQ144) and > > the > > > Vccint pins are driven by a 2.5V regulator (MAX1793). Regarding the Vcco > > > Pins, I tried to use the LVTTL standard (Vcco=3.3V) for IO Banks 2 and > 3 > > > and the LVCMOS2 standard (Vcco=2.5 V) for all the other IO Banks. The > > > regulators that I use are able to cover the power requirements of the > > FPGA. > > > However, the PCB does not operate normally. Does anyone know what may be > > > wrong? > > > > > > Thank you in advance, > > > Stamatis > > > > > > > > > > > >Article: 54342
Austin Lesea wrote: > > Rick, > > Spartan IIE on 300 mm has roughly 1/5 the original peak current spike that > Virtex E had. and if you don't supply it (and only supply the minimum in > the data sheet) it powers on cleanly. Hmmm... I am not totally sure of what you are saying. But if you are talking about the maximum currents with an unlimited current PSU, that will have no bearing on my design. When you refer to the data sheet minimum, that is 2 Amps in the industrial temperature range. That is the number I am designing to now. Is this number going to be reduced with the new process? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54343
Ian Young wrote: > > rickman <spamgoeshere4@yahoo.com> wrote: > > >I will try to download Webpack tonight and let it crank for the 10 to 15 > >hours it will take over this modem link. > > > >In the meantime, is there any info in the floorplanner for the 3S200, or > >3S400 device? Does the floorplanner show how many IO pins can be used? > > The WebPACK only supports the 3S50; so, maybe you don't need to do the > big download after all. > > -- Ian Yes, I was misreading the release notes. Hopefully they will add more members to the Webpack version. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54344
I have a problem with this request. It sounds genuine enough, but it is anonymous. Why would anybody who asks a reasonable request for help not give his name? How can he (she or it) expect some effort from one of us when he (she or it) is hiding ? I refuse to help Mr or Ms Anonymous. Peter Alfke ===================== Just Some Guy wrote: > > I've finally encountered a design problem where discrete logic isn't going > to cut it, and I'll need to use FPGAs. I've been reading up on the topic > from various places on the net, but I have a sense that this scattershot > approach isn't efficient and that I'd benefit from a more organized > methodology. To educate myself and develop skills, what should I start with, > and what should I follow on with? I have degrees in EE and Computer Science, > but am coming from a virtual zero knowledge point in programmable logic. My > particular application is Digital Signal Processing-ish in nature (frequency > synthesis, signal correlation, high-speed arithmetic, etc.) if that matters. > > Thanks for any suggestions.Article: 54345
Useful post. I did notice that you left out the XC2S150E entirely. Where did you get your prices? When I check distributors online or by quote, I always get very different pricing. I don't see where they use a sheet price. Did this come from Xilinx? Larry Doolittle wrote: > > On 8 Apr 2003 07:55:28 -0700, Emile <banktrade2002@yahoo.com> wrote: > >Nicolas Hervé <nicolas.herve@enssat.fr> wrote in message news:<3E917D5B.3020107@enssat.fr>... > >> Where can I get the price of fpga chips ? > >> > >> Xilinx: Spartan, Virtex-2 and Virtex-2Pro > >> Altera: Stratix and Escalibur > > > >This is pricing for a just a few Xilinx devices that we carry - stock > >items. You may contact us for more prices. > > Here's my collection of list prices for Xilinx devices. > I haven't checked it in a while, so if anyone has updates I'd like > to hear about it. Also, if someone can put together a simlar list > for Altera, I'd like to see that too. > > # Part I/O cells RAM price > # Export toggle for XC2Sxx-5: 276.9 MHz > XC2S50-5PQ208C 140 1536 32 14.75 > XC2S100-5PQ208C 140 2400 40 19.55 > XC2S150-5PQ208C 140 3456 48 21.60 > XC2S200-5PQ208C 140 4704 56 26.25 > > XC2S50-5FG256C 176 1536 32 16.65 > XC2S100-5FG256C 176 2400 40 24.65 > XC2S150-5FG256C 176 3456 48 27.00 > XC2S200-5FG256C 176 4704 56 32.45 > > XC2S100-5FG456C 196 2400 40 31.00 > XC2S150-5FG456C 260 3456 48 35.10 > XC2S200-5FG456C 284 4704 56 39.10 > > # Export toggle for XC2SxxE-6: 357 MHz > XC2S100E-6PQ208C 146 2400 40 22.75 > XC2S200E-6PQ208C 146 4704 56 29.80 > XC2S300E-6PQ208C 146 6144 64 41.30 ($17.95 for qty 250K) > > XC2S100E-6FT256C 182 2400 40 28.75 > XC2S200E-6FT256C 182 4704 56 36.25 > XC2S300E-6FT256C 182 6144 64 50.75 > XC2S400E-6FT256C 182 9600 160 91.52 > > XC2S100E-6FG456C 202 2400 40 36.10 > XC2S200E-6FG456C 263 4704 56 44.45 > XC2S300E-6FG456C 329 6144 64 61.55 > XC2S400E-6FG456C 329 9600 160 111.10 > XC2S600E-6FG456C 329 13824 288 152.90 > > XC2S400E-6FG676C 410 9600 160 141.90 > XC2S600E-6FG676C 514 13824 288 194.70 > > # Export toggle for XCVxxE-6: 357 MHz > XCV300E-6FG256C 176 6144 128 160.00 > XCV400E-6FG676C 404 9600 160 269.00 > XCV600E-6FG676C 444 13824 288 454.00 > > # Export toggle for XCVxxE-7: 400 MHz > XCV50E-7FG256C 176 1536 64 51.45 > XCV100E-7FG256C 176 2400 80 77.70 > XCV200E-7FG256C 176 4704 112 134.00 > XCV200E-7FG456C 284 4704 112 138.00 > XCV300E-7FG256C 176 6144 128 204.00 > XCV300E-7FG456C 312 6144 128 236.00 > XCV400E-7FG676C 404 9600 160 376.00 > > # price each for quantity 25-99 > # Export toggle for XC2Vxx-4: 653.59 MHz > # multipliers > XC2V500-4FG456C 264 6144 576 134.00 32 > XC2V1000-4FG256C 172 10240 720 177.00 40 > XC2V1000-4FF896C 432 10240 720 230.00 40 > XC2V1000-4FG456C 324 10240 720 194.00 40 > XC2V1500-4BG575C 392 15360 864 353.10 48 > XC2V1500-4FF896C 528 15360 864 403.70 48 > XC2V3000-4FG676C 484 28672 1728 598.00 96 > XC2V4000-4FF1152 824 46080 2160 1975.00 120 > XC2V6000-4FF1152C 824 67584 2592 2669.00 144 > > # price each for quantity 25-99 > # Export toggle for XC2Vxx-5: 751.31 MHz > XC2V40-5FG256C 88 512 72 46.95 4 > XC2V80-5FG256C 120 1024 144 59.45 8 > XC2V250-5FG256C 172 3072 432 122.00 24 > XC2V250-5FG456C 200 3072 432 132.00 24 > XC2V500-5FG256C 172 6144 576 206.00 32 > XC2V500-5FG456C 264 6144 576 226.00 32 > XC2V1000-5FG256C 172 10240 720 332.00 40 > XC2V1000-5FG456C 324 10240 720 364.00 40 > XC2V1000-5BG575C 328 10240 720 285.00 40 > XC2V1000-5FF896C 432 10240 720 322.00 40 > XC2V1500-5BG575C 392 15360 864 495.00 48 > XC2V1500-5FG676C 392 15360 864 471.90 48 > XC2V1500-5FF896C 528 15360 864 565.40 48 > XC2V2000-5FG676I 456 21504 1008 877.00 56 > XC2V3000-5FF1152C 720 28672 1728 1184.00 96 > XC2V4000-5FF1152C 824 46080 2160 1975.00 120 > > # price each for quantity 25-99 > XC2VP2-FG256 140 2816 216 ? 12 > XC2VP2-FG456 156 2816 216 ? 12 > XC2VP2-FF672 204 2816 216 ? 12 > XC2VP4-FG256 140 6016 504 ? 28 > XC2VP4-FG456 248 6016 504 ? 28 > XC2VP4-6FF672CES 348 6016 504 350.00 28 > XC2VP7-5FG456C 248 9856 792 251.90 44 > XC2VP7-6FF672C 396 9856 792 473.00 44 -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54346
Hello, I am using a Xilinx Coolrunner CPLD XCR3384. I test the board with some simple designs and it was working ok (using webpack 5.2 and iMPACT). Then I tried to load the entire design and it failed halfway while programming the CPLD. Since then, the CPLD cannot be detected by the software. Instead it says: "Communications with the cable could not be establish. Check the cable connections and cable power source" Other CPLDs are detected fine from the same software and same power supply. Also, I tired older versions of the webpack without success. It seems that I somehow "lock" the CPLD or configured it improperly so that I can do nothing to it now. If it is that, is there a simple way to erase it without taking it off the board? Thanks, AndreasArticle: 54347
What I'm 'hiding' from is spam and harvestbots. I leave my name and email address off of Usenet postings because I already get a ton of crap from past postings when I didn't. Nobody's ever complained before, but if it makes you feel better, here's the name in a harder-to-harvest form: H-A-N-K F-E-N-S-T-E-R. "Peter Alfke" <peter@xilinx.com> wrote in message news:3E92FB30.983CB73F@xilinx.com... > I have a problem with this request. > It sounds genuine enough, but it is anonymous. > Why would anybody who asks a reasonable request for help not give his > name? How can he (she or it) expect some effort from one of us when he > (she or it) is hiding ? > I refuse to help Mr or Ms Anonymous. > > Peter Alfke > ===================== > Just Some Guy wrote: > > > > I've finally encountered a design problem where discrete logic isn't going > > to cut it, and I'll need to use FPGAs. I've been reading up on the topic > > from various places on the net, but I have a sense that this scattershot > > approach isn't efficient and that I'd benefit from a more organized > > methodology. To educate myself and develop skills, what should I start with, > > and what should I follow on with? I have degrees in EE and Computer Science, > > but am coming from a virtual zero knowledge point in programmable logic. My > > particular application is Digital Signal Processing-ish in nature (frequency > > synthesis, signal correlation, high-speed arithmetic, etc.) if that matters. > > > > Thanks for any suggestions.Article: 54348
Hi
For a project in school i am using a Xilinx FPGA of the XC4000E family.
The source code is almost ready but in many parts of the code I'm having
problems when simulating.(I'm using the Project Manager's built-in simulator
of Xilinx Foundation F3.1i)
This is the piece of the code that doesn't work:
process (STROBE,Reset,CP_offline)
begin
if (CP_offline='1' or Reset='1') then ControlPanel_Online <= '0';
elsif (STROBE'event and STROBE='0') then
if (X='1') then
ControlPanel_Online <= '1';
end if;
end if;
end process;
I suppose it's obvious what this should do. The signal ControlPanel_Online
is set to '1' when there's a negative edge on STROBE and X='1';
This works in the simulation.
But when I try to set ControlPanel_Online back to '0' by making signal
CP_Offline '1', nothing happens! Only when I use the GlobalReset, I can get
ControlPanel_Online back to zero.
It must have something to do with the GSR-network of the FPGA, since I can
only use the GlobalReset and no other signal I intended to use as a reset
(like CP_offline).
Why is my CP_offline signal ignored? I'm not getting any warnings or errors
after synthesis so I really don't have a clue.
I hope my question is clear and that it is a common problem?
Can someone help me out here?
Thanks alot!
Peter
Article: 54349"George Fang" <gfang10@cox.net> wrote in message news:mauka.31$Qq5.23@fed1read02... > Hi everyone, < snip > > My questions is how can we reliably lock the data in to the FPGA. An > intuitive answer is to use the falling edge of the clock to lock the data > into registers but I was told by some designer that this does not agree with > the philosophy of "fully synchronous design", that we should stay with the > rising edge but use proper constraints to let tool take care of the delay > matching. < snip > The philosophy of fully synchronous design is not compromised by using the falling edge of the clock. If you have a min/max duty cycle, the timing constraints between falling and rising edges triggered flops have to be specified. If you choose to correct the duty cycle with a DCM (Digital Clock Manager) you can rely on the 50% duty cycle correction to provide the 1/2 clock cycle timing constraint that the timing analysis will assume. You still have one clock. You still have explicit timing where nothing is asynchronous. You just have non-integer clock cycles. Since this is input-only, you could use the DCM to delay the input clock by a specific phase as long as your system clock is a clean, ungated clock. You could use the delayed clock to just affect the input registers reducing the setup time for the next stage to a clock cycle reduced by the input clock phase shift OR you could use the delayed clock for your system clock if the rest of the timing works fine with that phase shift. Happy coding! - John_H
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