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Hi! In comp.arch.fpga, "CC Nguyen" <> said... > Hi all, > I know this is an old topic, but now I facing it. > I want to implement a double edge triggered flipflop in Virtex. > There's another factor : the clock signal is bursting (sometime it > totally flat, some time running), so I can't use the "clock double" > trick. Any suggestion is apreciated, > I haven't read these old topics, but how about toggeling one FF, using the risng edge and another using falling. If you then take the two results and put them through an XOR... Shouldn't it toggle in double frequency? Does it work? Sorry, I have not yet tested it, it just came to my mind... Be readin' ya, Thomas -- No matter if you are going on-piste or off-piste, just hit the slope and stay healthy! For mail reply replace "nospam" with "kurth".Article: 54476
> I am wondering if you know any available FPGA devices which are dynamically > reconfigurable. I am doing a project in the area of evolvable hardware and I > am looking to buy a board with dynamic reconfigurable FPGAs. The Virtex-II FPGA family from Xilinx (http://www.xilinx.com). They are dynamically as well as partially reconfigurable via the JTAG port using the IEEE 1149.1/1532 standards or via the traditional configuration ports. The reconfiguration is however not that flexible ; you can only re-configure on a column basis. EricArticle: 54477
I stumbled across this site
http://www.theepgd.com
which lists lots more sources for FPGAs than the standard franchised
distributors. It appears that some of these are operating as brokers,
buying and selling excess inventory etc. They will tell you date
codes
and whether the parts are new or not.
For folks who have dealt with these channels, I would be interested in
knowing
1. How much discount you've been able to get relative to franchised
distributor pricing.
2. Any problems or pitfalls to beware of.
3. Were you satisfied, would you do it again ?
4. There seems to be a concentration of brokers in a couple of places,
eg
Florida, and I can't help but wonder if these are separate businesses
or
the same business operating with multiple e-store-fronts. Any idea ?
Thanks !
-rajeev-
Article: 54478Fabrizio Mezzetti wrote: > thank you for your information, but now I must implementation the standard > IEEE 1284 on Altera's FPGA. How I can make? Someone knows gives some > indication to me on like writing or finding of the code? Thanks > "Georg Acher" ha scritto nel messaggio > news:b747ns$6pn$1@wsc10.lrz-muenchen.de... > > >In article , > > "Fabrizio Mezzetti" writes: > >|> Hi my name is Fabrizio and I'm student. I must implementation standard > >|> parallel port (slave) ieee1284 on FPGA. > >|> someone can gives some idea and to suggest to me some interesting web > > site > > >|> one to me to consult? Thanks > > > >http://www.beyondlogic.org/epp/epp.htm > >-- > > Georg Acher, acher@in.tum.de > > http://wwwbode.in.tum.de/~acher > > "Oh no, not again !" The bowl of petunias > > > Fabrizio, Do you have to implement SPP, EPP or ECP mode of your parallel port ? I have some EPP VHDL code, if you want. @+ LaurentArticle: 54479
Jake Janovetz wrote:
>
> Thanks, Uwe-
>
> I'll look at this possibility. I found _my_ err, though. Since I
> don't have the FPGA editor for a little while (offsite, using the
> Webpack), I was trying to use the floorplanner information to
> determine if something was pushed to the IOB by looking at the IOB pin
> mappings. It doesn't appear that this is a valid method to determine
> IOB packing.
>
Jake, you can also read a report generated by MAP to see if FFs
were indeed pushed into the IOB.
That way you don't have to P&R, which saves time.
Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)
Article: 54480Uwe, I once complained about the tri-state buffer polarity to Peter Alfke of Xilinx, and he told me that Xilinx's tri-state buffer is active high tri-state, so the datasheet is actually correct. In other words, active high tri-state means that the tri-state buffer is active low enable. Kevin Brace (If someone wants to respond to what I wrote, I prefer if you will do so within the newsgroup.) Uwe Bonnes wrote: > > > One thing that is missleading in the data sheet is the polarity of the > Tristate Output Buffer enable. While it is shown "active high " in the data > sheets, it is "active low" in reality.Article: 54481
In article <eEAla.175406$Zo.33420@sccrnsc03>, George R. Gonzalez <grg2@attbi.com> wrote: > >From my Computer Science classes, I dimly recall that there is no solution >to the reader-writer problem unless you have a way of doing atomic >test-and-set. That only applies if both sides are contesting the same bit. If one side always sets and the other side just waits for it and then clears you're fine. -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 54482
Hi Laurent. Material VHDL for EPP mode would go very well. Thanks "Laurent Gauch, Amontec" <laurent.gauch@amontec.com> ha scritto nel messaggio news:3E96CA7F.20200@amontec.com... > Fabrizio Mezzetti wrote: > > > thank you for your information, but now I must implementation the standard > > IEEE 1284 on Altera's FPGA. How I can make? Someone knows gives some > > indication to me on like writing or finding of the code? Thanks > > "Georg Acher" ha scritto nel messaggio > > news:b747ns$6pn$1@wsc10.lrz-muenchen.de... > > > > >In article , > > > "Fabrizio Mezzetti" writes: > > >|> Hi my name is Fabrizio and I'm student. I must implementation standard > > >|> parallel port (slave) ieee1284 on FPGA. > > >|> someone can gives some idea and to suggest to me some interesting web > > > > site > > > > >|> one to me to consult? Thanks > > > > > >http://www.beyondlogic.org/epp/epp.htm > > >-- > > > Georg Acher, acher@in.tum.de > > > http://wwwbode.in.tum.de/~acher > > > "Oh no, not again !" The bowl of petunias > > > > > > > Fabrizio, > > Do you have to implement SPP, EPP or ECP mode of your parallel port ? > > I have some EPP VHDL code, if you want. > > @+ > Laurent >Article: 54483
Thanks, It comes to my mind too, but instead of xor I use the mux and have clock signal driving it, looks like it works in low frequency, not sure if it's okay in high freq. In my app. the clock may run as fast as 25 mhz (20 ns per edge, assume its 50% duty) here the algorithm: # Two FD with different edge triger if clock edge rising, then Q1 <= D if clock edge falling, then Q2 <= D # The Mux if clock = 0, then Q = Q2 if clock = 1, then Q = Q1 Dont know if you have better ideas or something bad about this method, please point out. ThanksArticle: 54485
hi, can ne one lemme know all the different faults on FPGA, both interconect and logical faults, on Xilinx based FPGA's. thankin you in advance, naveenArticle: 54486
Hi all!
I'm new to Quartus II, and I'm tring to compile a simple test design.
I have 2 vhd source files: aaa_pkg.vhd and aaa.vhd.
The first contains a package declaration and body, the second use function
defined inside aaa_pkg via the use clause :
library my_lib;
use my_lib.aaa_pkg.all;
When I compile the design Quartus II give me error like this:
"VHDL Use Clause error at aaa.vhd(13): design library my_lib does not
contain primary unit aaa_pkg"
How can I create my own libraries, and how can Quartus II see them ?
Thanks
Andrea
Article: 54487I guess no one is using the Hot2 on the SUN. The answer is yes! I have used it on the SUN and it works! Steve "Sriram" <machosri@yahoo.com> wrote in message news:56210527.0304071344.639ae2cf@posting.google.com... > Hi , > Has anybody in this group used Virtual Computing Corporation(VCC)'s > HOT 2 board and development tools. > Are there any issues I should look out for in interfacing their board > to a SUN Solaris workstation through a PCI bus,or as they claim can I > create Hardware Objects ,use them as function calls in C++ code and > not worry about any problems with the interface part. > > Thanks, > SriramArticle: 54488
Martin Thompson wrote: > I'm just about to start down the Xilinx road and has thought of doing > a similar thing myself (I've been spoiled by Altera's LPM_RAM, which > does a similar thing for you). Don't suppose you can share the code > with us to save reinventing the wheel (probably square to start with > in my case :-) If you have synthesis available, you can infer LPM RAM with brand A or X: here's an example: http://groups.google.com/groups?q=vhdl+address_q+lpm -- Mike TreselerArticle: 54490
In article <b7f5eb6a.0304110842.4abb46a8@posting.google.com>, naveen <cvmnk@yahoo.com> wrote: >hi, > can ne one lemme know all the different faults on FPGA, both >interconect and logical faults, on Xilinx based FPGA's. > thankin you in advance, What do you mean? Soft errors vs hard errors? From the fab (before testing) or after testing? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 54492
Hi Andrea, > I'm new to Quartus II, and I'm tring to compile a simple test design. > I have 2 vhd source files: aaa_pkg.vhd and aaa.vhd. > The first contains a package declaration and body, the second use function > defined inside aaa_pkg via the use clause : > library my_lib; > use my_lib.aaa_pkg.all; > > When I compile the design Quartus II give me error like this: > "VHDL Use Clause error at aaa.vhd(13): design library my_lib does not > contain primary unit aaa_pkg" > > How can I create my own libraries, and how can Quartus II see them ? Assuming that you're using version 2.2 (the versions before that have a different menu structure) do the following: From the Project menu, select "Add/remove files in project" and add both files. Then make sure that aaa_pkg.vhd is the topmost one. You can do this by selecting aaa_pkg.vhd in the list and then hitting the 'Up' button a few times. If that doesn't work, just give another shout. Best regards, BenArticle: 54493
Hi Petter, > The SOPC Builder is not officially supported under Linux yet. However, > I can run the Java files distributed with the Solaris release under > Linux (IBM jre 2.13). But I get a message saying that SOPC Builder > requires an open Quartus II project. > > Is there a way to launch the SOPC Builder from within Quartus II or > trick it to communicate with the Quartus II process? Not at this point. Even though it _should_ work (after all, it's Java), SOPC Builder needs to connect to a Quartus server socket to query the current project. As Quartus under Linux has no such socket open, at the moment I can't think of a way to do this. I did ask around and SOPC Builder should be included in the 3.0 Linux package, with of course the NIOS being available for Linux as well. Best regards, BenArticle: 54494
Rajeev wrote: > I stumbled across this site > http://www.theepgd.com > which lists lots more sources for FPGAs than the standard franchised > distributors. It appears that some of these are operating as brokers, > buying and selling excess inventory etc. They will tell you date > codes > and whether the parts are new or not. > > For folks who have dealt with these channels, I would be interested in > knowing > > 1. How much discount you've been able to get relative to franchised > distributor pricing. I have not dealt with brokers for FPGA's, but I have bought processors and SRAM from them. Pricingwise, if it's a buyer's market like it is now, expect a 20%-25% discount over the best negotiated price from your distributer. If it's a seller's market, expect to be gouged for whatever the market will bear. I've seen $10 parts that just weren't available through distribution go for $100 through a broker. > 2. Any problems or pitfalls to beware of. Not lately. Years ago I got a lot of processor chips that were desoldered pulls that I had to send back. Make sure that you know the exact condition of the parts and then be sure to do incoming inspection on them. You'll not want to solder them down and find out there's a problem with them. The other problem is that dealing with brokers really pisses off your distributer. The broker will quote a price that the francised distributer can't possibly match and this can cause some bad feelings. Remember that you'll really want that distributer to be your friend when things turn around and the broker wants $100 for that $10 part. > 3. Were you satisfied, would you do it again ? > > 4. There seems to be a concentration of brokers in a couple of places, > eg > Florida, and I can't help but wonder if these are separate businesses > or > the same business operating with multiple e-store-fronts. Any idea ? > > Thanks ! > -rajeev-Article: 54495
The full installation for Webpack 5.2i is about 200 MB. I have tried to download this in the past and it can be a real PITA over a modem link. The phone lines here won't support over 28.8kbps which gives it a download time of 21 hours. Try getting a download to run continuously for that long without crapping out. Since I couldn't get a CD from Insight anymore, I started looking for places to get high speed access for a couple of hours. Some of the local for hire facilities did not do what I needed, so I went to the library. They had the highest download rates I have seen *anywhere*! After two hours I not only downloaded the Webpack 5.2i full install, but every one of the other files on that page. It all just fit on a CD. So why do you care? Because if you are bandwidth chalenged like I am, I will make you a copy and mail it to you for $5. I don't know if Xilinx has any problems with me doing this, but I will wait for them to tell me to stop. It is just too painful to make people download huge files like this over a modem. You can send me a $5 bill or a check made out to me personally with your mailing address. If I have to run this through the company accounting it will cost me $10 to cash the checks. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54496
Dear All, I have found a technique to reduce the area and the delay of Booth Multipliers by %10. This technique can be applied on any multiplier implementation which uses the Modified Booth Algorithm. I wonder which companies could benefit from such an improvement.Which companies would like to have it? Can anybody help me to contact them? ThanksArticle: 54497
Hello everyone, I did something interesting which some of you may be interested in. As the size of FPGA becomes larger, the downloading a bit file takes longer and longer time. Xilinx has released Parallel Cable IV which can speed up the downloading. However, the main reason why slow is not because of the cable but because of software overhead. For example, the size of a bit file for XC2V1000 is 510395 bytes. (~ 4Mb) The highest speed of JTAG clocking is 33MHz. If the bit file is downloaded at that speed, it just takes way less than a second. Even with 1MHz clocking, it just takes 4 second. I developed a board which has an Ethernet interafce and Printer port and a controller. I also wrote a program (Unix) so that a bit file is parsed and sent to the board. This way, the overhead is shared and reduced. Using Parallel Cable III and Xilinx tool, it takes around 40 seconds + GUI clikcking time to download a bit file for XC2V1000. With Parallel Cable III and the board mentioned above, it takes less than 4 seconds for everything. (TCKmax:1.57MHz) It could be faster. I have tried faster TCK clocking (> 3MHz) but the downloading became unstable. I used Ethernet interface such that I can place the target far from the WS. But you can do the same using different interface such as USB. It is not ready to release my design for now. But I may provide my design including JTAG class library to the FPGA community in the future. Thank you for your attention. Best regards, Aki NiimuraArticle: 54498
rrr@ieee.org (Rajeev) wrote in message news:<c0f37b00.0304110552.7943dc84@posting.google.com>... > I stumbled across this site > http://www.theepgd.com > which lists lots more sources for FPGAs than the standard franchised > distributors. It appears that some of these are operating as brokers, > buying and selling excess inventory etc. They will tell you date > codes > and whether the parts are new or not. > > For folks who have dealt with these channels, I would be interested in > knowing > > 1. How much discount you've been able to get relative to franchised > distributor pricing. > > 2. Any problems or pitfalls to beware of. > > 3. Were you satisfied, would you do it again ? > > 4. There seems to be a concentration of brokers in a couple of places, > eg > Florida, and I can't help but wonder if these are separate businesses > or > the same business operating with multiple e-store-fronts. Any idea ? > > Thanks ! > -rajeev- Rajeev, As an IC broker, I can tell you that we definitely have our share of bad-apples in this industry. And yes, even some flat our liars. That being said, all of your major contract manufacturers, Flextronics, Celestica, Plexus, and Sanmina-SCI, have a list of "preferred brokers" that they go to for significant savings and shortages. There are many more very reputable companies too; however, the contract manufacturers need to keep their vendor bases to a minimum. If the savings, which can be very significant, interests you, there are several precautions you can take in the early stages of new business with a broker. Try asking for a digital photograph of the product or a copy of the label. Once you find a trusted source in this arena, you'll experience "value added" sales that your franchise distributor can't offer. Boston BrokerArticle: 54499
Hallo, "Steve Lass" <lass@xilinx.com> wrote in news:3E95D117.5090004@xilinx.com... > Native Linux (7.3 and 8.0) and Windows2000 will both be supported in our > next major release, which is 6.1i in September. when support the WEP-Pack bigger FPGA's ?? up to 600kGates ( SpartanIIE or VirtexE ) ?? greatings Erik Spaenig
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