Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
In article <3E9B0799.4E74A073@yahoo.com>, spamgoeshere4@yahoo.com says... > Rich Grise wrote: > > > > anglomont@yahoo.com (TI) wrote in message news:<18a34598.0304061942.18a55177@posting.google.com>... > > > Is there some type of standard test other than hobby projects > > > that could serve to test for example circuit designs ability or > > > sales/marketing skill prior to taking a job? > > > I feel I could do both equally well provided I get paid enough to try > > > hard. > > > ( I suppose the experienced specialists bored with work probably have > > > the same attitude -dont care what I do provided I regularly get paid > > > enough?) > > > > Not a "standard" test, although I've undergone what could be > > regarded as "tests," and in each case it was related to what > > the company wanted the person to accomplish. In a couple of > > cases it involved reading schematics - those jobs I got. In > > another case, for a programmer job, the "test" was to output > > all the prime numbers between 1 and 1000. I panicked, as it > > was a timed test, and didn't even get half-through writing > > the stupid program. Some weeks later, I had a flash of > > inspiration at a bus stop, and wrote a Sieve of Eratosthenes > > in like 5 lines. But that job was long gone. Now I'm a "Tech > > Writer," and I do a variety of things. The only test, really, > > was when I showed the guy a couple of websites I've designed, > > and the recommendation of someone who's practically a partner. > > We're both contractors, and neither of us calls ourself an > > engineer, but when somebody else accidentaly calls me an > > engineer, I don't go to great lengths to correct them. > > Sometimes, when people ask me about a degree, I tell them > > I've had 30 years of BS in the School of Hard Knocks. ;-} > > > I have met good engineers with no degrees and lousy engineers who had > degrees. A degree is just one way to get an education, not a > certificate of accomplishment. > > On the other hand, I have met very, very few good managers. I've had a somewhat different experience. I've had some excellent managers, and a couple of duds. One of the duds was a personal friend. His wife once asked me how he was to work with. I answered, "terrible". I was always going over his cheap-head. His wife shrugged and said "figures". OTOH, most of my managers have been good to *very* good. A few have put their careers on the line to protect their people. > The one who > gave you a timed programming test was clearly out to lunch. Your > abililty to *write* code in a five minute window is no indication of the > *many* tasks you will have to perform as a programmer. I would be much > more interested in how well you write code and how you approach > debugging a program than how fast you can *code* it. Like soneone > posted in one of the other groups... "Since I touch type, I can *write* > code quite fast. Debugging it is another matter" or something > equivalent. I'm no programmer, though I do assembler and VHDL with some regularity. I'd prefer to see a piece of work the individual has done. Not being a programmer, I don't see the importance of coding. Specifications, design, and documentation seem to me to be more important than simple coding. I really don't see the purpose of testing well known algorithms or "tricks". I guess they would weed me out though. *shrug* My first manager out of school threw me a transmission line problem during the interview. IIRC it was an R-C terminated line. In my nervousness I got it exactly wrong (got parallel v.s. series backwards), but convinced him I was right. After hiring on I told him the right answer. ;-) OTOH, at an interview for a competitor (now out of business) I told the HR type, in front of 30 other candidates, to shove his stupid job where it's permanently dark, though if he needed illumination... They did a really *shabby* job of hiring (among other transgressions they accused me of ripping them off on expenses in front of said 30 candidates). -- KeithArticle: 54626
Hi, I'd like to know if it is possible to know the speed of a particular core in Xilinx core generator. For example, I want to create a combinational multiplier. How do I know if it will be fast enough for my design? Even if I choose the 'pipelined' option, how do I know the fastest clock rate possible for a given Fpga? Do I always have to make a project in ISE and test it myself with post place and route simulation? Thanks DavidArticle: 54627
>1. Is 8 bits enough to Error correct a 24 bit data stream? As a rough estimate, you need 1 bit to tell you if you have any errors at all (say parity) and log base 2 (N) to tell you which bit is in error. N includes the error correcting bits since you might have an error in them. 8 bits is enough to correct single bit errors in 64 data bits. You can also detect most double bit errors. But that only works if the error rate is very low and there are no mechanisms that produce multi-bit errors. (so it's reasonable to assume any error is a single bit error) If you have an error on the clock (extra or missed clock) then all bets are off. Maybe not all, but close to that. As others have said, you are probably better off with some sort of CRC and higher level protocol to retransmit packets that get mashed. In this context, NAKs are generally bad. Better to retransmit on timeouts. The ACK/NAK could get lost so you have to do that anyway. If something is broken and you can't correct it, it's better to ignore it rather than try to NAK something. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 54628
>As others have said, you are probably better off with some >sort of CRC and higher level protocol to retransmit packets >that get mashed. In this context, NAKs are generally bad. >Better to retransmit on timeouts. The ACK/NAK could get lost >so you have to do that anyway. If something is broken and you >can't correct it, it's better to ignore it rather than >try to NAK something. Stupid to followup my own post, but... I take that back. You are probably better off trying to figure out why you are getting ANY mashed bits and fixing that. RS232 type signaling is well understood. In a good setup there should be 0 errors. Or rather the error rate is so low that you can't measure it. If you are doing something kludgy like running RS232 links between buildings then maybe you would expect an occasional error. (especially if there is a local thunderstorm) If you are just going a few feet over to the next machine, then the error rate should be 0. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 54629
Hi Rajeev, Brokers are sometimes an extremely helpful resource for obsolete/hard to find components. As Emile rightly pointed out, there are many bad apples out there. I've had experience with my customers getting programmed OTP proms, bad Virtex, a commercial grade part marked as Industrial grade, just about all kinds of things. The parts may not have been carefully handled during transit and stocking. Beware that Xilinx will not provide warranty/replacement or do an RMA for failure analysis if the parts are not bought from an authorized channel. Risk is entirely yours.... My $.02 --Neeraj "Rajeev" <rrr@ieee.org> wrote in message news:c0f37b00.0304140428.5a8c9660@posting.google.com... > Jim, Emile, Leon, > > Thanks all for your responses and good advice ! > > -rajeev-Article: 54630
Hello, which are the most relevant FPGA sites on the net ? Showing applications, free cores, hints, datasheets, discussions and so on ? We plan to make a page of contents at our homepage. All answers welcome - thanks ! Peter SengArticle: 54631
bams wrote: > I have written a module in VHDL using generate and process > statements.when I simulated in Cadence nclaunch tool.It worked > perfectly, Out of curiousity, I tried to simulate in Xilinx, it didn't > synthesis.It is giving me multiple driver problem.Why it is so?why it > is different to different softwares.I am posting the VHDL code for > reference.the multiple driver problem is coming in the output > (Data_out1) in the code.please let me know why the same code isn't > simulated in two different softwares. Hi! There is a simple answer: You can simulate almost everything but you cannot realize everything. I did not read your code, but the "multiple driver problem" means that you have somewhere a shortcut. I.e. you have connected somewhere at least 2 outputs (non-tristatable) together. When you simulate this, sometimes you will very likely receive a value of 'U' (undefined) for the shortcut line. This is the case, when one output is '1' and another is '0'. Of course, synthesis will fail because the synthesis software will decline to accept erroneous designs. Regards, MarioArticle: 54632
On Tue, 15 Apr 2003 09:35:05 +0200, "Peter Seng" <p.seng@seng.de> wrote: >Hello, >which are the most relevant FPGA sites on the net ? >Showing applications, free cores, hints, datasheets, discussions and so on ? >We plan to make a page of contents at our homepage. >All answers welcome - thanks ! news:comp.arch.fpgaArticle: 54633
Hi Jim, "Jim M." <jim006@att.net> wrote in message news:6f3fc0f8.0304141222.15bf1ca8@posting.google.com... > I recently purchased a NIOS Stratix 1S10 Development Kit from Altera > and have mixed feelings about Quartus, SOPC Builder, and the NIOS > Core. (For those poor souls interested, I've included some comments > at the end of this post... feel free to provide feedback.) > > However, here's my question: > > What's the maximum clock frequency anyone has achieved using the NIOS > 3.0 CPU in 32bit mode with the standard peripherals (SRAM, SDRAM, > Ethernet, PIO, UART, etc. as in the Reference Design provided by > Altera)? The highest frequency I could get within one hour using the standard_32 reference design was 92-and-a-bit MHz by changing to an EP1S10F780C5, plus turning some of the logic resynthesis options on. Didn't use any LogicLock. Fitting time was 15min on a 1.25GHz Athlon Classic, be it with 1Gb of memory. Looking at the timing report (of course I tried to get to 100MHz) I found that just about all of the slow paths were either in the SDRAM controller or in the cache. Need any further help? Best regards, BenArticle: 54634
I recall that a team of researchers at Imperial College in London England did some work on ray tracing in FPGAs. @... http://www.doc.ic.ac.uk/~wl/ Rene Tschaggelar <tschaggelar@dplanet.ch> wrote in message news:<5171780df1eb68c6a990dd420f69ed45@news.teranews.com>... > Svjatoslav Lisin wrote: > > Does somebody know any ready hardware systems for raytracing acceleration ? > > How much can it cost? > > You'd need a geometry unit that calculates the traces, with > refraction and reflection > Then you'd need a scene manager that can sort the objects and > find which are to be met by which ray. > It appears to be more of a cpu job to me, once the geometry > is done. > > ReneArticle: 54635
Thanks. That was interesting. This makes the whole byte transmission very sensitive to the startbit edge then. And it also illuminates the requirement to have he idle level at the stop level. There are some RS485 implementations that cut the stop bit off. Such as using the TxBufferEmpty to reload the data and using the TxShiftEmpty for the disabling of the driver. Unless a timer is used to add the stopbit, it will be cut off. Rene Ray Andraka wrote: > Not quite. A UART typically samples the start bit at 16x clock, then from the > estimated center of the start bit (determined by a count of 8 clocks from when > the start goes active), the rest of the bits are simply sampled at the center of > the bit times, ie multiples of 16 clocks from the center of the start bit. It > can be accomplished with a 4 bit counter for the bit timing (preload with 8), a > bit counter, and a shift register with just enough bits to hold the intended > data bits, and parity if desired. The shift register gets enabled by the bit > counter terminal count. A simple state machine to hold the bit counter reset > (to 8) until the start bit is detected and again after the stop bit rounds the > design out. Unless you have a 16x recieve clock available, you'll also need an > accumulator to generate the 16x UART clock from your system clock. All you need > then, is an 8 bit shift register, a mod 16 counter, a 4bit counter and a few > extra flops for the state machine. Plus an accumulator if you need to generate > the 16 x clock. [ snip ]Article: 54636
www.opencores.org is in the process of accepting a verilog to vhdl script that converts a large synthesizable subset. Its open, of course, but you'll have to keep at eye on the mailing list for details as I can't see it on the web site yet. "Fernando" <fortizzz@hotmail.com> wrote in message news:b650f553.0304140846.195a6d9a@posting.google.com... > (In case you haven't seen it) you can try XHDL, I don't know about its > reliability though. It didn't work very well for me. > > http://www.edadirect.com/products.html > > prashantj@usa.net (Prashant) wrote in message news:<ea62e09.0304100920.25920bfe@posting.google.com>... > > Hi, > > Are there any reliable Verilog-to-VHDL or VHDL-to-Verilog converters in the market ? > > > > Thanks, > > PrashantArticle: 54637
2nd Call for Papers and Registration Open 6th MAPLD International Conference Ronald Reagan Building and International Trade Center Washington, D.C. 9-11 September 2003 Abstracts are being accepted for the 6th Military and Aerospace Programmable Logic Devices (MAPLD) International Conference. Programmable devices, technologies, and related aspects of digital engineering will comprise the major emphasis of this conference. Abstracts are due 25 April 2003 to mapld2003@klabs.org. Late papers will be accepted for the Poster Session only. The program will be announced no later than 2 June 2003. This year, there will be special emphasis on the following themes: • Reliability of Hardware and Designs; Fault Tolerance • Reconfigurable/Adaptive Computing Systems • Long-term Space Missions: > 15 Years • Hardware and Software: The Line is Blurring • Radiation Hardening by Design • Digital Signal Processing with Programmable Devices • Design Security • "War Stories" and Lessons Learned For registration information, please visit http://aiaa.org/events/mapld For a complete list of MAPLD topics, information on seminars, invited speakers, special sessions, exhibits, and the full call-for-papers, please visit the MAPLD Int'l Conference at http://klabs.org/mapld03 The Technical Program will consist of technical paper presentations and a poster session. The program will include special Invited Speakers along with the annual Invited History talk. Select papers will be published in an AIAA peer-reviewed journal. This conference is unclassified and open to both foreign participation and U.S. citizens. Invited Speakers Include (more to be announced): Theron M. Bradley Jr. Greg Hinckley Chief Engineer, NASA President, Mentor Graphics Corporation "Welcome and Opening Remarks" "Mil/Aero and PLD's: A CEO's View" SEMINARS will again be offered. Two seminars will be presented: "Advanced Design: Digital Signal Processing, Programmable Device Architecture, and Military/Aerospace Applications" and "Reconfigurable Computing: FPGA-Based, General Purpose, High Performance Systems." PANEL SESSION: Again, we will have leading engineers and managers on our panel for a spirited "discussion." One question left open from the 2002 panel that will be discussed at the 2003 panel is... "Why Is Software So Hard?" A Discussion of the Technical, Programmatic, and Political Factors That Have Lead To Failures Over the Last 40 Years and Its Impact for Future Systems Introduction: James Tomayko Carnegie Mellon University Paul Cerruzi National Air and Space Museum Opening Case Studies: Tony Spear, JPL Magellan and Mars Pathfinder Nancy Leveson Professor of Aeronautics and Astronautics, MIT Jack Garman Lockheed-Martin (NASA, retired) Fred Martin Averstar/Intermetrics Ben "VHDL" Cohen Independent Consultant and Author Steven S. Scott Chief Engineer, Goddard Space Flight Center Kevin Tones NASA Johnson Space Center John P. Dimtroff Aircraft Certification Engineer, FAA The 6th MAPLD International Conference is hosted by the AIAA and the NASA Office of Logic Design. For more information, please visit http://klabs.org/mapld03 or contact: Richard Katz - Conference Chair NASA Goddard Space Flight Center mapld2003@klabs.org Tel: (301) 286-9705 INDUSTRIAL EXHIBIT reservations should be sent to mapld2003@klabs.orgArticle: 54638
Hi. What's the position in writing an well-established type of CPU core (like a Z80) and selling it? Would I have to pay royalties to anyone? Cheers, -- Brendan Lynskey Comodo Research Lab Click on www.comodogroup.com/secure-email to keep your emails confidential with a complementary FREE personal Secure Email CertificateArticle: 54639
Hi Fellows, : I am experiencing following error in my make file which is using path : to XST tools. Actually this make file was using path to FST ( FPGA : Synthesis Tools ) before and now I want to compile using (Xilinx : Synthsis Tools). Can anybody give me the web link for more information : on how to make Makefile using XST or any information how to get rid of : this error. I tried different Options but it didn't work. : Error: : Error Number (1): : c:\xilinx\bin\nt\xst.exe -ofn xilinx -f fe_run.fst : ERROR:Portability:90 - Command line error: Switch "-force" is not : allowed. : Error Number (2): : c:\xilinx\bin\nt\xst.exe -ofn xilinx -f fe_run.fst : ERROR:Portability:90 - Command line error: Switch "-force" is not : allowed.Article: 54640
Hello folks, As FPGAs find their way into more and more devices, I know the big guys (X,A etc.) are always striving to reduce power consumption as much as possible with a view to getting big devices into consumer mobile technology. I have been looking at various papers that describe various techniques (glitch reduction etc.) for designing the circuit with reduced power in mind and a question came to mind: Is there some "holy grail(s)" of power consumption reduction that the manufacturers are still chasing that will dwarf any gains to be had through careful circuit design? Thanks for your time, Ken -- To reply by email, please remove the _MENOWANTSPAM from my email address.Article: 54641
On 6 Apr 2003, TI wrote:
> Is there some type of standard test other than hobby projects
> that could serve to test for example circuit designs ability or
> sales/marketing skill prior to taking a job?
Chances are that an appropriate aptitude test will show that you are
a little more likely to succeed at one or the other.
Check out the psychological tests, etc.
I recall reading about a study done at some U.S. university. I can't
remember the exact numbers (from the late '60s), but they ran something
like this, for the time to solve a standard wooden interlocking puzzle:
Time: Group:
2 hr. Average University student
30 min. Engineering student
20 min. Successful engineer, as defined by earning $50,000+ USD/yr
2 1/2 hr. Current justices of U.S, Supreme Court, with the exception
of Chief Justice Earl Warren, who gave up after nine hours.
The point is, some people are better at some things than others. Warren
had a mind like a steel trap, when it came to legal precedent. He could
often correct lawyers who mis-quoted a precedent - much to their chagrin.
He had a good "linear" memory, like the aboriginal "rememberers" and the
bards and minstrels of old. These people can accurately recite all the
"begats" of Deuteronomy, or 1,000 line sagas, if they put their minds to
it. Often, however, a relatively simple problem in three dimensions will
stump them.
Conversely, you may be able to solve that puzzle in under 10 min., but not
be able to remember if you read "See Spot Run" in grade school. If you
have several such abilities, you may be bucking for genius.
There are other mental abilities which can be measured. Some are more
easily learned, like simple addition; and others more difficult, like
extracting fifth roots in your head. Some just seem to be there, and
intensive training may only make the non-adept slightly better than
what he was before: for example eidetic memory, and perfect pitch.
Someone with eidetic memory, once he has read a book, can, in his mind's
eye, open that book and start reading a page - just as surely as if the
book was in front of him.
Someone with perfect pitch can "hear" the beat between a slightly
out-of-tune piano and what the note should be.
Children can learn a second language fluently - sometimes in a matter of
weeks - while some adults struggle for most of their life, just trying to
be understood.
Have you ever heard of "the cocktail party factor"? Experienced diplomats
can listen to several conversations - perhaps as many as twenty people
talking in three or four different languages at once. Or watched an
experienced elected politician "work the room"?
Boyd Ramsay
cx555@torfree.net
Article: 54642> Hi. > > What's the position in writing an well-established type of CPU core (like a > Z80) and selling it? That depends on patents that apply, and how you got the info. > Would I have to pay royalties to anyone? That also depends. See te above. IgmarArticle: 54643
Ken wrote: > Hello folks, > > As FPGAs find their way into more and more devices, I know the big guys (X,A > etc.) are always striving to reduce power consumption as much as possible > with a view to getting big devices into consumer mobile technology. > > I have been looking at various papers that describe various techniques > (glitch reduction etc.) for designing the circuit with reduced power in mind > and a question came to mind: > > Is there some "holy grail(s)" of power consumption reduction that the > manufacturers are still chasing that will dwarf any gains to be had through > careful circuit design? IMO, both efforts complement each other. The die becomes smaller, the gate capacitances decrease, the idle current decreases for a fixed frequency, the core voltage decreases, there are multiple clock regions. All these gains can be offset by increasing the clock frequency and increasing the used cell count to cram more features into one chip. Of course the advances in chip technology offset all design tricks in the long run - but can you wait till then ? The same applies when asking the question about Compiler or ASM for embedded CPUs. The answer is also :time to market, immediate cost, serviceability. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 54644
I'm trying to get nios-build to run under Solaris (using bash).
uname -a
SunOS scifire 5.9 Generic_112233-03 sun4u sparc SUNW,Sun-Fire
export sopc_builder=/net/sciraid2/raid2/home/local-solaris-sun4/altera/nios-3.0
. $sopc_builder/bin/nios_bash
This results in
------------------------------------------------
Welcome To Altera SOPC Builder
Version 2.8, Built Mon Jan 6 18:04:16 2003
Example nios designs can be
found in
/net/sciraid2/raid2/home/local-solaris-sun4/altera/nios-3.0/examples
Try:
nios-build hello_world.c
nios-run hello_world.srec
within one of the sdk subdirectories.
------------------------------------------------
bash: cygpath.exe: command not found
Why does the Solaris distribution try to execute something which
appears to be a windows program?
When I try to build an srec file I get
[SOPC Builder]$ nios-build hello_world.c
Can't use string ("-1") as a HASH ref while "strict refs" in use at - line 478.
Any ideas? Anybody else using SOPC under Solaris? Does anybody have a
clean Makefile to do the build rather than all the Perl stuff?
Petter
--
________________________________________________________________________
Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petter
Article: 54645Hi fellows, I am getting following error when I tried to make files using command line window. And tell me one thing if I am using (@ echo )statement in my make file then do I need echo utility or not as in UNIX. I have just make executable file and nothing else. Error: ******************************************************************************** c:\xilinx\bin\xst.exe -oem xilinx -f fe_run.fst process_begin: CreateProcess((null), c:\xilinx\bin\xst.exe -oem xilinx -f fe_run .fst, ...) failed. make (e=2): The system cannot find the file specified. make: *** [ana] Error 2 ******************************************************************************* In this error system is unable to find the file fe_run.fst which is not the case, this file is already there, but I don't why this error kept appearing. Regards KhanArticle: 54646
Hi fellows. I want to make file using command line. thats why lookig to make makefile for that purpose. As I didn't get FPGA express thats why I am using XST.exe. But te problem is " Errors". Do you think I need to change the command line options so as to make it compatible with xst because my makefile was using FST complier as target FEXP. Because what I did that I copy HW2_TPLT as a different name in my c directory. Then I installed make utility and then I changed the path to FEXP = c:\xilinx\bin\xst.exe which is where my xst.exe is located. Now, the following errors were there when I started making the files. Before I show you the errors, I replace -oem opiton to -ofn because it was appearing on the screen that -oem option is not allowed. Errors: : Error Number (1): : c:\xilinx\bin\nt\xst.exe -ofn xilinx -f fe_run.fst : ERROR:Portability:90 - Command line error: Switch "-force" is not : allowed. : Error Number (2): : c:\xilinx\bin\nt\xst.exe -ofn xilinx -f fe_run.fst : ERROR:Portability:90 - Command line error: Switch "-force" is not : allowed. ----------------------------------------------------------------------------------------- Now, then what i did I deleted all -force -progress or ect options in fe_run.fst and fe_tmplt.fst as required by the errors appearing on the screen. But it didn't work. Then delete all my files and start the process again by copying your original files from my back up and after giving path in makefile, when I issued the command on DOS prompt I recieved following error. Error: c:\xilinx\bin\xst.exe -ofn xilinx -f fe_run.fst process_begin: CreateProcess((null), c:\xilinx\bin\xst.exe -ofn xilinx -f fe_run .fst, ...) failed. make (e=2): The system cannot find the file specified. make: *** [ana] Error 2 --------------------------------------------------------------------------------------------- The file is there, but i don't know why this message is appearing !!!!! I have studied documents on how to make makefiles but thats all about using FST not XST . I am sure there wil be a difference and I have to make changes accornigdly but I am unable to find any document on web on how to make makefile using xst compiler. Or may be I am not looking in proper perspective. Thanking you in advance. M.K.KhanArticle: 54647
more or less. WIth the 4.2 and later version router, even that may not be
enough. The new router is lazy in that it only improves routing to meet the
slack on all paths. The result is less than optimal routing in which every path
becomes the critical path. If you are pushing the timing at all, a macro can
route with wonderful results in isolation but then when placed in the circuit
might fail miserably with the exact same timespecs. Worse yet, the same macro
instantiated multiple times will make timing on some instances and not on
others. This is new behavior starting with the 4.x tools (not so new anymore).
Please complain to Xilinx, they don't seem to see this as a problem...it was
changed to improve the time to a routed solution but as a result the quality of
route has plummeted. Altera, take notes so that you don't do the same slack
based routing mistake.
David wrote:
> Hi,
> I'd like to know if it is possible to know the speed of a particular core in
> Xilinx core generator. For example, I want to create a combinational
> multiplier. How do I know if it will be fast enough for my design? Even if I
> choose the 'pipelined' option, how do I know the fastest clock rate possible
> for a given Fpga? Do I always have to make a project in ISE and test it
> myself with post place and route simulation?
>
> Thanks
> David
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 54648
Yes, the transmission is sensitive to the timing of the start bit. The start bit
detection can be made more robust by resetting the count clock counter whenever the
input is a '1', that way it ignores false edges, but it also is not foolproof. If
there is a stop bit, the state machine has to wait for the stop bit before returning
to the idle state so that it doesn't trip the start again in the case where the last
data bit is a '0'. In cases where there is no stop bit, you still need to delay a
bit time before looking again for the start bit to avoid capturing the tail of the
last bit.
Rene Tschaggelar wrote:
> Thanks.
> That was interesting.
> This makes the whole byte transmission very sensitive to the
> startbit edge then. And it also illuminates the requirement
> to have he idle level at the stop level.
> There are some RS485 implementations that cut the stop bit off.
> Such as using the TxBufferEmpty to reload the data
> and using the TxShiftEmpty for the disabling of the driver.
> Unless a timer is used to add the stopbit, it will be cut off.
>
> Rene
>
> Ray Andraka wrote:
> > Not quite. A UART typically samples the start bit at 16x clock, then from the
> > estimated center of the start bit (determined by a count of 8 clocks from when
> > the start goes active), the rest of the bits are simply sampled at the center of
> > the bit times, ie multiples of 16 clocks from the center of the start bit. It
> > can be accomplished with a 4 bit counter for the bit timing (preload with 8), a
> > bit counter, and a shift register with just enough bits to hold the intended
> > data bits, and parity if desired. The shift register gets enabled by the bit
> > counter terminal count. A simple state machine to hold the bit counter reset
> > (to 8) until the start bit is detected and again after the stop bit rounds the
> > design out. Unless you have a 16x recieve clock available, you'll also need an
> > accumulator to generate the 16x UART clock from your system clock. All you need
> > then, is an 8 bit shift register, a mod 16 counter, a 4bit counter and a few
> > extra flops for the state machine. Plus an accumulator if you need to generate
> > the 16 x clock.
>
> [ snip ]
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 54649Makes sense. Usual UARTS never offered the option of not having a stopbit, AFAIR. Rene Ray Andraka wrote: > Yes, the transmission is sensitive to the timing of the start bit. The start bit > detection can be made more robust by resetting the count clock counter whenever the > input is a '1', that way it ignores false edges, but it also is not foolproof. If > there is a stop bit, the state machine has to wait for the stop bit before returning > to the idle state so that it doesn't trip the start again in the case where the last > data bit is a '0'. In cases where there is no stop bit, you still need to delay a > bit time before looking again for the start bit to avoid capturing the tail of the > last bit. > > Rene Tschaggelar wrote: > >>Thanks. >>That was interesting. >>This makes the whole byte transmission very sensitive to the >>startbit edge then. And it also illuminates the requirement >>to have he idle level at the stop level. >>There are some RS485 implementations that cut the stop bit off. >>Such as using the TxBufferEmpty to reload the data >>and using the TxShiftEmpty for the disabling of the driver. >>Unless a timer is used to add the stopbit, it will be cut off. >> >>Rene >> >>Ray Andraka wrote: >> >>>Not quite. A UART typically samples the start bit at 16x clock, then from the >>>estimated center of the start bit (determined by a count of 8 clocks from when >>>the start goes active), the rest of the bits are simply sampled at the center of >>>the bit times, ie multiples of 16 clocks from the center of the start bit. It >>>can be accomplished with a 4 bit counter for the bit timing (preload with 8), a >>>bit counter, and a shift register with just enough bits to hold the intended >>>data bits, and parity if desired. The shift register gets enabled by the bit >>>counter terminal count. A simple state machine to hold the bit counter reset >>>(to 8) until the start bit is detected and again after the stop bit rounds the >>>design out. Unless you have a 16x recieve clock available, you'll also need an >>>accumulator to generate the 16x UART clock from your system clock. All you need >>>then, is an 8 bit shift register, a mod 16 counter, a 4bit counter and a few >>>extra flops for the state machine. Plus an accumulator if you need to generate >>>the 16 x clock. >> >>[ snip ]
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z