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> One other neat thing is that you can access any unused NV memory on the EPCS > device from your design. You can use this as storage for a Nios processor, > or whatever else you want. Can you tell me more about this? I could not find any information how to program the EPCS without Nios. That's the reason I use 'normal' Flash (AMD) with a small PLD (7064) for configuration data and general mass storage for an application on my board. I program this Flash from the FPGA. This would be the preferred way with the EPCS. I don't like two ByteBlaster connectors on the board. Martin -------------------------------------------------------- JOP - a Java Processor core for FPGAs now on Cyclone: http://www.jopdesign.com/cyclone/Article: 54401
> I've been playing with my Altera Stratix NIOS Developer Board and it's > really neat to write the configuration to the AMD FLASH using tftp > from my Linux machine :-) It only takes a second or so to upload the > hexout file. That's the same way I do with my ACEX/Cyclone boards. If you have a working Ethernet connection with your FPGA it's really more fun. But I'm using Windows and had to write a few lines of Java for the tftp (For interest send me a mail). Martin -------------------------------------------------------- JOP - a Java Processor core for FPGAs now on Cyclone: http://www.jopdesign.com/cyclone/Article: 54402
Hi, Can anyone out there confirm that it is possible to use ST-Micros serial SPI interface flash for active serial configuration of Cyclone Devices? They are a lot cheaper than alternatives as far as I can see. Cheers, ChrisArticle: 54403
"Martin Schoeberl" <martin.schoeberl@chello.at> writes: > Ethernet connection with your FPGA it's really more fun. But I'm using > Windows and had to write a few lines of Java for the tftp (For interest send > me a mail). Under Linux atftp-0.6 worked right out of the box... Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 54404
"Martin Schoeberl" <martin.schoeberl@chello.at> writes: > > One other neat thing is that you can access any unused NV memory on the > EPCS > > device from your design. You can use this as storage for a Nios > processor, > > or whatever else you want. > > Can you tell me more about this? If memory serves me right... There was a post in this group not too long ago. A designer was using the EPCS both as config memory for his FPGA as well as program storage for a DSP processor. The programming was done with the ByteBlaster though. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 54405
Hi my name is Fabrizio and I'm student. I must implementation standard parallel port (slave) ieee1284 on FPGA. someone can gives some idea and to suggest to me some interesting web site one to me to consult? ThanksArticle: 54406
The SOPC Builder is not officially supported under Linux yet. However, I can run the Java files distributed with the Solaris release under Linux (IBM jre 2.13). But I get a message saying that SOPC Builder requires an open Quartus II project. Is there a way to launch the SOPC Builder from within Quartus II or trick it to communicate with the Quartus II process? Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 54407
> Hi, > khimbittle@cliftonREMOVEsystems.com (Khim Bittle) wrote: > > hello folks ... while tooling around the arrow site this evening > > doing some price comparisons ... I noticed that altera has million > > gate plus FPGA's that are priced in the $2000-4000 range , holly geeze > > 2k$ is a lot for doing mass articles like TV or DVD, but it is no > problem for complex systems which will be delivered only a few times. > In earlier days you would have produced an ASIC, if your system needs > an FPGA >1k$, nowadays there are people thinking its cheaper to spend > 2k$ for each selled product right after contract signing, then > spending once 1M$ and hopping that you sell more then 500 pieces to > reach break-even. Even if the market seems to be big enough to sell a > lot more then 1000 pieces over the years. I know when I first joined Altera I too couldn't fatham what could justify a $1k+ FPGA! Communications, which used to be the lion share of our revenues in the boom-times, is a prime example. Sure, you can't put a $1000 FPGA in a $500 product. But you think of the boxes sitting in the telco office that do long-distance communications, or DSLAMs (the box you connect to with your cable modem) or base stations for wireless communications, and now you're talking about a box that will cost in the 10's or 100's of thousands of dollars, and only sell a few 1000 if you're lucky. Other examples would be big servers (like EMC storage boxes) and routers ($100K+ Cisco boxes). That's the key to the FPGA business model... though the per unit costs of FPGAs are higher than ASICs, the fixed cost of developing is much lower. The simple way of looking at it is that mask costs for an ASIC can be ~$1 million these days, so you need to sell 1000+ units to break-even vs. using a $1000 FPGA. But the break-even point is probably much higher than that (say, 10x?) once you factor in time-to-market, risk, engineering time (you need more, and generally higher-skilled designers in order to get an ASIC out the door). And you have to consider the probability of failure of your chip and of your product. If your chance of having first silicon working is say 80% (random number), then that increases the effective one-time cost of ASIC by 25%, since you may need to do two spins of the mask. And the real costs are much higher because of the opportunity cost and time-to-market losses of having to delay your product by a couple months. Also, everyone *thinks* their product is going to sell a lot, but the reality is for every successful product you make, you'll have a number of unsuccessful products that won't generate enough salaes to pay for their ASIC development costs. So if you look at your break-even point across all designs you'll make over the life-time of your company, it may be even higher... Low-cost FPGAs can work their way into cheap boxes. At $4 or so, a Cyclone EP1C3 device will be cost-competitive with ASICs even into the 100,000's of units. And for those people who go with a huge/expensive FPGA and then find that their volumes are picking up, they can move to an ASIC. Even better, Altera offers its HardCopy program, which basically gives you a drop-in replacement for your FPGA at a much reduced cost. It's a mask-programmed gate array product that gives up to 80% cost reduction, but you have to pay an up-front NRE cost. We guarentee the performance and timing, so there's much less work for the customer than with a true ASIC conversion, and all the IP is the same (PLLs, IOs, memories, etc.) so interoperability and system-level testing is more likely to go smoothly. And it only takes ~8 weeks from first commitment to receive prototype units. Regards, Paul LeventisArticle: 54408
Paul Leventis napisal(a): >Here's an alternative solution :-) For future projects, try using Altera's >Cyclone product. It's designed to work with the EPCS1 and EPCS4 products -- >they are low-cost (as you point out) and low-footprint (8-pin package). >About as easy as it goes for configuration. Does EPCS1 work with EPF10k or ACEX family? -- Pozdrowienia, Marcin E. Hamerla "Every day I make the world a little bit worse."Article: 54409
Marcin, > Does EPCS1 work with EPF10k or ACEX family? The EPCS devices require an FPGA supporting active serial configuration, which is a new configuration mode offered only on the Cyclone family. Regards, Paul Leventis Altera Corp.Article: 54410
Tan Peng Khiang wrote: > > Laurent Gauch, Amontec wrote: > > > > Use chipscope to make sure about the mapping of your dual FFD and your > > output, Your trouble can be come from a different P&R of your output. > > > > Let me know, I am interested in this issue. > > > > Laurent Gauch > > www.amontec.com > > > > Tan Peng Khiang wrote: > > > > > Hello , recently i did a test on the coolrunner 2 , by having all ones > > > on the output when rising clock input is one and zeros when falling > > > clock input , i used the coolrunner2 's dualedge feature. > > > > > > The problem : i notice that all the output do not fall at the same time > > > , some outputs do match , but others don't match. > > > > > > Oscilloscope set to 1ns time step > > > Output as below: > > > > > > ----\ > > > 1 \ > > > \ > > > -------------------------- > > > ----\ > > > 2 \ > > > \ -------------------------- > > > > > > --------\ > > > 3->4 \ > > > \----------------------- > > > > > > ----\ > > > 5->9 \ > > > \ -------------------------- > > > > > > ---------\ > > > 10->16 \ > > > \ --------------------- > > > > > > It seems there is a difference in ralling time of difference output , is > > > there any ?? or is it a scope problem. > > > > > > Thanks in advance > > Thanks Laurent , i will try it out and keep you inform. > > Thanks for reply. Hello , laurent , sorry no CHIPSCOPE , but anyhow , the difference in fall time , i don't think i will be able to fix it. ThanksArticle: 54411
Paul, Not to leave this unbalanced, so I have two points: 1) For the first time in history IBM announced that "ASIC's are NOT Dead, yet" in EE Time Online yesterday. What an amazing article! Think about it....they are mounting a defense against FPGAs? http://www.eedesign.com/story/OEG20030409S0025 Maybe FPGAs are just now to enter the mainstream? 2) Spartan was the first "low cost" FPGA, and still has the lead today for price/IOs/gates. With the recent announcement of the ES shipment of 90nm, we will have the price/IOs/gates leadership tomorrow, too. Austin Paul Leventis wrote: > > Hi, > > khimbittle@cliftonREMOVEsystems.com (Khim Bittle) wrote: > > > hello folks ... while tooling around the arrow site this evening > > > doing some price comparisons ... I noticed that altera has million > > > gate plus FPGA's that are priced in the $2000-4000 range , holly geeze > > > > 2k$ is a lot for doing mass articles like TV or DVD, but it is no > > problem for complex systems which will be delivered only a few times. > > In earlier days you would have produced an ASIC, if your system needs > > an FPGA >1k$, nowadays there are people thinking its cheaper to spend > > 2k$ for each selled product right after contract signing, then > > spending once 1M$ and hopping that you sell more then 500 pieces to > > reach break-even. Even if the market seems to be big enough to sell a > > lot more then 1000 pieces over the years. > > I know when I first joined Altera I too couldn't fatham what could justify a > $1k+ FPGA! > > Communications, which used to be the lion share of our revenues in the > boom-times, is a prime example. Sure, you can't put a $1000 FPGA in a $500 > product. But you think of the boxes sitting in the telco office that do > long-distance communications, or DSLAMs (the box you connect to with your > cable modem) or base stations for wireless communications, and now you're > talking about a box that will cost in the 10's or 100's of thousands of > dollars, and only sell a few 1000 if you're lucky. Other examples would be > big servers (like EMC storage boxes) and routers ($100K+ Cisco boxes). > > That's the key to the FPGA business model... though the per unit costs of > FPGAs are higher than ASICs, the fixed cost of developing is much lower. > The simple way of looking at it is that mask costs for an ASIC can be ~$1 > million these days, so you need to sell 1000+ units to break-even vs. using > a $1000 FPGA. > > But the break-even point is probably much higher than that (say, 10x?) once > you factor in time-to-market, risk, engineering time (you need more, and > generally higher-skilled designers in order to get an ASIC out the door). > And you have to consider the probability of failure of your chip and of your > product. If your chance of having first silicon working is say 80% (random > number), then that increases the effective one-time cost of ASIC by 25%, > since you may need to do two spins of the mask. And the real costs are much > higher because of the opportunity cost and time-to-market losses of having > to delay your product by a couple months. > > Also, everyone *thinks* their product is going to sell a lot, but the > reality is for every successful product you make, you'll have a number of > unsuccessful products that won't generate enough salaes to pay for their > ASIC development costs. So if you look at your break-even point across all > designs you'll make over the life-time of your company, it may be even > higher... > > Low-cost FPGAs can work their way into cheap boxes. At $4 or so, a Cyclone > EP1C3 device will be cost-competitive with ASICs even into the 100,000's of > units. > > And for those people who go with a huge/expensive FPGA and then find that > their volumes are picking up, they can move to an ASIC. Even better, Altera > offers its HardCopy program, which basically gives you a drop-in replacement > for your FPGA at a much reduced cost. It's a mask-programmed gate array > product that gives up to 80% cost reduction, but you have to pay an up-front > NRE cost. We guarentee the performance and timing, so there's much less > work for the customer than with a true ASIC conversion, and all the IP is > the same (PLLs, IOs, memories, etc.) so interoperability and system-level > testing is more likely to go smoothly. And it only takes ~8 weeks from > first commitment to receive prototype units. > > Regards, > > Paul LeventisArticle: 54412
Hi folks... It's been a long time since I've posted here. Seems like forever. I'm having a bear of a time trying to get a particular design to map IOB FFs to registered outputs and was hoping someone here could help. I've read several items found in Xilinx answers and technical documentation and it's not working. I would prefer not to explicitly instantiate the IOB FF in my Verilog, but it may be the next step. I've turned on IOB FF mapping in XST (it's on auto by default). Essentially, my code is: ----- reg [7:0] something, other; wire [7:0] outputsomethingorother; reg [7:0] outputbus; assign outputsomethingorother = which ? something : other; always @(posedge clk) begin outputbus <= outputsomethingorother; end ----- 'something' and 'other' should become internal CLB FFs. 'somethingorother' should become the output of a CLB MUX. 'outputbus' should become a bunch of IOB FFs, right? JakeArticle: 54413
Allan Herriman <allan_herriman.hates.spam@agilent.com> wrote in message news:<gn2q8v4t7vjqjaha7bgnrahikur6bq6fqs@4ax.com>... > On Thu, 03 Apr 2003 09:57:06 -0800, Mike Treseler <tres@fluke.com> > wrote: > > >Allan Herriman wrote: > >> Hi, > >> > >> Does anyone have experience with VHDL tool support for bit vectors > >> (or vectors of other types) that have lots of elements? > >> > >> I'm thinking of using one for a generic or a constant (not a signal) > >> to hold the initialisation value for a Xilinx block ram (18432 bits). > >> > >> I'm interested in both simulation and synthesis. > > > > > >Initialization for a block RAM occurs when the binary > >image is loaded into into the device. The only way to > >to control this from VHDL source is with device > >specific instances and attributes or by inferring > >a ROM by declaring a constant array of vectors > >of an appropriate size. > > Not quite the "only way". In simulation, one needs to use the INIT_XX > generics on the block rams. The attributes are ignored. > > >Sim and synth tools can handle vector widths > >of several hundred thousand bits, up to natural'high. > > Somehow I can't see any tool working with a vector length of 2 ** 31 - > 1. (At least not under versions of Windows that have problems > allocating more than 2Gbyte of ram to a process.) > > I have seen std_logic_vectors of several hundred thousand bits used in > Modelsim quite successfully. > > Does anyone have any other practical experience? I was rather hoping > someone from Synplicity would reply. I know they read this news > group. > > Thanks, > Allan. Hi Allan, I use a package that defines a constant of a subtype made of an array of bitvectors, and strings. This is then passed in to the ram/rom block model as INIT_XX values for synthesis and as generics for simulation, compiled with Synplify_pro and simed with Modelsim 5.6e. I've used this for RAM/ROM values up to 64Kx32 in a VirtexII 6000 device. The only catch is that I have an issue where I have to run a perl script to fix the line length issue in the .edf file created by synplify, (500 char line length). It works fine though. If this is what you are trying to do, let me know, I can send you an example.Article: 54414
What's up with that? I tried to install Webpack last night and it didn't work. A careful read of the web site says it's only supported on Win2000 and XP. This is a serious drawback from my customers and I. Does anyone have any workaround for this problems? Has Win98 support been dropped permanently or is this just a bug?Article: 54415
Fabrizio Mezzetti wrote: > Hi my name is Fabrizio and I'm student. I must implementation standard > parallel port (slave) ieee1284 on FPGA. > someone can gives some idea and to suggest to me some interesting web site > one to me to consult? Thanks > > for intro check - http://www.amontec.com/ieee1284.shtml for 1284 info - http://www.amontec.com/chameleon.shtml for 1284 applications Our chameleon POD can be a good entry point for you. We will add only our EPP and ECP slave core, but this will be free and we are very busy now with all our commercial part. Chameleon POD is based on a Xilinx coolrunner XPLA device on 1284. We are able to config and to dialog (in SPP, EPP, ECP mode) from the parallel port of your PC. Chameleon POD is coming with free configurations: RAVEN JTAG EMULATOR WIGGLER JTAG EMULATOR XILINX PARALLELCABLEIV ALTERA BYTEBLASTER ACTIVE I2C ACTIVE ISP ACTIVE CLOCK GEN (32 MHZ to 125KHz) ACTIVE DDS (Direct Digital Synthesizer) ACTIVE PSK GENERATOR ALL OF THIS FOR ONLY $149.- Regards, LaurentArticle: 54416
In article <Uhdla.24800$iy5.696256@twister2.libero.it>,
"Fabrizio Mezzetti" <fmezzo@libero.it> writes:
|> Hi my name is Fabrizio and I'm student. I must implementation standard
|> parallel port (slave) ieee1284 on FPGA.
|> someone can gives some idea and to suggest to me some interesting web site
|> one to me to consult? Thanks
http://www.beyondlogic.org/epp/epp.htm
--
Georg Acher, acher@in.tum.de
http://wwwbode.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 54417Hi, Are there any reliable Verilog-to-VHDL or VHDL-to-Verilog converters in the market ? Thanks, PrashantArticle: 54418
Jim Stewart wrote: > > What's up with that? I tried to install > Webpack last night and it didn't work. A > careful read of the web site says it's only > supported on Win2000 and XP. This is a > serious drawback from my customers and I. > > Does anyone have any workaround for this > problems? Has Win98 support been dropped > permanently or is this just a bug? If you read the requirements for any of the current Xilinx development products you will find that they only support two versions of Windows, 2000 and XP. This is not a bug and I suspect the only thing about it that is not permanent is Win2000 support. My guess is that they will drop that in the next release or two. At that point I expect I will use something else for FPGA development. I am a long way from moving to XP. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54419
On 10 Apr 2003 09:18:38 -0700, emil.isaakian@l-3com.com (Emil Isaakian) wrote: >Allan Herriman <allan_herriman.hates.spam@agilent.com> wrote in message news:<gn2q8v4t7vjqjaha7bgnrahikur6bq6fqs@4ax.com>... >> On Thu, 03 Apr 2003 09:57:06 -0800, Mike Treseler <tres@fluke.com> >> wrote: >> >> >Allan Herriman wrote: >> >> Hi, >> >> >> >> Does anyone have experience with VHDL tool support for bit vectors >> >> (or vectors of other types) that have lots of elements? >> >> >> >> I'm thinking of using one for a generic or a constant (not a signal) >> >> to hold the initialisation value for a Xilinx block ram (18432 bits). >> >> >> >> I'm interested in both simulation and synthesis. >> > >> > >> >Initialization for a block RAM occurs when the binary >> >image is loaded into into the device. The only way to >> >to control this from VHDL source is with device >> >specific instances and attributes or by inferring >> >a ROM by declaring a constant array of vectors >> >of an appropriate size. >> >> Not quite the "only way". In simulation, one needs to use the INIT_XX >> generics on the block rams. The attributes are ignored. >> >> >Sim and synth tools can handle vector widths >> >of several hundred thousand bits, up to natural'high. >> >> Somehow I can't see any tool working with a vector length of 2 ** 31 - >> 1. (At least not under versions of Windows that have problems >> allocating more than 2Gbyte of ram to a process.) >> >> I have seen std_logic_vectors of several hundred thousand bits used in >> Modelsim quite successfully. >> >> Does anyone have any other practical experience? I was rather hoping >> someone from Synplicity would reply. I know they read this news >> group. >> >> Thanks, >> Allan. > >Hi Allan, > I use a package that defines a constant of a subtype made of an array >of bitvectors, and strings. This is then passed in to the ram/rom >block model as INIT_XX values for synthesis and as generics for >simulation, compiled with Synplify_pro and simed with Modelsim 5.6e. >I've used this for RAM/ROM values up to 64Kx32 in a VirtexII 6000 >device. The only catch is that I have an issue where I have to run a >perl script to fix the line length issue in the .edf file created by >synplify, (500 char line length). It works fine though. If this is >what you are trying to do, let me know, I can send you an example. That's sounds similar to what I'm doing. I never instantiate "bare" block rams. Instead, I always instantiate them via a wrapper component. The wrapper takes generics to indicate the desired width of the address and data buses, and the fpga family (Virtex-E, Virtex-2, etc.), and it works out the most efficient way to achieve the result. The wrapper also contains an optional simulation model that simulates about 10 times faster than the slow slow slow unisim components. I guess you could think about it as a coregen replacement, but faster, and with much better integration into my tool flow. I'm in the process of adding a generic to the wrapper that will allow me to initialise the block rams. The init generic is a single bit_vector that describes the entire memory array. I have written code that turns this generic into generics and attributes for the individual block rams. This is based on code I wrote a few years ago, and works well. I am having a few problems with Synp... uh, a popular synthesis tool though. It uses about 700Mbyte (before my laptop crashes) during compilation / elaboration on a trivial test design that instantiates 3 ramb4 components, although it does eventually produce the correct result if I run it on a machine with a few Gbytes of ram. A version of the code without the init generics uses much less ram and compiles much faster. I don't see this problem with other tools. Regards, AllanArticle: 54420
if you start project navigator with _pn.exe, direct from ..Xilinx\bin\nt it will work on W98 (xst,map, par are working impact wont with wdm driver, use old .vxd), make a shortcut on the desktop. "Jim Stewart" <jstewart@jkmicro.com> schrieb im Newsbeitrag news:99E62C824CD7FE6B.8A8A8441CF02F9C1.08E80CC2EC4B22E3@lp.airnews.net... > What's up with that? I tried to install > Webpack last night and it didn't work. A > careful read of the web site says it's only > supported on Win2000 and XP. This is a > serious drawback from my customers and I. > > Does anyone have any workaround for this > problems? Has Win98 support been dropped > permanently or is this just a bug? >Article: 54421
I popped an email off to the compiler folks here at Synplicity about the vector lengths. They don't see a problem with large arrays such as your 18432 bits for a block ram or more bits for initialization of an array of block rams. If you have seen a problem then please let us know. - Ken Allan Herriman wrote: > On Thu, 03 Apr 2003 09:57:06 -0800, Mike Treseler <tres@fluke.com> > wrote: > > >>Allan Herriman wrote: >> >>>Hi, >>> >>>Does anyone have experience with VHDL tool support for bit vectors >>>(or vectors of other types) that have lots of elements? >>> >>>I'm thinking of using one for a generic or a constant (not a signal) >>>to hold the initialisation value for a Xilinx block ram (18432 bits). >>> >>>I'm interested in both simulation and synthesis. >>> >> >>Initialization for a block RAM occurs when the binary >>image is loaded into into the device. The only way to >>to control this from VHDL source is with device >>specific instances and attributes or by inferring >>a ROM by declaring a constant array of vectors >>of an appropriate size. >> > > Not quite the "only way". In simulation, one needs to use the INIT_XX > generics on the block rams. The attributes are ignored. > > >>Sim and synth tools can handle vector widths >>of several hundred thousand bits, up to natural'high. >> > > Somehow I can't see any tool working with a vector length of 2 ** 31 - > 1. (At least not under versions of Windows that have problems > allocating more than 2Gbyte of ram to a process.) > > I have seen std_logic_vectors of several hundred thousand bits used in > Modelsim quite successfully. > > Does anyone have any other practical experience? I was rather hoping > someone from Synplicity would reply. I know they read this news > group. > > Thanks, > Allan. >Article: 54422
In my project, I instanciated LUT1, CLKDLLs, BUFGs e IBUFs. After sinthesis, when I perform ngdbuild tool, it issues these errors: ERROR:NgdBuild:466 - input pad net 'clock_int' has illegal connection. Possible pins causing this are pin O on block clock_ibuf with type IBUF ERROR:NgdBuild:455 - logical net 'clock_int' has multiple drivers. The possible drivers causing this are pin O on block clock_ibuf with type IBUF, pin PAD on block clock_int with type PAD I don´t know what to do for solving these errors. Can someone help me? I appreciate any kind of help. Eduardo Wenzel Brião Catholic University of Rio Grande do Sul state - PUCRS Porto Alegre city BrazilArticle: 54423
Paul - thanks for the insights. FPGAs are definitely the order of the day....it will take time to give a run to the ASICs, but we'll get there.... To substantiate further, have a look at the Xilinx EasyPath solutions...what an innovative way to reduce cost upto 80% and at an MOQ at which no fab will talk to you.... http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=v2_easypath An interesting FPGA Vs ASIC cost analyzer is also available http://www.xilinx.com/products/virtex2/EasyPath/cost_analyzer.htm --Neeraj "Paul Leventis" <paul.leventis@utoronto.ca> wrote in message news:m5ela.2443$sI1.553@news01.bloor.is.net.cable.rogers.com... > > Hi, > > khimbittle@cliftonREMOVEsystems.com (Khim Bittle) wrote: > > > hello folks ... while tooling around the arrow site this evening > > > doing some price comparisons ... I noticed that altera has million > > > gate plus FPGA's that are priced in the $2000-4000 range , holly geeze > > > > 2k$ is a lot for doing mass articles like TV or DVD, but it is no > > problem for complex systems which will be delivered only a few times. > > In earlier days you would have produced an ASIC, if your system needs > > an FPGA >1k$, nowadays there are people thinking its cheaper to spend > > 2k$ for each selled product right after contract signing, then > > spending once 1M$ and hopping that you sell more then 500 pieces to > > reach break-even. Even if the market seems to be big enough to sell a > > lot more then 1000 pieces over the years. > > I know when I first joined Altera I too couldn't fatham what could justify a > $1k+ FPGA! > > Communications, which used to be the lion share of our revenues in the > boom-times, is a prime example. Sure, you can't put a $1000 FPGA in a $500 > product. But you think of the boxes sitting in the telco office that do > long-distance communications, or DSLAMs (the box you connect to with your > cable modem) or base stations for wireless communications, and now you're > talking about a box that will cost in the 10's or 100's of thousands of > dollars, and only sell a few 1000 if you're lucky. Other examples would be > big servers (like EMC storage boxes) and routers ($100K+ Cisco boxes). > > That's the key to the FPGA business model... though the per unit costs of > FPGAs are higher than ASICs, the fixed cost of developing is much lower. > The simple way of looking at it is that mask costs for an ASIC can be ~$1 > million these days, so you need to sell 1000+ units to break-even vs. using > a $1000 FPGA. > > But the break-even point is probably much higher than that (say, 10x?) once > you factor in time-to-market, risk, engineering time (you need more, and > generally higher-skilled designers in order to get an ASIC out the door). > And you have to consider the probability of failure of your chip and of your > product. If your chance of having first silicon working is say 80% (random > number), then that increases the effective one-time cost of ASIC by 25%, > since you may need to do two spins of the mask. And the real costs are much > higher because of the opportunity cost and time-to-market losses of having > to delay your product by a couple months. > > Also, everyone *thinks* their product is going to sell a lot, but the > reality is for every successful product you make, you'll have a number of > unsuccessful products that won't generate enough salaes to pay for their > ASIC development costs. So if you look at your break-even point across all > designs you'll make over the life-time of your company, it may be even > higher... > > Low-cost FPGAs can work their way into cheap boxes. At $4 or so, a Cyclone > EP1C3 device will be cost-competitive with ASICs even into the 100,000's of > units. > > And for those people who go with a huge/expensive FPGA and then find that > their volumes are picking up, they can move to an ASIC. Even better, Altera > offers its HardCopy program, which basically gives you a drop-in replacement > for your FPGA at a much reduced cost. It's a mask-programmed gate array > product that gives up to 80% cost reduction, but you have to pay an up-front > NRE cost. We guarentee the performance and timing, so there's much less > work for the customer than with a true ASIC conversion, and all the IP is > the same (PLLs, IOs, memories, etc.) so interoperability and system-level > testing is more likely to go smoothly. And it only takes ~8 weeks from > first commitment to receive prototype units. > > Regards, > > Paul Leventis > >Article: 54424
Jake Janovetz wrote: > Hi folks... > > It's been a long time since I've posted here. Seems like forever. > I'm having a bear of a time trying to get a particular design to map > IOB FFs to registered outputs and was hoping someone here could help. > > I've read several items found in Xilinx answers and technical > documentation and it's not working. I would prefer not to explicitly > instantiate the IOB FF in my Verilog, but it may be the next step. > I've turned on IOB FF mapping in XST (it's on auto by default). > Essentially, my code is: There are two places where the mapping has to be turned on. The first is in the synthesis properties, which you already have. The second is in the "Process Properties", where you need to select the tab "Map Properties". -- My real email is akamail.com@dclark (or something like that).
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