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Hello, In article <3E9B5930.D5C331BA@andraka>, ray@andraka says... > Not quite. A UART typically samples the start bit at 16x clock, then from the > estimated center of the start bit (determined by a count of 8 clocks from when > the start goes active), the rest of the bits are simply sampled at the center of > the bit times, ie multiples of 16 clocks from the center of the start bit. Is this the only technique used? Sorry if this seems naive, but I've frequently seen the term "vote logic" or "majority detector" used in conjunction with UARTs(even in the TI literature for the UART the OP mentioned). I was always under the impression that the bits are sampled at 16x and the bit is given the majority value. I guess this leads to another interesting question: Any easy way to do the majority detection logic, or is one forced to eat the logic needed for all the comparators? Regards, S.R.Article: 54651
invalid@invalid.com wrote: > Hello, > > In article <3E9B5930.D5C331BA@andraka>, ray@andraka says... > >>Not quite. A UART typically samples the start bit at 16x clock, then from the >>estimated center of the start bit (determined by a count of 8 clocks from when >>the start goes active), the rest of the bits are simply sampled at the center of >>the bit times, ie multiples of 16 clocks from the center of the start bit. > > > Is this the only technique used? Sorry if this seems naive, but I've > frequently seen the term "vote logic" or "majority detector" used in > conjunction with UARTs(even in the TI literature for the UART the OP > mentioned). I was always under the impression that the bits are sampled > at 16x and the bit is given the majority value. I was under the same impression (majority vote) after having read the description of the 8250 and/or 16550 about 15 years back. ReneArticle: 54652
KB, Have you ever pondered V= - L dI/dt? Think about it....what possible use is a package that has 1 volt of ground bounce when the Vccint is 1.2volts? It is one thing to read a data sheet and compare us with some other manufacturer. It is altogether another to realize that the ground bounce is going to be so bad that the design will not function. Lucky for you, we already thought of that (see xapp623). There is a reason the larger parts don't come in leaded pakages...... Of course, if you want to use every other IO pin as a ground pin (hey, where are all those IOs go?) then be my guest. Austin KB wrote: > On Mon, 14 Apr 2003 16:59:06 -0400, Theron Hicks > <hicksthe@egr.msu.edu> wrote: > > >Has anyone noticed that this part is available with LEGS? It appears > >that someone at Xilinx was listening to the request for non-BGA parts. > > > > Actually I was a little disappointed in this area. Only the XC3S50 / > 200 / 400 is available in the 208 pin pqfp .. the 2e took this package > up the 300 part so some improvement yes .. but the Cyclone EP1C12 is > available in a 240 pin pqfp ... 30+ more I/O pins, and the cyclone has > 12K registers , a bunch more than the new 400 part. my 2'c KBArticle: 54653
Thanks, Ray. I used the RLOCs and double-checked the routing to make sure the numbers were "smallest" and still found myself with almost no margin left over for input jitter tolerance. The Tcko and any of the Tceck or Tdick or Tsrck values along with the shortest net I could muster left the 1.8 ns for 1/4 clock at the hairy edge. I was hoping there was an innovative approach to avoiding the 1.8ns requirement for a 7.2 ns x1clk. - John_H Ray Andraka wrote: > John, You are right ot be concerned about skew between the 1x and 2x clocks. If > you control placement and are clever about getting direct flip-flop to flip-flop > connections you can manage to do what you are describing using a falling edge > sensitive FF in the 2x domain to capture the 1x clock, then take the output of > the falling edge FF and feed it to a rising edge FF in the 2x domain to time > align the resulting CE with the 2x clock rising edges. The CE is probably > inverted WRT to what you wanted at that point, in which case an additional > rising edge FF will put it right without adding any logic delays in the critical > timing around the neg edge FF. You'll need to use primitives with RLOCs on them > to keep the timing tight, and with v4.2 and later tools you need to make sure > you put the time constraints in for each connection in order to keep the router > honest (3.3 did a good job of finding the direct connect without having an > explicit time constraint). > > John_H wrote: > > >>Thanks for the message last week, Eric - my newsreader at work isn't >>100% and I had to read/respond at home. >> >>Your comment about only needing two flops is accurate as long as the >>designer can trust that the x1clk and x2clk domains will always work >>together as we'd expect where the rising edges are coincident. The >>reality is that those two edges may be separated by some 100s of ps >>since the clock net loading can be different between the two domains and >>input clock jitter to the DLL may translate to the two domains at >>different cycles. THe former problem is known, I'm only speculating on >>the latter. Bottom line: I can't depend on the two domains to play nice >>at the common rising edge, hense the nead to offset things by 1/4 the >>x1clk (or 1/2 th x2clk). >> >>Any further thoughts are appreciated. >> >>- John_H >> >>Eric Pearson wrote: >> >>>"John_H" <johnhandwork@mail.com> wrote in message >>>news:T9Hka.9$716.2363@news-west.eli.net... >>> >>> >>>>Has anyone figured out a nice, clean method to track which phase of a >>> >>>Xilinx >>> >>> >>>>DLL's 1x clock corresponds to a 2x clock cycle? One 2x rising edge >>>>corresponds to the 1x rising edge, the other 2x rising edge corresponds to >>>>the 1x falling edge. >>>> >>>>When I start getting up in frequencies, the ability to use the 1x clock >>> >>>and >>> >>> >>>>inverted 1x clock to generate two signals that I can XOR for a phase is >>>>compromised. It's not inherently safe to use the 1x edges and 2x rising >>>>edges as "effectively" the same edge due to clock skews and input jitter >>>>issues. Using the falling edge of the 2x clock to sample the 1x generated >>>>signals works, but at the 1/4 period timing budget is too tight at the >>>>frequencies I'm working. >>>> >>>>For those who are Verilog friendly, the code here shows how I would >>>>"normally" extract the phase without running a clock through a LUT. The >>>>"negedge x2clk" is where the timing gets tough since the Tcko+Tnet+Tick is >>> >>>a >>> >>> >>>>little over the 1/4 period of my x1clk. >>>> >>>>always @(posedge x1clk) posTog <= ~posTog; >>>>always @(negedge x1clk) negTog <= posTog; >>>>always @(negedge x2clk) rawPhase <= posTog ^ negTog; >>>>always @(posedge x2clk) phase <= rawPhase; >>>> >>>>Is there a cleaner way to figure out the which half of the x1clk I'm in? >>>> >>>>Thanks, >>>>- John_H >>>> >>>> >>> >>> >>>It really only takes 2 flops working on rising edge. >>> >>>always @(posedge x1clk) Toggle <= ~Toggle; >>>always @(posedge x2clk) Delayed <= Toggle; >>>assign Phase = DelTog ^ Tog; >>> >>>Eric >>> >>> >> > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 54654
Ray, The liklihood of flipping a FF is nil in the FPGA (or pretty near 0). In fact the logic of a customer design about 30X harder to upset that in an ASIC where everything is "optimal" (lowest loading, and fewest transistors). One big benefit of having all those "extra transistors" around. The memory cells that control the interconnect are the lightly loaded ones, and the smallest features. Those are the ones that get affected by soft errors (SEUs - cosmic rays). Buit it takes from 6 to 80 "hits" to change a customer design logic result! If you were to reload the configuration once a day, you also would prevent cumulative upsets, and reduce the probability of a customer logic upset even further. See the http://www.xilinx.com/support/techxclusives/1000-techX35.htm tech exclusive. Not only do we actually know how sensitive we are, we also know which bits are sensitive. And with Virtex II ICAP (internal configuration acess port) you can create a design to continually check itself (skipping columns with BRAM and LUT RAM/SRLs) and even check and correct itself. And, you don't have to ask: evaluation of 130 nm and 90nm is in progress, and we will have those results for those that need to know. You see, we have known about SEUs (SEEs, soft errors) for more than 10 years now, and we have taken all of this into account by design. By the way, what we are doing is so far up from all of the others that it is hard to breath at this altitude. Fact. The next lot of 100 goes to WMRC. Austin Ray Andraka wrote: > Then don't forget IOB failure due to abuse and/or ESD. Generally speaking, the guts of the FPGA are pretty > bulletproof. If you are operating at high altitude or in space, you'll get an occasional soft failure that clears > itself next time that flip-flop is toggled (note that if it is a configuration register the flipped bit is held > until the device is reconfigured). There are many papers on the subject in the proceedings from MAPLD over the > last several years. I've got one such paper dealing with detection of configuration upsets in SRAM FPGAs on my > website. > > naveen wrote: > > > hi, > > i meant all the list of the faults. doent matter if its before > > testing or after testing. > > i lnow some of them but iam writing a paper on "diagnosis and fault > > tolerence of FPGA's", i dont want to miss ne of them. > > thanks, > > naveen > > nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) wrote in message news:<b770oe$171v$1@agate.berkeley.edu>... > > > In article <b7f5eb6a.0304110842.4abb46a8@posting.google.com>, > > > naveen <cvmnk@yahoo.com> wrote: > > > >hi, > > > > can ne one lemme know all the different faults on FPGA, both > > > >interconect and logical faults, on Xilinx based FPGA's. > > > > thankin you in advance, > > > > > > What do you mean? Soft errors vs hard errors? From the fab (before > > > testing) or after testing? > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 54655
"Paul Baxter" <pauljnospambaxter@hotnospammail.com> wrote in message news:<3e9bd81b$0$11383$cc9e4d1f@news.dial.pipex.com>... > www.opencores.org is in the process of accepting a verilog to vhdl script > that converts a large synthesizable subset. Its open, of course, but you'll > have to keep at eye on the mailing list for details as I can't see it on the > web site yet. > > "Fernando" <fortizzz@hotmail.com> wrote in message > news:b650f553.0304140846.195a6d9a@posting.google.com... > > (In case you haven't seen it) you can try XHDL, I don't know about its > > reliability though. It didn't work very well for me. > > > > http://www.edadirect.com/products.html > > > > prashantj@usa.net (Prashant) wrote in message > news:<ea62e09.0304100920.25920bfe@posting.google.com>... > > > Hi, > > > Are there any reliable Verilog-to-VHDL or VHDL-to-Verilog converters in > the market ? > > > > > > Thanks, > > > Prashant Hi, I've used XHDL and it seems to do a reasonable job for synthesizable Verilog or VHDL code. However, I have seen some fundamental flaws with the tool when translating designs with very large hirarchies or slightly ambiguous code such as the following sample code from Verilog to VHDL (multiplexor). assign enadet = (synchronization !== "none") ? neg : (channel == 8) ? custom : neg_sync; XHDL will also insert a lot of bogus connections that don't hurt the functionallity but add uneceisary delay - I didn't care about the delay at the time but if you are tryn' to create high-speed designs it might not perserve delta cycles etc or carfully placed delays/buffers. All said... the tool does do a solid job of translation despite the weaknesses you would find in just about any translator anyway. An GNU open sourec alterative is vhd2vl - and its pretty good too... You can get it from... http://www.asherm.com/research/hdl/vhd2vl/ an example of the translation from vhdl to verilog is located at http://www.asherm.com/research/hdl/vhd2vl/example/ Take care, >Asher< San Francsico, CA http://www.asherm.com/Article: 54656
"Michael A. Covington" wrote: > > "Eric Smith" <eric-no-spam-for-me@brouhaha.com> wrote in message > news:qhllycn8j1.fsf@ruckus.brouhaha.com... > > > > I've found that it *is* necessary when interviewing programmers to ask > > them to write at least a little code, because some people with great > > resumes can't actually code their way out of a paper bag. Having been > > on the other side of the interview process, I know that spontaneously > > writing code on a whiteboard is much more difficult than coding in a > > normal situation. So when I do this, I'm not timing them, and I'm not > > looking for perfect syntax. I mostly just want to see that they appear > > to know how to write code. > > Right. I've run into that, too. In oral exams, I often give a rather > simple programming task, to see if the student can write a few lines of code > on the whiteboard. Sometimes they seem to have no idea! When this happens > with someone who has just finished 2 years of programming, I come away > unimpressed. Maybe I am just getting old and don't work the same as the younger crowd. The last job interview I had (the one after the one where I refused to sign an NDA and got tossed out in the middle of the interview) I was asked to write some VHDL on the white board. It was then that I realized that my development process did not actually involve "writing" code. I learned to design hardware before ICs (as a teenager, not professionally, I'm not *that* old) and so I think in terms of what I need the hardware to be rather than the code to express the hardware. Then I pull in snippets of code to implement the hardware. Most of the time I am lifting code from other designs or even other sources. I don't feel the need to memorize every last detail of the rules of VHDL and I never learned the rules for Verilog. So I avoid the few known pitfalls in both languages and just keep my code simple. But I can't do it at all cold in front of a white board. This same company, different interviewer, asked me how to make a serial design work at a higher speed when the circuit was maxed out. I simply did not understand what he was asking. Now I realize that he was trying to ask me if I understood how to design parallel circuits to process more than one bit at a time. Well, of course I understand that. But because I did not make the connection in 15 seconds, I failed that interview. As for debugging exercises, I don't see how this is any different from asking someone to write code. I do a much better job of debugging my own designs because I already understand what they do and *how* they do it. To pick up someone else's code and to figure out what they were thinking can take a few seconds or a few hours depending on how differently they think from me. Of course you can't use the resume alone as a way to judge a job applicant either. My methods normaly involve a lot of questions about their prior work and a judgement on my part on at what level they talked and whether they understood the things they told me. Anyone can fill in the details from a book. I look for people who *understand* the top level view. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54657
Austin Lesea wrote: > > Rick, > > Really neat and useful things. > > Really. > > We will outline all of that it a data sheet or user's guide at some point > relatively soon. I see that this is not new to S3 since it is also in V2. Can you tell us what it does in V2? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54658
"Brendan Lynskey" <brendan@comodogroup.com> wrote in message news:<j9Rma.7414$xd5.264132@stones.force9.net>... > Hi. > > What's the position in writing an well-established type of CPU core (like a > Z80) and selling it? > > Would I have to pay royalties to anyone? > > Cheers, I believe it depends how old the CPU and any associated patents are. I believe the US patents last for 17 years. Not sure how it works with copyrighted instruction sets (or if that is even possible). Many very good CPU cores have already been copied and many are freely available at (www.opencores.org). Some, MIPS and ARM come to mind, are so scared of the open/free implementations of their CPUs that they fight very hard to get them removed. OpenCores has even it's own CPU IP core (Open RISC), developed completely from scratch, with it's own development tools as well (the GNU chain of course :*). I wouldn't be surprised if it soon will kick but on any commercial CPU available. -- rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores --> http://www.asics.ws/ <---Article: 54659
Goran, I mentioned that I had mixed feelings then went on to only convey the negative ones. Not the best move on my part. I don't really want to open up a Xilinx vs. Altera debate. One of the big reasons I went with Altera is that they support all of their devices in the free versions of their software. What I mean by 'all' is that each family has at least one device supported. Event the Excalibur family with ARM processor. Their dev kits come with a device and are generally less expensive with more peripherals. In addition the NIOS soft core is provided free with any NIOS dev-kit (with software tools) and it's royalty free for re-use... this is a big deal. Those were some of the factors in my decision to go with Altera. I'm very interested in hearing from other NIOS users on their experiences. Goran Bilski <Goran.Bilski@Xilinx.com> wrote in message news:<3E9B1F99.17B9B1C5@Xilinx.com>... > Hi Jim, > > If you can give the overview picture of your system, I could then create a > similar system using MicroBlaze. > This will give you something to compare against. > > Göran Bilski > > "Jim M." wrote: > > > I recently purchased a NIOS Stratix 1S10 Development Kit from Altera > > and have mixed feelings about Quartus, SOPC Builder, and the NIOS > > Core. (For those poor souls interested, I've included some comments > > at the end of this post... feel free to provide feedback.) > > > > However, here's my question: > > > > What's the maximum clock frequency anyone has achieved using the NIOS > > 3.0 CPU in 32bit mode with the standard peripherals (SRAM, SDRAM, > > Ethernet, PIO, UART, etc. as in the Reference Design provided by > > Altera)? > > > > I've tried isolating the various components into LogicLock regions. > > I've tried different fitter/netlist optimizations. The maximum Fmax I > > have achieved to date is 80 MHz. This is after letting Quartus "fit" > > for 10 hours... it actually didn't stop, I had to abort the fitting > > and refit to finially get an interim result (see other misc comments > > below). > > > > Altera advertises 125 MHz for the Stratix Device and NIOS 3.0... > > However a reference design that builds at that clock rate is not > > provided. It appears that Altera gives you just enough to get your > > feet wet... anything above and beyond that is Intellectual Property > > that you need to buy. > > > > Other Observations/Comments: > > > > 1. The Quartus II SP1 software is extremely flakey. I've generated > > numerous faults when deleting/modifying child LogicLock Regions. It > > also takes forever to fit my Stratix design which is only 6000 LEs. > > If I select the "limit fitting attempts to 1" option, Quartus > > sometimes fits many times (like forever...) why?!?!? Also, after a > > design is finished building, the software sits around for up to 5 > > minutes before it generates a "finished" dialog box. I'm not sure > > what's going on between the Quartus Application thread and the Quartus > > Compiler thread, but it's fustrating enough just waiting for the > > design to build, let alone waiting for Quartus to figure out the build > > is done. I could go on and on, and that's only the result of 4 weeks > > of effort with a small design. I feel sorry for those folks working > > on a 100,000+ gate design. I guess modularity is the key there. > > > > 2. I can't simulate designs with virtual pins. I get warning during > > the analysis of the simulation and then receive results with all input > > pins a zero and output pins undefined. In addition, I can generate > > hold time warnings during simulation for a design that didn't compile > > with any hold time warnings. I'm not talking about hold time warnings > > on my input signals, I'm talking about hold time warnings on internal > > registers in my verilog code. Registers that I've taken care to hold > > for 1 or more clock cycles before using in other parts of the design. > > Again, the compilation of the design did not generate hold time > > warnings... only the simulation of the design. > > > > 3. PLLs generate different timing analysis results. THIS IS VERY > > ANNOYING! When I build up a "black-bock" design with virtual pins I > > obtain a Fmax calculation from the timing analysis routine. I then > > LogicLock the design and export it. When I import the design into a > > new project and clock it using a PLL it generates negative slack time > > warnings! If I remove the PLL and replace it with a clock pin, I get > > the Fmax result that I obtained during the "black box" design. I beat > > myself up for a week trying to debug a design that wasn't broken > > because of this goofy behavior in Quartus. I'm still not sure if the > > slack time warning it legit and wether I should be concerned about it. > > > > 4. SOPC Builder will lock itself up if you double-click components > > before selecting them. Give it a try... double click a component line > > in your NIOS design before selecting the line item. After a couple > > times the SOPC builder application creeps to a halt. > > > > 5. Documentation on the various megafunctions is lacking. A good > > example is the altsyncram megafunction. It doesn't state any timing > > requirements on the input registers, enable, and clock signals. Do I > > hold the data 1 cycle before flipping the write enable? How about > > holding the write enable before de-activating it? Why is the > > addressing based upon the data bit-width? Trying to tie a 32-bit > > altsyncram block to a NIOS CPU is difficult because you need to > > specify the address space of the peripheral and the address space of > > the altsyncram block is based upon the bit width (not the number of > > bytes). > > > > 6. I have yet to get a Leonaro-Spectrum synthesized Verilog file to > > build in Quartus. I can used Spectrum generated .edf files but not > > verilog. I get LCELL parameter errors. Unfortunately, Altera can't > > seem to duplicate this... anyone else see this behavior? I'm not sure > > if Spectrum synthesizes Verilog better that Quartus, but it definitely > > does it faster. > > > > Feedback is welcome... even if it's the "you're an idiot and here's > > why" variety...Article: 54660
"valentin tihomirov" <valentin@abelectron.com> wrote in message news:<3e9a865c_2@news.estpak.ee>... > I have an idea to implement all digital logic of my circuit into a CPLD. The > only doubt is external UART. I know, additional UART is a big pain, > currently I use tl16c750. I think that a price of external uart is the same > or greater than an average CPLD chip. All IP cores suggested by google are > complex, ie with FIFOs and flow control. I would be satisfied with the > 8051-compatible UART. That means an interrupt, 8bit SIN, SOUT registers, TI, > RI flags and a hardwired frecuency. Any suggestions. Try www.opencores.org, there must be half a dozen different flavors of uarts ... Regards, rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores --> http://www.asics.ws/ <---Article: 54661
"Peter Seng" <p.seng@seng.de> wrote in message news:<b7gcu4$3fv$1@online.de>... > Hello, > which are the most relevant FPGA sites on the net ? > Showing applications, free cores, hints, datasheets, discussions and so on ? > We plan to make a page of contents at our homepage. > All answers welcome - thanks ! > > Peter Seng Try www.opencores.org, many good examples, Free IP cores ... Regards, rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores --> http://www.asics.ws/ <---Article: 54662
Hi There! I am working on building a bus bridge module in an FPGA for a porprietary, synchronous PCB-bus system I am also working on. All I need is a 'free' SOC-bus protocol that allows for pipelining and is user-configurable, manufacturer independent... and free of fees. :-) I already made an approach with WISHBONE, but gathered more or less severe problems in realization of pipelined mode, because Wishbone has a somehow 'not-pipelineable' signaling scheme. I'd be very thankful if somebody helps me. regards Chris. P.S.: Have had a glance at Avalon, AMBA, CoreConnect, but either didn't get the features I wanted or was terrified by limitations in license matters.Article: 54663
OK.
Here it is:
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=11182
Answer 11182:
Applies to Virtex II Pro, and also to Spartan III, except that the JTAG pins
use external pullups to 3.3V in order
to be compliant with the JTAG spec (which requires 3.3V -- though it works fine
at 2.5 V).
Answers Database:
Virtex-II - What is the purpose of the VCCAUX power
supply
pins?
Family: Hardware
Product Line: Virtex-II
Part: Virtex-II
Version:
Record
Number: 11182
Last
Modified: 07/18/02 18:06:21
Status:
Active
Problem Description:
Keywords: Virtex-II, VCCAUX, power, supply, pin, input,
JTAG, configuration, I/O, IO, volt
Urgency: Standard
General Description:
On Virtex-II devices, what is the purpose of the VCCAUX
power supply pins?
Solution 1:
VCCAUX (3.3V) is used to power the JTAG and dedicated
configuration pins, thus making them
independent of VCCO. (This resolves the issue encountered
in Virtex-E, where Banks 2 and 3 were
required to be powered by 3.3V for JTAG configuration.)
Additionally, VCCAUX powers IOB pre-drivers, differential
input amplifiers/comparators, LVDS bias
generators, DCM delay lines, and other internal reference
supplies.
VCCAUX must ALWAYS be connected and bypassed properly in
order for Virtex-II device to
function correctly.
The VCCAUX value does not need to be the same as the VCCO
or VREF value in the same bank.
When VCCAUX is applied, VBATT does not draw any current;
thus, the battery can be removed or
exchanged.
If VCCAUX and VCCO are both 3.3V on the same bank, they
can be powered by the same supply.
VCCAUX is required regardless of the I/O standard used.
This configuration simplifies PCB power
management, provided the power plane is properly
decoupled/ bypassed.
In a design where DCM is used, it may be beneficial to
separate VCCAUX and VCCO power planes to
prevent VCCO droop (that may be caused by SSO) from
disturbing VCCAUX. Please see (Xilinx
Answer 13756) for more information about this guideline.
NOTE: For more information about VCCAUX, please see:
- The Virtex-II Handbook, Chapter 3, Page 350,
"Introduction => Mixed Voltage Environment":
http://www.xilinx.com/products/virtex/handbook/index.htm
- The Virtex-II Data sheet:
http://www.xilinx.com/partinfo/ds031.htm
Austin
rickman wrote:
> Austin Lesea wrote:
> >
> > Rick,
> >
> > Really neat and useful things.
> >
> > Really.
> >
> > We will outline all of that it a data sheet or user's guide at some point
> > relatively soon.
>
> I see that this is not new to S3 since it is also in V2. Can you tell
> us what it does in V2?
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
Article: 54664Ok my question was a little more basic than this. I'm currently designing some audio processing in an fpga. Let's say I want to build a 'volume' control core. Basically, it's only a divider (say 32 bits). However, how do I know that it will run fast enough for my application (say 44.1khz)? Thanks David "Ray Andraka" <ray@andraka.com> wrote in message news:3E9C0082.4D3AEAE1@andraka.com... > more or less. WIth the 4.2 and later version router, even that may not be > enough. The new router is lazy in that it only improves routing to meet the > slack on all paths. The result is less than optimal routing in which every path > becomes the critical path. If you are pushing the timing at all, a macro can > route with wonderful results in isolation but then when placed in the circuit > might fail miserably with the exact same timespecs. Worse yet, the same macro > instantiated multiple times will make timing on some instances and not on > others. This is new behavior starting with the 4.x tools (not so new anymore). > Please complain to Xilinx, they don't seem to see this as a problem...it was > changed to improve the time to a routed solution but as a result the quality of > route has plummeted. Altera, take notes so that you don't do the same slack > based routing mistake. > > > David wrote: > > > Hi, > > I'd like to know if it is possible to know the speed of a particular core in > > Xilinx core generator. For example, I want to create a combinational > > multiplier. How do I know if it will be fast enough for my design? Even if I > > choose the 'pipelined' option, how do I know the fastest clock rate possible > > for a given Fpga? Do I always have to make a project in ISE and test it > > myself with post place and route simulation? > > > > Thanks > > David > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 54665
If you're using Linux, OpenMosix is some good load balancing software.. Then you could do someting like start up a bunch of processes to render each scanline, and then OpenMosix would move these processes out to the other computers automatically. -Buddy On Mon, 14 Apr 2003, Matt Giwer wrote: > I've connected my older computers into a LAN. I've been parcelling out > frames for animations with very worth-the-effort improvements. I've been > considering an actual cluster but haven't worked out how to make it work > with povray yet. I can automatically parcel out rows by cpu speed but I > haven't dug into cleanly reassembling them to a single image. I can do > that without a cluster. > > -- > Those who think and question are the minority, those who do not > the majority. Directing propaganda at those who think and question > can at best gain 100% of the minority. It is best to target > the majority. > -- The Iron Webmaster, 2607 > >Article: 54666
The primary reason for this change was cost related. We evaluated a huge number of designs from customers and found that nearly all designs used less than 50% of the available distributed RAM or SRL features. Certainly, there were a small percentage that used above 50%, mostly targeted to extreme-performance DSP applications. Distributed RAM or SRL is typically used for small, local storage needs. Applications that need more distributed RAM or SRLs can continue to use Virtex-II or Virtex-II Pro. Applications requiring large amounts of RAM leverage the on-chip 18Kbit block RAMs. Removing the distributed RAM or SRL from half the slices allowed us to shrink the CLB fairly significantly, consequently allowing us to shrink the cost. The slices with memory are called SLICEM's, the 'M' indicating Memory. The slices without memory are called SLICEL's, the 'L' indicating Logic-Only. Logic functions fit in either slice type. Distributed RAM and SRL only fit in SLICEM's. Another often-asked question is "If removing distributed RAM and SRL reduces cost, why didn't you remove it from all the slices?" There are two reasons, primarily. One is that a variety of designs and IP cores use distributed RAM and SRLs already to great effect. Another is that, when you use these features, you effectively boost the gate capacity of a slice by up to a factor of sixteen or reduce the slice cost by up to a factor of sixteen. -- --------------------------------- Steven K. Knapp Spartan-3/II/IIE FPGAs E-mail: steve.knapp@xilinx.com --------------------------------- Eric Smith wrote: > > In the Spartan 3, Only two of the slices in a CLB can have their LUTs > used for distributed RAM or SRL. That's a new "feature", isn't it? Was > there a technical reason why this was done, or is it just product > differentiation?Article: 54667
The primary reasons we chose not to offer a 240-pin PQFP (PQ240) option are signal integrity, power dissipation, and cost. The smaller, lower-cost 256-ball fine-pitch BGA package (FT256) is significantly better in these areas plus provides additional I/O pins. The FT256 is only 25% the area of the PQ240 package. http://www.xilinx.com/bvdocs/packages/ft256.pdf I agree that BGAs are more difficult for small-volume prototyping compared to the PQFPs. However, they offer significant benefits for volume applications, the primary target for Spartan-3 FPGAs. Just as an aside, it is true that the 1C12 has additional registers (I'm assuming that you meant flip-flops), but the 1C12 also costs more than XC3S400. Furthermore, the XC3S400 has more block RAM (288Kb vs. 234 Kb) and more total I/O (264 vs. 249), plus dedicated multipliers, plus two more clock managers, etc. If the concern is strictly register based, then the distributed RAM or SLR functions in the XC3S400 provide up to an amazing 60,928 registers (896 CLBs * 4 Lust with memory/CLB * (16 registers/LUT + 1 flip flop/LUT). Obviously, not every application can use all this capability, but it is achievable in some DST applications. -- --------------------------------- Steven K. Knapp Spartan-3/II/IIE, Spartan/XL FPGAs E-mail: steve.knapp@xilinx.com --------------------------------- KB wrote: > > On Mon, 14 Apr 2003 16:59:06 -0400, Theron Hicks > <hicksthe@egr.msu.edu> wrote: > > >Has anyone noticed that this part is available with LEGS? It appears > >that someone at Xilinx was listening to the request for non-BGA parts. > > > > Actually I was a little disappointed in this area. Only the XC3S50 / > 200 / 400 is available in the 208 pin pqfp .. the 2e took this package > up the 300 part so some improvement yes .. but the Cyclone EP1C12 is > available in a 240 pin pqfp ... 30+ more I/O pins, and the cyclone has > 12K registers , a bunch more than the new 400 part. my 2'c KBArticle: 54668
"Hal Murray" <hmurray@suespammers.org> wrote in message news:v9ncbao3qpqv5c@corp.supernews.com... > If you are doing something kludgy like running RS232 links > between buildings then maybe you would expect an occasional > error. (especially if there is a local thunderstorm) If > you are just going a few feet over to the next machine, then > the error rate should be 0. Unless the next machine over is a serial-controlled arc welder :-). I have to agree with your point. I've never had data corruption problems over reasonable RS232 runs (say 100 feet) even when running at absurdly high speeds.Article: 54669
Hi, I have to develop a image processing system, so I'm studying Altera APEX PCI Development Kit to perform image transmission between PC memory and the APEX FPGA. However the tools avaiable to the developers are not clear to me, where can I find OpenCores? What's necessary from the PC side? I really thank any help. []s MarcosArticle: 54670
"Peter Seng" <p.seng@seng.de> wrote in message news:b7gcu4$3fv$1@online.de... > Hello, > which are the most relevant FPGA sites on the net ? > Showing applications, free cores, hints, datasheets, discussions and so on ? > We plan to make a page of contents at our homepage. > All answers welcome - thanks ! Useful material seems to be scattered widely across the net, and I've found all of the following to be helpful at one time or another. I'll let others decide which of these would fall into the "most relevant" category. In no particular order: http://www.mrc.uidaho.edu/fpga/fpga.html http://www.optimagic.com/lowcost.html http://www.staticfreesoft.com/ http://www.al-williams.com/pldhome.htm http://www.asics.ws/fip_sub.html http://www.fpgacpu.org/ http://www.opencores.org/ http://www.us.design-reuse.com/download/sip/ http://www.free-ip.com/ http://www.acc-eda.com/vhdlref/index.html http://members.aol.com/SGalaxyPub/useful_links_vhdl.htm http://tech-www.informatik.uni-hamburg.de/vhdl/Article: 54671
Bams,
I think I agree with the Xilinx multiple driver issue.
Your generate statement includes the process:
"P1: process (clk,load,control)"
Hence, it creates size number of copies of process P1.
As a result, the signal Data_out1 is driven size number
of times.
Interesting that it worked in nclaunch.
Cheers,
Jim
bams wrote:
> Hello,
>
> I have written a module in VHDL using generate and process
> statements.when I simulated in Cadence nclaunch tool.It worked
> perfectly, Out of curiousity, I tried to simulate in Xilinx, it didn't
> synthesis.It is giving me multiple driver problem.Why it is so?why it
> is different to different softwares.I am posting the VHDL code for
> reference.the multiple driver problem is coming in the output
> (Data_out1) in the code.please let me know why the same code isn't
> simulated in two different softwares.
>
>
> ------------------------------------------------------------------
> VHDL code
> ------------------------------------------------------------------
> library IEEE;
> use IEEE.std_logic_1164.all;
>
> entity FIFO_new is
> generic (width: integer := 64;
> size: integer := 4);
> port (
> Data_in: in STD_LOGIC_VECTOR( (width -1) downto 0);
> clk: in STD_LOGIC;
> clear: in STD_LOGIC;
> control: in STD_LOGIC;
> load: in STD_LOGIC;
> Data_out1: out STD_LOGIC_VECTOR(15 downto 0)
> );
> end FIFO_new;
>
> architecture FIFO_arch of FIFO_new is
>
>
> component reg2
> generic (k: integer := 16);
> port (
> D: in STD_LOGIC_VECTOR((k -1) downto 0);
> clk: in STD_LOGIC;
> clear: in STD_LOGIC;
> Q: out STD_LOGIC_VECTOR((k -1) downto 0)
> );
> end component;
>
> ---signal declarations
>
> type DATA is array (0 to (size-1)) of STD_LOGIC_VECTOR(15 downto 0);
> signal T: DATA;
> type ENTRY is array (0 to (size-1)) of STD_LOGIC_VECTOR (15 downto 0);
> signal S: ENTRY;
>
>
> begin
> -- <<enter your statements here>>
>
> G1: for i in 0 to (size-1) generate
>
>
> S(i) <= Data_in(((16*i) + 15) downto (16*i)) ;
>
> FG2: reg2 port map (S(i), clk, clear, T(i));
>
>
>
> ---new process for the parsed outputs to be retrieved from the array.
>
>
> P1: process (clk,load,control)
>
> variable tmp: integer range 0 to (size-1);
> begin
> if (clk'event and clk = '1') then
>
>
> if (control='0' and load='1' ) then
> tmp := 0;
>
>
> elsif (load ='1' and control='1') then
> if (tmp < (size-1)) then
> tmp := tmp + 1;
> end if;
> end if;
>
> Data_out1 <=T(tmp);
> end if;
>
> end process P1 ;
>
> end generate G1;
>
> end FIFO_arch;
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Article: 54672> > johnjakson@yahoo.com (john jakson) wrote in message > snip > Before you go further, I presume you have a valid logic simulation in some >form that demonstrates correct results for different m,n sizes, signed & >unsigned, with random data sets, preferably in C or HDL. That will get you a >good deal more credit, here and with any industry contact. The C models are ready. The correctness of the technique is proved mathematically. > I am somewhat intrigued to know what is up your sleeve, perhaps if you are > real serious you may wish to disclose under NDA to another expert for a sanity > check, safer than blowing it all to the world here. If it was my invention, I > might contact an engineer at TI whose sole job is designing arithmetic units > for the DSP products, (if he's still there). > That is what I want to do. Signing a NDA and disclosing the idea to an industry expert. I would be very thankful If somebody could help me to establish the bridge. > By the way, last time I did an ASIC that was all focussed on minimizing no of > muls, and the area/delay of the muls, an improvement of 10% for the mul might > have made the chip 0.1% smaller. But if you have something, it might be speed, > since muls with acc are often theeee critical path for a whole design in DSP > or maybe FPU. So now besides logic sims, a spice or static timing analysis > would demonstrate what your improvement is over usual design for some set of > rules. I will publish a pdf file including a graphical presentation of the technique. It will become clear how the hardware and delay is reduced.Article: 54673
Rene Tschaggelar wrote: > > invalid@invalid.com wrote: > > Hello, > > > > In article <3E9B5930.D5C331BA@andraka>, ray@andraka says... > > > >>Not quite. A UART typically samples the start bit at 16x clock, then from the > >>estimated center of the start bit (determined by a count of 8 clocks from when > >>the start goes active), the rest of the bits are simply sampled at the center of > >>the bit times, ie multiples of 16 clocks from the center of the start bit. > > > > > > Is this the only technique used? Sorry if this seems naive, but I've > > frequently seen the term "vote logic" or "majority detector" used in > > conjunction with UARTs(even in the TI literature for the UART the OP > > mentioned). I was always under the impression that the bits are sampled > > at 16x and the bit is given the majority value. > > I was under the same impression (majority vote) after having read > the description of the 8250 and/or 16550 about 15 years back. The 80C51 uses 3 slot sampling, and because the dats is serial, you only need one vote block. In the simplest form, this is a gated saturating 2 bit counter. Data into the shift register is from this filtering. 16x seems mainly historical, and newer UARTS and uC allow for this to be reduced. 'Good' UART design is non trivial, you should sample the START bit at 0.5T, to confirm it is not noise, and also reset the start bit sampler NOT at the end of the stop bit, but in the centre of the stop bit. A holding buffer is also usually needed, unless your app can guarantee it only reads/writes the shift registers in their narrow valid & static time slots. Some UARTs allow fractional stop bits on TX. -jgArticle: 54674
Steve Knapp wrote > --------------------------------- > Steven K. Knapp > Spartan-3/II/IIE FPGAs > --------------------------------- Why Spartan-3, not Spartan-III?
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