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> Martin, > Did you try to run LTC3405A in the "burst" mode, i.e. with a MODE pin > connected to the GND ? Yes, I did. The burst mode only helps to save power at low current with a higher output ribble. In puls skipping mode the LTC3405 has also less EMC problems. I did not understand why the example in Alteras app. note used burst mode. FPGA circuits are no 'low power' applications. MartinArticle: 53551
Hi, All, Does anyone have propagation delay data of 16 bit adders/comparators on Xilinx FPGA spartan and vertex families? What are the gate counts ? Thanks JimmyArticle: 53552
Martin Schoeberl wrote: > > "Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag > news:vZOca.5899$8b.682508@news02.tsnz.net... > > "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message > > news:wppca.229368$AV5.2637012@news.chello.at... > > > I would like to thank all for their good ideas and help. > > > > > > I've tested some of the suggested ideas and wrote a little summary with > > some > > > osci plots. You can find them at: > > > http://www.jopdesign.com/cyclone/powerup.jsp > > > > Interesting results. > > Observations: > > > > There are two good plots that clearly show 'stalling', one at 400mA, and > > another that peaks at > > 600mA+, and also stalls. This is the 'hard to model behaviour'. > > A simple R-C model has some time element, and peak current content, but a > > real device is more > > charge modeled. > > But both are the stalls of the LTC3405, not really the Cyclone. The first > one is where only the LTC3405 is used and it delivers 'what it can' at 0.5 > V. The second is the same with additional current from the Vbe multiplier. But the cyclone was connected, or did I mis-read the notes ? The key issue with this FPGA startup problem is that it departs from a classic charge model, and can, in fact 'stall for ever' - if it took twice as long, at half the current, it would not be so important to get it right ( ie with margin). <snip > > A vanilla LM317 also looks a good candidate, tho the package is not small > > (SOT223 & up) > > I considered this too, but there are two reasons I don't like it. You have > to add an additions tantal co of 10uF for stability. And I'm a little bit > afraid that two integrated regulators (with all those protection) could > result in an unstabile circuit. The 10uF is needed on the newer LDO 1117 et al, and the 317 should remove itself when Vo > 1.25V, so regulation should be stable. ( it can only source current ) Some parallel Rl might be needed, to avoid Vcore creep, but IIRC the cyclone has some 10's of mA min Icc ? Be interesting to see the plots with a LM317A :) (ref to gnd) One regulator that looks good for total 'recalcitrant FPGA' core supply in the new LDO-317 arena, is the FAN1086 from Fairchild - 4.5A Limit, DPAK SMD, and 48c price point.Article: 53553
> > But both are the stalls of the LTC3405, not really the Cyclone. The first > > one is where only the LTC3405 is used and it delivers 'what it can' at 0.5 > > V. The second is the same with additional current from the Vbe multiplier. > > But the cyclone was connected, or did I mis-read the notes ? > It was connected. Perhaps it was not clear what I wrote. It's a way how you see it. Stalls the Cyclone or the LTC3405? It's a combination. If you can 'fool' the LTC3405 with a higher voltage at it's maximum current it does not 'see' a short circuit. > The key issue with this FPGA startup problem is that it departs > from a classic charge model, and can, in fact 'stall for ever' - if > it took twice as long, at half the current, it would not be > so important to get it right ( ie with margin). Right. I just used the simple RC model to experment a little bit without blowing the FPGA :-) > One regulator that looks good for total 'recalcitrant FPGA' > core supply in the new LDO-317 arena, is the > FAN1086 from Fairchild - 4.5A Limit, > DPAK SMD, and 48c price point. DPAK is too large for my board :-( MartinArticle: 53554
Joshua, Thanks for the response. I am not quite sure how I didn't see this before. Apparently I just like to humiliate myself publicly :) The simulation that I am implementing inside the fpga involves states that are being loaded out of blockram and are eventually updated and loaded back into memory replacing their previous values. At this stage in my design I was only interested in using a testbench to run the simulation and probe the internal signals to verify that it is working properly. Yet I was using the synthesis tool as a check for any errors in my vhdl before I moved into modelsim. This testbench mindset is what got me into trouble. The synthesis tools did exactly what they are supposed to do and since I didn't want to see anything outside the fpga that involved the blockram outputs it figured that I didn't need them. (This must be one of those rare occasions where the synthesis tool was smarter than the programmer) Chip Lukes "B. Joshua Rosen" <bjrosen@polybus.com> wrote in message news:<pan.2003.03.15.22.12.35.670516.5021@polybus.com>... > On Sat, 15 Mar 2003 16:58:37 -0500, Chip wrote: > > > Hello all, > > > > I ran into a problem in a design where my instantiated dual port > > blockrams were being optimized away. > > > > I created a very simple example to help explain my problem. > > > > A dual port block ram is created such that data is only written to port > > A and only read from port B. > > > > Port A of a Block RAM writes data into memory at addressX. Port B reads > > data from memory at addressY. > > > > the data output of of port B is attached with a signal to the data input > > of port A. (in my original design this data was actually modified) > > > > This feedback of an output to an input causes synthesis to remove the > > instantiated block ram entirely. Am I doing something wrong or do I > > just need to explicitly tell ISE 5.1 to not optimize my blockrams away? > > > > Is the output of the RAM connected to anything except it's data input? If > there is no logical path to an output pin the logic will be optimized > away.Article: 53555
hi john, glad to see ur mail. this is not related to the school assignments. i am working on some projects and the resources are almost none. so i require someone from texas instruments who can help em with. can u please suggest me the news group i need to put the request. thank you for ur suggestion niranjandas johnjakson@yahoo.com (john jakson) wrote in message news:<adb3971c.0303141820.35ee5eb6@posting.google.com>... > > All very well to ask serious engineering related question from > industry, but it takes some nerve to ask so many question which as far > as I can tell do not relate to FPGA. > > You should be asking class mates who will be much more familiar with > your assignments. > > Still in the wrong NG (news group)Article: 53556
"Dan" <dan@nospam.hvwtech.com> wrote in message news:MPG.18dbaf6c7aa5b0a98969b@news.telusplanet.net... > In article <60e37826.0303131024.77a1fe15@posting.google.com>, > santa19992000@yahoo.com says... > > Guys, > > > > what is FPGA?. Also what is the difference between FPGA, CPLD and > > ASIC?. Especially the functionality diff between ASIC and FPGA?. > > Thanks in advance. > > > Field Programmable Gate Array > Configurable (??) Programmable Logic Device > > These types of devices are "programmable" or "configurable". These days > it may be more marketing then technical but FPGA's are layed out in > arrays and developed the name. > > You stumped me on ASIC I know that is a silicon chip that has been > designed for a specific function. It is not "programmable" or > "configurable". Before FPGA's were cheap and small enough the only > option for an inexpensive design was for an ASIC to be designed. ASIC - application specific integrated circuit what about usic ? user specific integrated circuit Is this term actually used at all or is it just a academic used term ? according to our lecturer classifications of IC's general - general purpose devices eg z80, 68000, basic gates asic - application specific ic eg modem chips, embedded controllers usic is user specific ic designed to meet the needs of a specific user eg most glue chips in present day micro computers AlexArticle: 53557
"zhengyu" <zhengyu@attbi.com> wrote in message news:N6Wba.70411$6b3.259215@rwcrnsc51.ops.asp.att.net... > Hello, > > I am just wondering if it is possible to write a single byte in memory, > then write another single byte right next to it. > Normally I would pre-append two bytes into a word of 32 bit wide, then do a > single write to the memory. But is it possible to write it byte by byte, > instead all at once. Assuming 32 bit memory bus width. On many systems the cache will handle this. Some have byte addressable (byte enable) memory, so it would take two cycles. Some have only word addressable memory, so the word is fetched, modified, and rewritten. It could do this twice, or realize that both were the same word and read or write once. -- glenArticle: 53558
"Brian Drummond" <brian@shapes.demon.co.uk> wrote in message news:ndc17v0bfavtd5u6ivs508og63t23ujauh@4ax.com... (snip) Someone wrote: > >> By the way this is the wrong NG, and the wrong century. > > > >Which newsgroup do you suggest, comp.arch.ttl? > > oh goody... > > can we have a comp.arch.tube as well? Oh no. I just remembered that someone I knew some time ago worked on what would have been integrated circuit vacuum tubes. The application was ballistic missiles, after it was found that tubes were less sensitive to radiation and/or EMP*. * (not Experience Music Project) -- glenArticle: 53559
"Chip" <john_doebertson@yahoo.com> wrote in message news:49cdb4ba.0303151857.1fa12036@posting.google.com... (snip) > The simulation that I am implementing inside the fpga involves states > that are being loaded out of blockram and are eventually updated and > loaded back into memory replacing their previous values. At this > stage in my design I was only interested in using a testbench to run > the simulation and probe the internal signals to verify that it is > working properly. Yet I was using the synthesis tool as a check for > any errors in my vhdl before I moved into modelsim. > > This testbench mindset is what got me into trouble. The same problem happens in computer system/compiler benchmarks. Some programs are designed to take time, but not actually output anything, and some optimizing compilers will optimize away the part that takes time. Even more fun, some will compute complex expressions at compile time, leaving nothing left for run-time. I suppose synthesis tools could do that, too. -- glenArticle: 53560
hi , ive been implementing designs on XILINX XC2V100 FPGA. But till ow i dint make use of the components on the chip, like MULTIPLIER AND RAMS. i used COREGEN to create my Memory blocks and other multiplier structures, i dont think they r the actual components on the chip. can ne tell me how to acces these components. I Think v can use to constraint file. is this correct? thanx in advanceArticle: 53562
Sync resets may not reach all flops in a multiple clock domain case where some clocks are gated off at powerup hence it is better to assert reset asynchronously and deassert it synchronously regards JagsArticle: 53563
On Sat, 15 Mar 2003 18:57:46 -0800, Chip wrote: > Joshua, > > Thanks for the response. I am not quite sure how I didn't see this > before. Apparently I just like to humiliate myself publicly :) > > The simulation that I am implementing inside the fpga involves states > that are being loaded out of blockram and are eventually updated and > loaded back into memory replacing their previous values. At this stage > in my design I was only interested in using a testbench to run the > simulation and probe the internal signals to verify that it is working > properly. Yet I was using the synthesis tool as a check for any errors > in my vhdl before I moved into modelsim. > > This testbench mindset is what got me into trouble. > > The synthesis tools did exactly what they are supposed to do and since I > didn't want to see anything outside the fpga that involved the blockram > outputs it figured that I didn't need them. > > (This must be one of those rare occasions where the synthesis tool was > smarter than the programmer) > > > Chip Lukes > > I guess the rule is If you can't read it, then you don't need it (sorry, couldn't resist...) PCWArticle: 53564
Alex Gibson <alxx@ihug.com.au> wrote: : what about usic ? : user specific integrated circuit : Is this term actually used at all or is it just a academic used term ? I've never heard or seen this term used in the "real world". Indeed, this is the first time I've ever heard it used, period. It must be either an academic term, specific to Oz, or your prof just made it up. StuartArticle: 53565
In article <v79gsqcicnmnc8@corp.supernews.com>, Stuart Brorson <sdb@cloud9.net> wrote: >Alex Gibson <alxx@ihug.com.au> wrote: >: what about usic ? >: user specific integrated circuit > >: Is this term actually used at all or is it just a academic used term ? > >I've never heard or seen this term used in the "real world". Indeed, >this is the first time I've ever heard it used, period. It must be >either an academic term, specific to Oz, or your prof just made it up. It is an academic term that I've never heard of, and I've been campin out in dis here ivory-soap tower for years. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 53566
Hi, I'm looking to acquire a dev board for xilinx fpgas. As i'm currently a hobbyist, price is probably my main concern, although i will need a moderate number of gates. Recommendations of models/manufactureres are greatly appreciated. thanks, --buddyArticle: 53567
> Hi, > > I'm looking to acquire a dev board for xilinx fpgas. As i'm currently a > hobbyist, price is probably my main concern, although i will need a > moderate number of gates. > > Recommendations of models/manufactureres are greatly appreciated. a good list: http://www.fpga-faq.com/FPGA_Boards.htm the BurchED boards are very popular and moderate priced. MartinArticle: 53568
I am looking at XESS.com although I haven't committed to buying anything yet.Article: 53569
"Buddy Smith" <nullset@dookie.net> wrote in message news:b52kg4$l0c$1@news-int.gatech.edu... > Hi, > > I'm looking to acquire a dev board for xilinx fpgas. As i'm currently a > hobbyist, price is probably my main concern, although i will need a > moderate number of gates. > > Recommendations of models/manufactureres are greatly appreciated. > > thanks, > http://www.digilentinc.com/ http://www.digilentinc.com/Catalog/system_boards.html http://www.digilentinc.com/Catalog/digilab_2e.html http://www.digilentinc.com/Catalog/peripheral_boards.html Affordable prices. They make the coolrunner2 board in the xilinx coolrunner2 dev kit. I bought the d2e and io board.Had no problems with it. Give good support. AlexArticle: 53570
Silly me but, why not ask Xilinx? They exist to have their product used. If your looking for solder pad sizes, that the route I would take. I don't design myself but I have checked out board data this way. -- harry.mythpig@ntlworld.com To reply, throw out the bacon. "Mike Hubert" <mph@xiphos.ca> wrote in message news:Xns933C5E6639BBBmphxiphosca@142.77.1.194... > Hi, > > I am about to get started on the design of a board containing two Xilinx > FPGAs: a Virtex II, and a VirtexII Pro, both in FG256 packages. > > I am looking for a footprint source for these components... may it be a > friendly individual, or a company. I checked with ECS and they don't have > them. I know designing them myself wouldn't be too much of a pain but the > fact of the matter is that we are extremely pressed for time and have to > save every minute I can! > > Any tips would be greatly appreciated. > > Thanks > > Mike Hubert > Xiphos Technologies Inc. > > Montreal, CanadaArticle: 53571
Tad off subject BUT, Does anyone know of a FPGA dev board that can be expanded? I know of the DINI group that has 5 large FPGAs on it but what I'm looking for is a board that can connect to other boards in order to expand the gate count. Tks in advance Jerry "Buddy Smith" <nullset@dookie.net> wrote in message news:b52kg4$l0c$1@news-int.gatech.edu... > Hi, > > I'm looking to acquire a dev board for xilinx fpgas. As i'm currently a > hobbyist, price is probably my main concern, although i will need a > moderate number of gates. > > Recommendations of models/manufactureres are greatly appreciated. > > thanks, > > --buddy >Article: 53572
In article <b52dc4$gav$1@sparta.btinternet.com>, aeu96186 @yahoo.co.uk says... > > Sorry me again, looking for footprints. I feel I kind of have to justify > > myself: don't get me wrong, I love dsesigning my own footprints. But I > have > > to have the next rev of our main product out for Tuesday, so I'm trying to > > cut corners wherever I can. > > What is a footprint? You don't live in snow country I guess. Think about your foot. Then design a PC board to plug yourself into. -- KeithArticle: 53573
"Peter Alfke" <peter@xilinx.com> news:3E720F88.B9A71C3A@xilinx.com... > Louis, there is nothing wrong with your approach if you: > 1. > distribute the slow 20 MHz clock on global lines (skew and hold-time > issues are equally important at 20 MHz as they are at 160 MHz. They can > even bite you at 10 kHz) > 2. > Watch the data transfer between the two clock domains very carefully. > Since your 20 MHz is the derived clock, assume that its edge is > significantly later than the 160 MHz edge that created it. That can lead > to unreliable race conditions when you transfer from the fast to the > slow domain. Using the opposite 160 MHz edge would be nice, but then you > have to watch the prop delay... > > Peter Alfke > Thank you very much for your reply. Yes, I ever worried about the above two issues, and I made high-speed module work at falling edge, and low-speed module work at rising, instead. Besides, some area constraints were added to the high-speed module to lessen the prop delay... There's still another gated clock application in my design. For redundancy purpose, we have two clock source from different systems. So I employ a phase-frequency detector to decide which clock is presented, and then select one of them for the whole chip. Thus, the clock for the remaining chip was a combinational gated clok... Is it possible to eliminate the gated clock?Article: 53574
> Does anyone know of a FPGA dev board that can be expanded? I know of the > DINI group that > has 5 large FPGAs on it but what I'm looking for is a board that can connect > to other boards > in order to expand the gate count. > Almost every board has some kind of expansion (pin heads). So just buy some of them and connect them with a short cable. I am thinking about this from time to time when I see the many FPGA boards laying around on my desk. Building a FPGA(-cpu) computing cluster :-) Martin
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