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I've been reading through some information about Xilinx tools (it's printed information, so it may be a bit out of date). It seems to me that the WebPACK is going to be perfectly sufficient for small designs, but installation involves a number of different licences and registrations for different parts, and at least one part needs the licence and registration renewed every 30 days. Is this sort of thing really necessary? What is the point? The software is freely available - it is arguably of interest to Xilinx to ask for an initial regsitration, but they are effectively hiring out the software for a regular payment of nothing. We do embedded systems development - that means long-term support for products. I need to know that the tools I use now will still work in five years time - even after the chips themselves are no longer available, we may still need to be able to update the code. We had exactly this sort of problem with tools for an older CPLD family from another manufacturer - the modern tools did not support the design language we had used, and renewal licences were not available. That meant messing around with old machines and changing the PC's time and date, just to change a couple of lines in the code. That is something we want to avoid in the future - it is of questionable legal status, and is definitely a big pain. As far as my very rough research has gone, most manufacturers seem to have this sort of arrangement for their tools. Are the paid-for versions of the development tools free of this sort of continual renewal demands? At least then we would have the option of buying our way out if Xilinx (or whatever manufacturer we choose) decides to make new development tools that are inconsistant with the current ones. (I have no objection to paying for better tools, although obviously lower price or free tools make it a lot easier to get started.) I'm resigned to following these policies and renewing licences regularly as necessary - it seems unavoidable, and it is not going to influence my choice of manufacturer or software. But I would love to hear if anyone has a reasonable explanation of why the software is "rented" rather than "sold".Article: 52876
Hi group, Can anybody tell me which kind of Decoupling Capacitor I should us for Xilinx Xc98288XL-10FG256. Is there any standard Guideline for selecting the Device Decoupling? Thanks in Advance SanjayArticle: 52877
Erik Spaenig <vikinger@uni.de> wrote: : Hi all, : I use the Xilinx WebPack (Release 4.2WP2.x - Par E.37) for an SpartanII : in my prjekt sometimes say the "Pad Report" from "Place & Route" the : SlewRate for the PCI-pads (IO-Standart : PCI33_5) is Slow : and this is the "Default value". : where can i switch this value permanetly to a fast SlewRate ?? E.g. in the UCF constraints file oder the constraint editor. Consider however which PADs to give the FAST attribute, as the FAST attribute increases switching noise and probably reflections. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 52878
AFAIR, the software prices from FPGA vendors 4-5 years back were very high, to the tune of $12K (I remember this price when Xilinx used to bundle Viewlogic tools with it's P&R). That was a perpetual license though and had a yearly maintenance renewal for an amount close to 10-15% of the original cost. This high initial cost was a hindrance in getting the tool in the hand of engineers, and they adopted a time-based-license (TBL) model to reduce the initial investment. So every year the license needs to be renewed at ~the same price as the initial investment or the then current price. Per Xilinx, once you buy a TBL you will receive updates free through the year. You should purchase an extension to stay current after one year. However, if a user does not purchase the extension, user can still use the existing version to finish any designs started during the year or fix bugs later for the same designs. Regarding Webpack, the free downloadable tool from Xilinx, AFAIK, only one initial registration on the web is needed, which as you rightly said is quite fair. I'm not sure where you read about multiple licenses and registrations. I'm sure the friendly Xilinx rep in your area will be able to help you with clarifications. "David Brown" <david@no.westcontrol.spam.com> wrote in message news:b3fb9l$sc6$1@news.netpower.no... > I've been reading through some information about Xilinx tools (it's printed > information, so it may be a bit out of date). It seems to me that the > WebPACK is going to be perfectly sufficient for small designs, but > installation involves a number of different licences and registrations for > different parts, and at least one part needs the licence and registration > renewed every 30 days. Is this sort of thing really necessary? What is the > point? The software is freely available - it is arguably of interest to > Xilinx to ask for an initial regsitration, but they are effectively hiring > out the software for a regular payment of nothing. We do embedded systems > development - that means long-term support for products. I need to know > that the tools I use now will still work in five years time - even after the > chips themselves are no longer available, we may still need to be able to > update the code. We had exactly this sort of problem with tools for an > older CPLD family from another manufacturer - the modern tools did not > support the design language we had used, and renewal licences were not > available. That meant messing around with old machines and changing the > PC's time and date, just to change a couple of lines in the code. That is > something we want to avoid in the future - it is of questionable legal > status, and is definitely a big pain. > > As far as my very rough research has gone, most manufacturers seem to have > this sort of arrangement for their tools. Are the paid-for versions of the > development tools free of this sort of continual renewal demands? At least > then we would have the option of buying our way out if Xilinx (or whatever > manufacturer we choose) decides to make new development tools that are > inconsistant with the current ones. (I have no objection to paying for > better tools, although obviously lower price or free tools make it a lot > easier to get started.) > > I'm resigned to following these policies and renewing licences regularly as > necessary - it seems unavoidable, and it is not going to influence my choice > of manufacturer or software. But I would love to hear if anyone has a > reasonable explanation of why the software is "rented" rather than "sold". > > >Article: 52879
Philip Freidin <philip@fliptronics.com> writes: > On 24 Feb 2003 12:51:34 -0800, mats_trash@hotmail.com (mat) wrote: > >As a project I've got a motherboard with an LVDS connector, which I > >understand can be used to control an LCD screen. > <snip> > > If on the other hand, this is a DVI connector (which is always > LVDS too), According to the DVI spec, the physical layer is TMDS (transition minimised digital signalling). It looks a lot like LVDS at a cursory inspection, but I haven't stared hard enough to see if the two are actually interchangeable. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 52880
"Neeraj Varma" <neeraj@cg-coreel.com> wrote in message news:b3fkif$1gtb0g$1@ID-159439.news.dfncis.de... > AFAIR, the software prices from FPGA vendors 4-5 years back were very high, > to the tune of $12K (I remember this price when Xilinx used to bundle > Viewlogic tools with it's P&R). That was a perpetual license though and had > a yearly maintenance renewal for an amount close to 10-15% of the original > cost. > > This high initial cost was a hindrance in getting the tool in the hand of > engineers, and they adopted a time-based-license (TBL) model to reduce the > initial investment. So every year the license needs to be renewed at ~the > same price as the initial investment or the then current price. I can see that point for the purposes of continually upgrading to the latest versions, which is essential for using the latest parts. > > Per Xilinx, once you buy a TBL you will receive updates free through the > year. You should purchase an extension to stay current after one year. > However, if a user does not purchase the extension, user can still use the > existing version to finish any designs started during the year or fix bugs > later for the same designs. Does this mean that you are somehow limited to not being able to start new designs? What is important for me is that if I purchase a licence now, I can use that software in the future, without having to continually pay in the mean time. We don't do much PLD work - I did one big design with a CPLD, and then it was about four years before I needed to touch it again (when the particular chip and package used became obsolete). Even if I had paid for the upkeep throughout the time when I did not use the software, I would still be left with nothing since the manufacturer stopped supporting the original design tools and was no longer issuing renewed licences, and the later software (which is admittedly very much better in most regards) did not support my original design language. I would like to be sure that I will not be in that position again - preferably with the free tools that I expect to be sufficient for our needs. Failing that, I would like to know that it is possible to buy a licence to cover this situation (and I'm sure that there are other development firms for whom this is an even more important issue). There are other things that make this far less of a problem now than last time (for example, I'll code in VHDL instead of a proprietry manufacturer's language, and I'll pick a fpga family that is not likely to be sold back and forth between manufacturers), but it is still a principle. > > Regarding Webpack, the free downloadable tool from Xilinx, AFAIK, only one > initial registration on the web is needed, which as you rightly said is > quite fair. I'm not sure where you read about multiple licenses and > registrations. I'm sure the friendly Xilinx rep in your area will be able to > help you with clarifications. > I'm not sure about the Xilinx tools themselves, and - as I said - I'm basing this on printed literature that is a little out of date. But certainly the ModelSIM module needs/needed renewal every 30 days, and there were a couple of other parts that also needed renewal every year. > > "David Brown" <david@no.westcontrol.spam.com> wrote in message > news:b3fb9l$sc6$1@news.netpower.no... > > I've been reading through some information about Xilinx tools (it's > printed > > information, so it may be a bit out of date). It seems to me that the > > WebPACK is going to be perfectly sufficient for small designs, but > > installation involves a number of different licences and registrations for > > different parts, and at least one part needs the licence and registration > > renewed every 30 days. Is this sort of thing really necessary? What is > the > > point? The software is freely available - it is arguably of interest to > > Xilinx to ask for an initial regsitration, but they are effectively hiring > > out the software for a regular payment of nothing. We do embedded systems > > development - that means long-term support for products. I need to know > > that the tools I use now will still work in five years time - even after > the > > chips themselves are no longer available, we may still need to be able to > > update the code. We had exactly this sort of problem with tools for an > > older CPLD family from another manufacturer - the modern tools did not > > support the design language we had used, and renewal licences were not > > available. That meant messing around with old machines and changing the > > PC's time and date, just to change a couple of lines in the code. That is > > something we want to avoid in the future - it is of questionable legal > > status, and is definitely a big pain. > > > > As far as my very rough research has gone, most manufacturers seem to have > > this sort of arrangement for their tools. Are the paid-for versions of > the > > development tools free of this sort of continual renewal demands? At > least > > then we would have the option of buying our way out if Xilinx (or whatever > > manufacturer we choose) decides to make new development tools that are > > inconsistant with the current ones. (I have no objection to paying for > > better tools, although obviously lower price or free tools make it a lot > > easier to get started.) > > > > I'm resigned to following these policies and renewing licences regularly > as > > necessary - it seems unavoidable, and it is not going to influence my > choice > > of manufacturer or software. But I would love to hear if anyone has a > > reasonable explanation of why the software is "rented" rather than "sold". > > > > > > > >Article: 52881
In article <9nsk5vgm3t1q4oskv99t8a1ggkhcdnuenn@4ax.com>, jjlarkin@highSNIPlandTHIStechPLEASEnology.com says... > Hi, > > I'm considering the design of a PCI card that will use a fairly big > (400 I/Os, maybe) Xilinx FPGA and a bunch of SRAM to hold images (2D > histograms, actually). There would be a bunch of control registers in > the FPGA, and PCI block transfers to/from the dual-ported image RAM. > > The thing is, I'd like to have the PC application code be able to > configure the FPGA for various applications. So the FPGA would likely > not be the actual PCI interface, and would power up un-configured. > > So, any suggestions on an architecture? Some possibilities I've > thought of are... > > A standard PCI chip, like the AMCC or PLX parts, do the real PCI > interface, with some sort of path (maybe a little glue logic) for > initializing and configuring the FPGA. Go with the PLX chips, you won't be sorry. The 9030 is a really easy to use target interface. If you need a master the 9054 is a nice chip also, but a bit harder to use. I just did a design using the 9056, 64bit 66Mhz Master. The thing just worked, not one problem !!! For $100 you can also get PLX's SDK that has Windows/Linux drivers and source code that work very well also. If you do want to do block transfers, use a master. The 9030 is a great chip, but its not very good at moving around lots a data. If you use a master you have DMA available. On the 9030 you can use the 4 GPIO lines to program the FPGA via JTAG. All of the PLX master chips do not have any GPIO bits, so you have to stick a small CPLD between the PLX and the FPGA if you wish to program the FPGA via the PCI bus (This is my only grip with the higher end PLX chips, no GPIO and no chip selects). > A second, fix-configured FPGA or CPLD to front-end the big one, ditto. The only reason to do this would be to do what I memtioned above, to enable a PLX master chip to program the FPGA. > Partial reconfiguration somehow? Like initial config from a EEPOM, > with self-managed reconfig afterwards? Sounds nasty. See above... > Ideas welcome. And if anybody has this all worked out already, we'd > consider buying the IP. > > John -- Greg Deuerling Fermi National Accelerator Laboratory P.O.Box 500 MS368 Batavia, IL 60510 (630)840-4629 FAX (630)840-5406 Electronic Systems Engineering Group Work: egads@fnal.govArticle: 52882
yes, i agree. "Matt" <bielstein2002@attbi.com> wrote in message news:<L9D6a.229028$tq4.5093@sccrnsc01>... > Okay, sorry... :-) > Fair enough. I think my point is that ModelSim SE is their top of the line > product and that it is expected to significantly out perform their lowest > end products. A comparison to the "starter" version is comparing apples and > oranges. (Check their web site for details.) For the Windows vs. Linux > thing... not gonna get into religious wars. But if you are going there then > it makes sense to me that you compare the same product on both OS's on the > *same* hardware. > > IMHO > > Matt > > > > > "Duane Clark" <junkmail@junkmail.com> wrote in message > news:b3dmpm023qu@enews3.newsguy.com... > > Matt wrote: > > >>And as a little comparison, I recently ran a simulation of a couple > > >>thousand line program on similar machines. A simulation that under > > >>Modelsim SE/Linux took 20 seconds, required 30 minutes under Modelsim > > >>XE-Starter/Windows 2000! Yikes! > > >> > > >>... oops, are we not supposed to post benchmarks ;) > > > > > > > > > ModelSim SE (Linux) vs. ModelSim XE-Starter (Win2K)... huh? And what > > > Scientific method are claiming to use? > > > > I don't believe I made any such claim. I merely found a 90 to 1 > > difference to be rather astonishing. > > > > -- > > My real email is akamail.com@dclark (or something like that). > >Article: 52883
David Brown <david@no.westcontrol.spam.com> wrote: : I've been reading through some information about Xilinx tools (it's printed : information, so it may be a bit out of date). It seems to me that the : WebPACK is going to be perfectly sufficient for small designs, but : installation involves a number of different licences and registrations for : different parts, and at least one part needs the licence and registration : renewed every 30 days. Is this sort of thing really necessary? What is the : point? . . . . . . . . I used WebPack at work (as did a lot of other people). Once I got my Xilinx acct set up & downloaded the software, I didn't have to bother with any licensing issues again. I used WebPack for many months without a problem -- at least one involving the licensing . . . I *did* have a weird GUI bug, but that's another story. As a practical matter, once you download WebPack, you can use it forever without having to do anything with any license. It's easy and fun to get all resentful about licensing policies. I do think that companies do their utmost to gouge their customers for software. They do this when they can. However, the marginal cost of producing another copy of some software package or another is almost zero. Therefore, by the grim, iron-clad laws of capitalist economics, the cost of software will tend towards zero in the long run -- as long as there is competition. And God bless the free software movement, which is helping to accelerate this trend. The fact that WebPack is free evinces this tendency. Stuart p.s. Now when is Xilinx going to offer WebPack for Linux? And, no, I don't mean running the command line tools under Wine. . . . .Article: 52884
Xilinx iMPACT is for programming Xilinx FPGA's. I don't think you can use it for your application. You would need other JTAG tools to be able to program the flash through XC9536 JTAG interface. Jim "Markus Meng" <meng.engineering@bluewin.ch> wrote in message news:3e5a6036_4@corp.newsgroups.com... > Hi Jim, > > do you need a special tool to add the sequences for SPI clocking, or is > there a > backdoor through which you can use Xilinx IMPACT JTAG Tool to do the > stuff ... > > markus > > "Jim Wu" <jimwu88NOOOSPAM@yahoo.com> schrieb im Newsbeitrag > news:nFq6a.4972$8f7.1367@nwrdny02.gnilink.net... > > Basically you need to put the XC9536 in EXTEST mode and drive the pins > that > > are connected to the flash SPI interface according to the timing and > > sequences required in the flash spec. > > > > HTH, > > JimArticle: 52885
I seem to have run into a double-bind using COREGEN (Alliance 3.3sp6 version) to generate a ROM (for a lookup table). I can generate the ROM, and generate the .COE file to give it initial values, and all should be well for synthesis. However the simulation model needs a .MIF file... now I can generate that too, or Coregen can save one from the COE file. But reading the .MIF file into the simulation is another matter. The package to do this (mem_init_file_pack.vhd) is just a placeholder for VHDL-87/93-specific versions. To quote the book, "User’s wishing to use this feature should compile either, themem_init_file_pack.vhd87 (for VHDL-87 compilers) or the mem_init_file_pack.vhd93 (for VHDL-93 compilers) package, [...] Both packages can be downloaded from: http:\\www.xilinx.com\ipcenter " But where? I spent hours looking, even prowling ftp.xilinx.com/pub but to no avail. Or have they been deleted, since 3.3 is not exactly current? And if so, is there any other source for these files? The alternative seems to be to forget Coregen for this and use duplicated initialisation statements (for simulation) and attributes (for synthesis). Messy. If anyone knows where on the Xilinx website I can find these, I would be grateful. Thanks, - BrianArticle: 52886
"Stuart Brorson" <sdb@cloud9.net> wrote in message news:v5mt47homuiq4d@corp.supernews.com... > David Brown <david@no.westcontrol.spam.com> wrote: > : I've been reading through some information about Xilinx tools (it's printed > : information, so it may be a bit out of date). It seems to me that the > : WebPACK is going to be perfectly sufficient for small designs, but > : installation involves a number of different licences and registrations for > : different parts, and at least one part needs the licence and registration > : renewed every 30 days. Is this sort of thing really necessary? What is the > : point? . . . . . . . . > > I used WebPack at work (as did a lot of other > people). Once I got my Xilinx acct set up & downloaded the software, > I didn't have to bother with any licensing issues again. I used > WebPack for many months without a problem -- at least one involving the > licensing . . . I *did* have a weird GUI bug, but that's > another story. As a practical matter, once you download WebPack, you > can use it forever without having to do anything with any license. If that's the case, then I'm happy. I haven't yet downloaded the WebPack and looked at the exact licencing terms in it - I have only read about it (referring to version 4.1, IIRC) in a Xilinx booklet. > > It's easy and fun to get all resentful about licensing policies. I do > think that companies do their utmost to gouge their customers for > software. They do this when they can. However, the marginal cost of > producing another copy of some software package or another is almost > zero. Therefore, by the grim, iron-clad laws of capitalist economics, > the cost of software will tend towards zero in the long run -- as long > as there is competition. And God bless the free software movement, > which is helping to accelerate this trend. The fact that WebPack is > free evinces this tendency. I can understand licencing codes for paid-for software - these sorts of tools are expensive to develop, and the developers want to protect that investment. I am also quite happy with the idea of regular payment for regular upgrades. But I dislike the idea of continuous licence renewal for using the same software, and for free downloads I can't even see any benifits for the supplier. But from these replies, it looks like I don't have to worry about this for current versions of the Xilinx WebPack software. > > Stuart > > p.s. Now when is Xilinx going to offer WebPack for Linux? And, no, I > don't mean running the command line tools under Wine. . . . .Article: 52887
Hi, > I read somewhere that in the absence of other information, > Xpower assumes a data toggle rate of 12%. That number was actually 12.5% and dates from versions of the software released prior to 5.1i. Versions 5.1i and later assume a default of 0%. > Since this does > not correspond at all to my cases, I'm wondering if there > is an easy way to tell it what the real cases are that does > not involve generating huge .vcd files for different cases. There is the capability in XPower of estimating activity rates. This capability uses a probability algorithm. In versions 5.1i and later this capability is in the tool for both FPGAs and CPLDs. Prior to 5.1i the capability is only there for CPLDs. > For example, I would like it to estimate power for two cases: > 1: inputs datain* change on every clock cycle, which will cause > pretty much every node to change too. > 2: inputs datain* change once every 500 clock cycles, leaving > the device quiescent almost all the time. > > Is there some simple command I can give it to get more accurate > data out of Xpower? The command is "Tools->Estimate Activity Rates", as well as a corresponding toolbar button and accelerator key. BrendanArticle: 52888
Hello, Im programming an FPGA Virtex-E using Verilog HDL. I have used a RAM from Coregen and I instantiate it after defining data types: lut512 lutPI ( .ADDR(addr), .CLK(clk_PIPQ), .DI(PI), .WE(we_PIPQ), .DO(PId)); The question is: Can I generate a rising edge for a clk that feeds a RAM inside an always loop? Like that: always@(posege clk_index) begin we_PIPQ=0; //set LUT to read clk_PIPQ=0; clk_PIPQ=1;//Rising clk, We get PId PI=PId*V; we_PIPQ=1; //set LUT to write clk_PIPQ=0; clk_PIPQ=1;//After the rising edge, PI is written into the LUT end I have tried it and it works like the clock clk_PIPQ didnt move at all. I understand that it only cares for the ultimate value of clk_PIPQ inside the always loop. If I cant do that, How can I generate a rising clock so that I get PId and make operations with it? Thanks for your time, I appreciate your help. LauraArticle: 52889
Are you using the Webpack or some other version of the tools. In any case, you really do use a VHDL top level code and then link the lower level EDIF. I don't recall all the details but I will ask the person who did the actual coding. The easiest solution involves using the regular ISE tools. However, Webpack will work as well. The older ISE tools (pre 4.2) are a little more difficult. Again, if you can tell me which version of the tools you are using then the answer is pretty simple to implement. Scott wrote: > Thanks for your input Theron. It looks like we're going to just use > the XAPP233 UART from Xilinx and scrap the USB. > > I have been trying to understand the whole "black box" concept talked > about in the XAPP233 application note. To be honest, I am not sure > how to do that at all. I understand how to instantiate the UART Tx/Rx > in VHDL, but am confused on how to link that VHDL code to the given > macros in XAPP233. Since the marcos are EDIF I need to have my > project be an EDIF project and not a VHDL project. Im really confused > on how this is to be implemented. I dont know if you are famililar > with this particular appliation or not, but I would appreciate your > thoughts. > > Thanks again!!! > > Scott > > "Theron Hicks" <hicksthe@egr.msu.edu> wrote in message news:<b3e4ph$2iln$1@msunews.cl.msu.edu>... > > Scott, > > I am looking at a USB application myself and the nicest option I found > > is the quickUSB option from QuickUSB. They have a daughter card with a > > built-in USB 2.0 connection. The card can either go to an altera FPGA or to > > a break-out board. We are also using the spartan2e. They use a cypress > > chip (EZ-USB). There also a couple of USB source codes in opencores > > http://www.opencores.org . If I recall correctly, the full USB core takes a > > fairly big FPGA. It sounds like the real object of the project is > > compression not USB. Could you live with a standard com port to do the > > up-load and down load? I know the time to do the upload/download is > > horrible but would that do what you want for the project? If so, there are > > several good UARTs out there. (look at Xilinx for a free reliable UART. > > XAPP223) > > > > Theron Hicks > > > > > > "Scott" <scottiecs@yahoo.com> wrote in message > > news:ad642abe.0302241334.393e834a@posting.google.com... > > > I am new to FPGA's and its programming language VHDL. I am working on > > > an electrical engineering senior project and have a few questions. > > > 1.) is it possible to connect a USB device (ie a digital camera) to > > > the Spartan 2e FPGA? 2.) If it is possible, could someone give a > > > quick overview or a good resource for me to research. 3.) If not, any > > > good suggestions on how i would go about accomplishing my > > > objective(see below) > > > > > > My main goal is to connect a Digital camera directly to the FPGA board > > > to get a picture from the camera. Once the picture is loaded into the > > > FPGA memory i am going to compress that image and then send it to a > > > computer. > > > > > > Thanks in advance!! > > > ScottArticle: 52890
"Xateta" <spanishgirlinireland@yahoo.es> wrote > How can I generate a rising clock so that I get PId and > make operations with it? Don't do it like that. Clock your synchronous RAM from the same system clock (clk_index) and use a state machine to manipulate the RAM's read and write enable signals appropriately. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 52891
Stuart Brorson <sdb@cloud9.net> wrote: : David Brown <david@no.westcontrol.spam.com> wrote: : p.s. Now when is Xilinx going to offer WebPack for Linux? And, no, I : don't mean running the command line tools under Wine. . . . . One a recent and well configured wine, you can install and run Xilinx Webpack even in graphical mode, as I now to with the placer in the background :-) Only impact can't be used for actuall device programming, due the the use of hardware drivers... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 52892
David Brown <david@no.westcontrol.spam.com> wrote: : "Stuart Brorson" <sdb@cloud9.net> wrote in message : news:v5mt47homuiq4d@corp.supernews.com... :> It's easy and fun to get all resentful about licensing policies. I do :> think that companies do their utmost to gouge their customers for :> software. They do this when they can. However, the marginal cost of :> producing another copy of some software package or another is almost :> zero. Therefore, by the grim, iron-clad laws of capitalist economics, :> the cost of software will tend towards zero in the long run -- as long :> as there is competition. And God bless the free software movement, :> which is helping to accelerate this trend. The fact that WebPack is :> free evinces this tendency. : I can understand licencing codes for paid-for software - these sorts of : tools are expensive to develop, and the developers want to protect that : investment. I am also quite happy with the idea of regular payment for : regular upgrades. But I dislike the idea of continuous licence renewal for : using the same software, and for free downloads I can't even see any : benifits for the supplier. But from these replies, it looks like I don't : have to worry about this for current versions of the Xilinx WebPack : software. The economics of software is very interesting, and is not well understood, IMHO. You are right: the up-front cost of developing some software system or another can be quite high, but if the marginal cost of production is zero, then competition drives the price on the market to zero. Therefore, the question is: How can SW companies make money on producing software? I see three ways: 1. The company needs to be a monopoly of some sort or another. Micro$oft is a good example of this. 2. The company needs to continually innovate so that there is no other competitive company offering the same mix of features/abilities. (In a sense, this means that the company is again a monopoly.) 3. The company can give the software away (or sell it for cheap), and then make money on services instead. This is the Free Software model, and is also used by IBM, Computer Associates, etc. This approach makes economic sense, because the marginal cost of producing services is never zero. (That is, you need to pay the consultant who is working for the client.) On the other hand, this kind of business doesn't scale well. Ultimately, you can only bill for the number of hours worked by your staff, so you can't ramp up production to increase revenue like you can with a factory. The revenues you make only scale with the number of bodies you employ. A chip vendor like Xilinx has a fourth way to generate revenues: sell chips. Since the marginal cost of producing a chip is non-zero, they will never give the chips away. However, they can give their synthesis software away, and treat it as a loss-leader for their chips. Anyway, have fun with WebPack! StuartArticle: 52893
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: : Stuart Brorson <sdb@cloud9.net> wrote: : : David Brown <david@no.westcontrol.spam.com> wrote: : : p.s. Now when is Xilinx going to offer WebPack for Linux? And, no, I : : don't mean running the command line tools under Wine. . . . . : One a recent and well configured wine, you can install and run Xilinx : Webpack even in graphical mode, as I now to with the placer in the : background :-) Recent rev of Wine I can manage. Well configured, well . . . . that's another issue. Maybe it works for you, but it never works for me. :-( StuartArticle: 52894
Steve T Shannon wrote: > Hello! I'm hacking a FSM together (spartan-II), and I'm trying to have > an external clock and then a double-speed internal clock (multiplied > via a DLL). I'd like the FSM to transition on the rising edge of the > external (1x) clock, so I tried using the other clock to determine my > next state, but this does two different things in behavioral and > post-P&R! So, any suggestions how to have an FSM with a CLK and a 2x > CLK? > > The only thing I could think of that would be guaranteed to work would > be to use another DLL (!) to offset CLK by 90, so I can always be sure > that I'm sampling what I expect to be sampling when switching states > on the internal 2X clk. Is there a better way? You could try this, but I don't know how your synthesizer will react. process(clk) if clk'event and clk = 1 (for the rising edge of the clock) . . . if clk'event and clk = 0 ( for the falling edge of the clock) see if this works. LTArticle: 52895
Controling delay in a FPGA is almost impossible (or at least not predicatable) You can resynchronize your data on the same clock by using dual port ram (Block Ram in the virtex2). One port configured as write port with your input clock and the second port as read clock with your system clock. There is a good article from Xilinx on this issue: http://www.xilinx.com/support/techxclusives/fifo-techX18.htm Larry "Jeremy Whatley" <jeremyw@erlangtech.com> wrote in message news:v5l585suksb8bc@corp.supernews.com... > I am trying to interface a Virtex2 to an ASIC with very poor clock/data > timing. The data coming out of this ASIC is arriving as 8 distinct > channels, each with its own frequency (but not phase) related clock. There > are too many clocks for me to adjust their phases with DCMs to match the > data. I also cannot use global clock buffers for the same reason, but I do > not need to drive very many flip-flops, so skew is not an issue. > > I need to find a way to manually insert delay in my clock line. Inverting > the clock does not provide the correct phase relationship. I have tried > instantiating some AND2 primitives and placing them in the clock path, but > doing this has a seemingly random effect. Does anyone have any ideas on how > to do this? > > Thanks!!! > > Jeremy Whatley > jeremyw@erlangtech.com > >Article: 52896
Is this normal, that a blank CPLD is driving high the IO-Pin? markus -- Mit freundlichen Grüssen Markus Meng P.S. Achtung wir haben eine neue FAX-Nummer ******************************************************************** ** Meng Engineering Telefon 056 222 44 10 ** ** Markus Meng Natel 079 230 93 86 ** ** Bruggerstr. 21 Telefax 056 222 44 34 <-- NEU !! ** ** CH-5400 Baden Email meng.engineering@bluewin.ch ** ** Web www.meng-engineering.ch ** ******************************************************************** ** You cannot create experience. You must undergo it. Albert Camus** -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 52897
First, please realize that the silicon you are designing to most probably has built-in clock enables that are being unused with your current design. If you don't use (Increment_counter & Clock) to clock your counter but instead enable the always-clocked counter with Increment_counter, your design will work as expected. If your Increment_counter is generated by the same rising Clock edge as you're using to increment your counter, the combinatorial element you use will see the new Increment_counter signal while the Clock is still high which - through the AND - gives you a positive going edge even though your clock edge happened a nanosecond or two earlier. When the next rising Clock edge comes in, the Increment_counter signal is still valid for a nanosecond or two which gives you a very narrow pulse from your AND. Go synchronous and use an enabled counter. If you must use a combinatorial form, consider using an OR gate with the invert of the Increment_counter signal. You can still use the same rising edge for your counter and for generating the gating signal but by using the OR, the only time the negative going pulse happens in the middle of the gate, not at the edges. Synchronous clocks are good. Very good. "bams" <bamini222@yahoo.com> wrote in message news:4306d0af.0302241646.650b62eb@posting.google.com... > I am having a problem in a schematic design.I am using a 8 bit counter > output to the address bus of a 256X16 RAM.My basic logic is to search > for a given 16bit data in the RAM.I have a increment_counter flag > from my controller. I and Increment_counter and Clock and connected it > to the clock of the counter.The idea behind is that when > increment_counter goes high i should increment the register address.To > my dismay whenever the counter is gerting the clock it is > incrementing twice.i.e when the counter gets the clock it is going > from 00 to 01 at clock first clock pulse and from 01 to 02 at second > clock pulse though increment_counter is 0 at the second clock pulse.i > couldn't figure out why it is doing like that? > > --PraveenArticle: 52898
> I need to find a way to manually insert delay in my clock line. Inverting > the clock does not provide the correct phase relationship. I have tried > instantiating some AND2 primitives and placing them in the clock path, but > doing this has a seemingly random effect. Does anyone have any ideas on how > to do this? I remember that I once saw a research paper that described how the authors calibrated ring oszillators in a FPGA. They manuelly placed and routed a macro in the FPGA editor. Than they used JBITs to add fanouts to the routing during runtime. Doing this they could add delay in chunks of a few hundred picoseconds. Sorrry, I do not have a pointer to the paper, nor do I now the names of the authors. Kolja SulimmaArticle: 52899
Hi guys, I have a question about initializing multi-ported memories for Altera using a MIF file. The MIF file starts with the DEPTH and the WIDTH of the memory, but what should these be if I have a RAM with different sized ports? Can I just take the depth and width of any port (with corresponding initialization values) or are there rules for this? Any help appreciated, Regards, Johan
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