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Hi, I am targetting my design to Xilinx Virtex2-6000. I have the following = warning after I syntesize my design : WARNING: found 571 physical components for which 100% back-annotation is = not possible simulation models for these components will be constructed from the NCD. Why I've got this message (as most of my component are taken from = Xilinxcorelib) ? How to verify my design ? especially the verification with delay = information. Pld gimme your hands. Thanks. Best regards, BasukiArticle: 52926
Hi, I'm lookin for someone who has some experience with Jbits tool , especially the genetic hardware part. I need help with some examples provided with the Genetic FPGA classes from the Jbits library. I can't get work the examples named Prec1x1, 2x2 ... and following I work with the virtex simulator VirtexDS configured as the XCV100 board. The compiler says that the CoreTemplate class throws the exception : "Device XCV50 was specified, but Device XCV1000was targetted". I wonder if the genetic FPGA is able to work with another board than the Rc1000pp board (XCV1000). If i configure my virtexDS as XCV1000 then the compiler says a little farther that it could not load the SRAM onto the device. If you have succeeded to make it work yourself, please help me !!! A+.PanzoArticle: 52927
Hello, On Xilinx site, they seem to have release version 5.2 of their outstanding ISE tools, for the CD version. Yet the ISE Webpack is still in v5.1 SP3. Does anyone know whether it will be available for download in v5.2? And by the way, what are main new features of this release? Yours, FBArticle: 52928
> What we want to do is to use a nand-flash device to configure the fpga to > further reduce cost plus the nand flash can also be used as a mass storage > device. The idea is to use a 16 bit flash , 8 bits containing the > configuration code, 6 bits to do error correction (nand flash is not > garanteed error free). The error correction and the nandflash interface > could be handled by a cpld. An interesting idea. I thought about the same for an Altera FPGA (Cyclone) board. The problem is similar for X and A. But in a nand-flash you have complete bad blocks. This makes logic in the CPLD pretty complex. I decided to go the 'convential' way with a very small CPLD (MAX7064) and a 4Mbit flash for configuration and some application data and an optional nand-flash. Both flash are programmed via the FPGA. The additional flash is cheaper than a more complex CPLD. You can find schmatic and VHDL details at: http://www.jopdesign.com/index.html Martin SchoeberlArticle: 52929
Xilinx update their tool so fast! "Frederic Bastenaire" <fba@free.fr> wrote in message news:d977c973.0302260333.4088db0@posting.google.com... > Hello, > > On Xilinx site, they seem to have release version 5.2 of their outstanding ISE > tools, for the CD version. > Yet the ISE Webpack is still in v5.1 SP3. > Does anyone know whether it will be available for download in v5.2? > And by the way, what are main new features of this release? > > Yours, > > FBArticle: 52930
Hello, thank you very much. It works now. I had tried it last week too, but i had probably made something wrong. with best regards StefanArticle: 52931
I need to know the detail arch. (hw) of the fgpaArticle: 52932
Hi all,
I am designing a PCB based on a Xilinx SpartanII FPGA (XC2S100 - TQFP144
package) and on an AVR Microcontroller. A clock of 8 Mhz will be used. In
this frequency are high frequency bypass capacitors necessary?
Furthermore, I would like to configure I/O pins in that way so as to be
compatible with the LVCMOS2 Standard. I read in the SpartanII datasheet that
the only requirement is to connect Vcco pins to a 2.5 Volts Voltage. Is
there any other requirement even in the VHDL level (something for libraries
(IBUF symbols) is mentioned in the datasheet)?
Article: 52933On 26 feb 2003, you wrote in comp.arch.fpga: >> What we want to do is to use a nand-flash device to configure the >> fpga to further reduce cost plus the nand flash can also be used as a >> mass storage device. The idea is to use a 16 bit flash , 8 bits >> containing the configuration code, 6 bits to do error correction >> (nand flash is not garanteed error free). The error correction and >> the nandflash interface could be handled by a cpld. > > An interesting idea. I thought about the same for an Altera FPGA > (Cyclone) board. The problem is similar for X and A. But in a > nand-flash you have complete bad blocks. This makes logic in the CPLD > pretty complex. I decided to go the 'convential' way with a very small > CPLD (MAX7064) and a 4Mbit flash for configuration and some > application data and an optional nand-flash. Both flash are programmed > via the FPGA. The additional flash is cheaper than a more complex > CPLD. You can find schmatic and VHDL details at: > http://www.jopdesign.com/index.html > > Martin Schoeberl > > > > The idea was to move the complexity to the nand-flash programming software. What you then could do is use the last bytes (nand page = (256 + 8) x 16 bits) to build some kind of linked list. These last bytes would contain the address of the next 'valid' block. Then the cpld statemachine only has to update his address pointer after each block read. Jo KenensArticle: 52934
"Peter Tawdross" <tawdross@rhrk.uni-kl.de> wrote > I need to know the detail arch. (hw) of the fgpa FGPA is a new abbreviation for the familiar American educational concept of F****d-up Grade Performance Average. Its hardware architecture is characterised by very high densities of beer and parties, a complete absence of textbooks, and extremely limited routing resources between student accommodation and lecture halls. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 52935
Stamatis Sotiropoulos <ssothro@hotmail.com> wrote: : Hi all, : I am designing a PCB based on a Xilinx SpartanII FPGA (XC2S100 - TQFP144 : package) and on an AVR Microcontroller. A clock of 8 Mhz will be used. In : this frequency are high frequency bypass capacitors necessary? Yes, as internal switching and the edges of signals going off chip are still fast. Using SLOW output slew rate (which is default with webpack) somehow relaxes things. : Furthermore, I would like to configure I/O pins in that way so as to be : compatible with the LVCMOS2 Standard. I read in the SpartanII datasheet that : the only requirement is to connect Vcco pins to a 2.5 Volts Voltage. Is : there any other requirement even in the VHDL level (something for libraries : (IBUF symbols) is mentioned in the datasheet)? Nothing more needed. I normally let XST infer the IOBUFs and only contrain the IO standard of the pins in question with the constraints file. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 52936
Peter, how about following to find out about FPGAs: 1) from your email-address I gather that you're attending a uni 2) From that I assume you passed school and are able to read. If we now assume that item 2) is true (I could be wrong and that could mess up the complete theory) then you could do exactly that. Read it. You found this forum so you probably are able to find the vendors doing FPGAs and there you can find lot of information. But I don't think anyone in here is going to do your homework. FritzArticle: 52937
I need all the hardware details "Jonathan Bromley" <jonathan@oxfordbromley.u-net.com> schrieb im Newsbeitrag news:b3ih3v$op3$1$8300dec7@news.demon.co.uk... > "Peter Tawdross" <tawdross@rhrk.uni-kl.de> wrote > > > I need to know the detail arch. (hw) of the fgpa > > FGPA is a new abbreviation for the familiar American > educational concept of F****d-up Grade Performance > Average. Its hardware architecture is characterised > by very high densities of beer and parties, a complete > absence of textbooks, and extremely limited routing > resources between student accommodation and lecture halls. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK > Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com > Fax: +44 (0)1425 471573 Web: http://www.doulos.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. > > >Article: 52938
Hallo, Are the PROGRAM (input) and DONE (tri-state) pins in Spartan2 5V tolerant? Regards, Pawel J. RajdaArticle: 52939
u means u need the vhdl code to convert from ps2 input to parallel output? "bams" <bamini222@yahoo.com> schrieb im Newsbeitrag news:4306d0af.0302232303.3dba3d88@posting.google.com... > I want to know how to interface a keyboard to xilinx fpga(spartan xcs10pc84) > board.? > > --bamsArticle: 52940
I beleive u need a rs-flipflop (glatch) in with with maxterm at each of the set and reset. "Kyle Davis" <kyledavis@nowhere.com> schrieb im Newsbeitrag news:Ibg6a.1536$PM4.84557984@newssvr14.news.prodigy.com... > From what I learn, you can eliminate Static 1 hazard by circle-ing minterm > including the redundant one. You can eliminate static 0 hazard by circle-ing > the maxterm including the redundant one. But is there any way that I can > eliminate both static 1 and static 0 hazard without creating seperate > circuits for each hazard? > >Article: 52941
Hi, How I can program an Altera EPC1 with a ByteBlaster cable? I want to do an adapter to program it, but I canīt find any document with the eprom program method. I have not an external programmer. Can anybody help me? Thanks.Article: 52942
Bams, This topic has come up before. ISE does automatically creates VHDL or Verilog file for you. Please take a look in your project folder and you should find either VHF(equivalent of VHD) or VF(verilog) file. Regards, Wei bams wrote: > I know that altera Maxplus has option of giving a VHDL code for a > schematic design,do xilinx has this option.If it has, I am curious to > know how i can generate a VHDL code from a schematic design?(It is not > part of any homework or a project as some feared ...) > > with regards, > bmsArticle: 52943
"Jo Kenens" <(no_spam)Jo(no_spam).ken(no_spam)ens@acunia.com> schrieb im Newsbeitrag news:Xns932E9544CAADnospamJonospamkennos@195.129.110.155... > On 26 feb 2003, you wrote in comp.arch.fpga: > > >> What we want to do is to use a nand-flash device to configure the > >> fpga to further reduce cost plus the nand flash can also be used as a > >> mass storage device. The idea is to use a 16 bit flash , 8 bits > >> containing the configuration code, 6 bits to do error correction > >> (nand flash is not garanteed error free). The error correction and > >> the nandflash interface could be handled by a cpld. > > > > An interesting idea. I thought about the same for an Altera FPGA > > (Cyclone) board. The problem is similar for X and A. But in a > > nand-flash you have complete bad blocks. This makes logic in the CPLD > > pretty complex. I decided to go the 'convential' way with a very small > > CPLD (MAX7064) and a 4Mbit flash for configuration and some > > application data and an optional nand-flash. Both flash are programmed > > via the FPGA. The additional flash is cheaper than a more complex > > CPLD. You can find schmatic and VHDL details at: > > http://www.jopdesign.com/index.html > > > > Martin Schoeberl > > > > > > > > > > The idea was to move the complexity to the nand-flash programming > software. What you then could do is use the last bytes (nand page = (256 > + 8) x 16 bits) to build some kind of linked list. These last bytes would > contain the address of the next 'valid' block. Then the cpld statemachine > only has to update his address pointer after each block read. > > Jo Kenens So you assume that the first page is a good block (chances are high). Your idea is good, perhaps we can work on it together. What complexity of PLD do you expect? I expect you will need a 128 LC part. So it will get e a little bit more expensive: MAX7064 bout $6, AMD Flash $4 but a MAX7128 is about $13 (all prices on single pieces, but ok for comparison). But you can save a little bit of board space. MartinArticle: 52944
In article <b3iing$pht$1@news.uni-kl.de>, Peter Tawdross <tawdross@rhrk.uni-kl.de> wrote: >I need all the hardware details Its built of Kegs, Plastic Cups, Togas, and Cheerleader uniforms (on guys). -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 52945
Anyone know how/where to get hold of a Xilinx Coolrunner-II dev kit ($49) in the UK please? The Xilinx web store is out of stock. The offical distrbitutor for the UK (Insight Memec) only seems to sell it in the U.S. Many thanks.Article: 52946
You are right, actually I used the day to: -- verify that the CPLD is operating correctly -- The Spartan-II device that is on my boards are all from a production slot that seems to have an error, or a problem or both ... The following happens: Production and Device Code first: (- reading what the label on top is saying ...) XC2S200 FG2565AFP0109 D1162963A 5C Actually I'am using the FPGA in Master Serial Mode. However the Configuration EEPROM is not present at the moment. The following happens - on all boards ... 1.) The FPGA is trying to read in the bitstream code - master serial mode 2.) No valid code is available, however some IO's are driven high, like configured... 3.) When I configure the device through JTAG, the device seems to work, however now I have the egg and the 'Huhn' problem. I processor should start to work and to update the configuration EEPROM, which is empty at the moment. The processor can't start-up correctly because for any kinf of reason some of the IO's are driven even without a configuration ... Well that's all for the moment, it sounds a little bit strange, but that's what I measure and I can reproduce ... If someone else had a similar problem I would appreciate to hear about it ... markus "Falser Klaus" <kfalser@IHATESPAMdurst.it> schrieb im Newsbeitrag news:MPG.18c68a5ad4ce5d62989693@151.99.250.3... > In article <3e5b9ae9$1_4@corp.newsgroups.com>, meng.engineering@bluewin.ch says... > > Is this normal, that a blank CPLD is driving high the IO-Pin? > > > > markus > > > > Yes, if you look at the data sheet for the 9500XL family (table 5), > you can see that the IOB-Bus hold circuitry does a pull-up even for the > erased device. > > Best regards > > -- > Klaus Falser > Durst Phototechnik AG > kfalser@IHATESPAMdurst.it -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 52947
Stamatis Sotiropoulos wrote: > > Hi all, > I am designing a PCB based on a Xilinx SpartanII FPGA (XC2S100 - TQFP144 > package) and on an AVR Microcontroller. A clock of 8 Mhz will be used. In > this frequency are high frequency bypass capacitors necessary? > As has been mentioned here many times: Decoupling capacitors are needed to support the short rise and fall times inside and outside the chip. The clock frequency has almost nothing to do with that. So, yes, you need good decoupling even at 8 MHz ( or even at 100 kHz clock rate). Peter AlfkeArticle: 52948
Peter, go to the library or on the web, and RTFM ( Read The Manuals ). Might keep you busy for a while and improve your education... Peter Alfke ================= Peter Tawdross wrote: > > I need all the hardware details > > "Jonathan Bromley" <jonathan@oxfordbromley.u-net.com> schrieb im Newsbeitrag > news:b3ih3v$op3$1$8300dec7@news.demon.co.uk... > > "Peter Tawdross" <tawdross@rhrk.uni-kl.de> wrote > > > > > I need to know the detail arch. (hw) of the fgpa > > > > FGPA is a new abbreviation for the familiar American > > educational concept of F****d-up Grade Performance > > Average. Its hardware architecture is characterised > > by very high densities of beer and parties, a complete > > absence of textbooks, and extremely limited routing > > resources between student accommodation and lecture halls. > > -- > > Jonathan Bromley, Consultant > > > > DOULOS - Developing Design Know-how > > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services > > > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, > UK > > Tel: +44 (0)1425 471223 mail: > jonathan.bromley@doulos.com > > Fax: +44 (0)1425 471573 Web: > http://www.doulos.com > > > > The contents of this message may contain personal views which > > are not the views of Doulos Ltd., unless specifically stated. > > > > > >Article: 52949
Hi all, sorry for all this self conversation... Here the results I stop now ... Fact: Dont try to configure through master serial mode when there is no bitstream available. It may produce erratic behavior even if a checksum should prevent this ... I now changed everything for the FPGA to slave serial mode, and what happens ... nothing happens anymore all 'not configured' IO's behave as expected, and the processor subsystem is working ... Now I suppose that with some production versions of Spartan-II there seems to be a configuration problem in mater serial mode with a non valid bitstream - ie. no bitstream ... have a nice day markus "Markus Meng" <meng.engineering@bluewin.ch> schrieb im Newsbeitrag news:3e5cec89$1_4@corp.newsgroups.com... > You are right, > > actually I used the day to: > > -- verify that the CPLD is operating correctly > -- The Spartan-II device that is on my boards are all from a production > slot that seems to have an error, or a problem or both ... > > The following happens: > > Production and Device Code first: > (- reading what the label on top is saying ...) > > XC2S200 > FG2565AFP0109 > D1162963A > 5C > > Actually I'am using the FPGA in Master Serial Mode. However the > Configuration EEPROM is not present at the moment. The following > happens - on all boards ... > > 1.) The FPGA is trying to read in the bitstream code - master serial mode > 2.) No valid code is available, however some IO's are driven high, like > configured... > 3.) When I configure the device through JTAG, the device seems to work, > however > now I have the egg and the 'Huhn' problem. I processor should start to work > and to update the configuration EEPROM, which is empty at the moment. > The processor can't start-up correctly because for any kinf of reason some > of the IO's are driven even without a configuration ... > > Well that's all for the moment, it sounds a little bit strange, but that's > what I > measure and I can reproduce ... > > If someone else had a similar problem I would appreciate to hear about it > ... > > markus > > "Falser Klaus" <kfalser@IHATESPAMdurst.it> schrieb im Newsbeitrag > news:MPG.18c68a5ad4ce5d62989693@151.99.250.3... > > In article <3e5b9ae9$1_4@corp.newsgroups.com>, meng.engineering@bluewin.ch > says... > > > Is this normal, that a blank CPLD is driving high the IO-Pin? > > > > > > markus > > > > > > > Yes, if you look at the data sheet for the 9500XL family (table 5), > > you can see that the IOB-Bus hold circuitry does a pull-up even for the > > erased device. > > > > Best regards > > > > -- > > Klaus Falser > > Durst Phototechnik AG > > kfalser@IHATESPAMdurst.it > > > > > -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- > http://www.newsfeeds.com - The #1 Newsgroup Service in the World! > -----== Over 80,000 Newsgroups - 16 Different Servers! =----- -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----
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