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Bassman59a@yahoo.com (Andy Peters) wrote in message news:<9a2c3a75.0302191641.7a06b3ef@posting.google.com>... > akshaymishra@rediffmail.com (Akshay) wrote in message news:<937606cb.0302170535.2347978a@posting.google.com>... > > 1) Does the synthesis tool give you any errors or warnings? > > 2) The multiplier may be eating up a lot of area, and you may not be > meeting timing. What's your clock speed? Have you set any timing > constraints? Are you meeting the constraints? > > -ap If I simplify as to what is desired: output<= coef1*y(1) - coef2*y(2); y(2)<=y(1); y(1)<=output; in other words an IIR Filter. giving the above sequence in a single process, i don't get anything. the synthesizer gives no warnings and says all constraints were met. the clock period was kept at 30ns. giving the code in two separate processes with the first process dependent upon clock and the second upon output also fails. the initializations are proper and i have got the vhdl simulation working fine. thanx, akshay.Article: 52751
Has anyone out there succesfully operated the TRUELVDS receivers on the APEX II at 1GHz? Given the derating of the flexible LVDS pins, I would be much happier if I knew that someone else had managed to get the TRUE pins working at full spec. Thanks in advance. Robert Hamilton.Article: 52752
If you just dig deep enough, it's hot even in Norway, or underneath the North Sea :-) Peter Alfke ==================== Petter Gustad wrote: > > Peter Alfke <peter@xilinx.com> writes: > > > when I read "highest temperature" and "Norway", I assume this is for a > > High temperature and Norway - to me it sounds like a contradiction :-) > > Petter > -- > ________________________________________________________________________ > Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 52753
"Xateta" <spanishgirlinireland@yahoo.es> wrote in message news:<b32fqf$uce$1@peque.uv.es>... > There is not an error,just the warnings bellow > I saw the Synthesis Report as well:no errors > > What is exit code 0002? > (Done: failed with exit code: 0002.) It looks like you are missing signals in a sensitivity list. This causes the synthesizer to infer one or more latches that Xilinx may not like. Do you REALLY mean to infer latches? John P.Article: 52754
I'm driving clock buffer BUFGS with combinatorial logic (multiplexer output -> BUFGS). No mather what I do I always see a warning: >Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic. As seen from floorplanner the signal is corectly routed to BUFGS. Should I ignore the warning? Is it necesary to set attribute clock_signal? (It doesn't make any difference) Thanks for any help. jOc [VHDL] architecture mux_cntrl of mux_cntrl is signal nWE,nOE:std_logic; attribute clock_signal : string; attribute clock_signal of nWE : signal is "yes"; attribute clock_signal of nOE : signal is "yes"; component BUFGS port (I: in std_logic; O: out std_logic); end component; begin nWE<=CEP_nWE when CEP_nPCI='1' else pci_nWE; nOE<=CEP_nOE when CEP_nPCI='1' else pci_nOE; --mux nBE(3:0) i_nBE<=CEP_nBE when (CEP_nPCI='1' and i_nBE_cntrl='0') else "0000" when (CEP_nPCI='1' and i_nBE_cntrl='1') else pci_nBE; U1: BUFGS port map (I => nWE, O => i_nWE); U2: BUFGS port map (I => nOE, O => i_nOE); [WEBPACK warning // WepPack 4.2] -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ u1_I_pci_lholda__n0004:O | NONE(*)(u1_pci_lholda) | 9 | u15_u2:o | NONE(*)(u13_plx_rd_6) | 35 | u15_u1:o | NONE(*)(u0_reg_08_0) | 109 | gck2 | BUFGP | 113 | -----------------------------------+------------------------+-------+ (*) These 3 clock signal(s) are generated by combinatorial logic, and XST is not able to identify which are the primary clock signals. Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.Article: 52755
ZX,
Try killing all quartus processes from the Task Manager. The processes
are quartus and quartus_cmp. You should not have to reinstall Windows.
- Subroto Datta
"ZX" <ZX@TheEmail.com> wrote in message
news:b32ktu$2fs7$1@news.adamastor.ac.za...
> Have anyone else had this problem? Or does anyone have a possible
solution?
>
> This morning Quartus II (Ver 2.1 SP1 for PC) decided to stop compiling.
> Whenever I click on "Start Analysis & Synthesis" or "Start Compilation" or
> use the menu commands to do the same, the compiler start to initialize and
> then ends with the message "Netlist Extraction and synthesis was NOT
> successive" but the actual compilation has never started and there are no
> error messages or warnings in the messages window.
>
> This happens for ALL designs (the tutorials that came with Quartus, some
old
> designs that I haven't touched in a few months and some small test-designs
I
> created to test what is going on) and it seems to happen for all device
> selections too. I'm not using any third party EDA tools so this is a
Quartus
> problem.
>
> A full uninstall (and registry wipe) and then reinstallation didn't solve
> the problem. The only other solution I can think of (while I wait for
Altera
> to respond to my service request) is to reinstall windows, but I really
> don't want to do that unless it is absolutely necessary!
>
> Please let me know if you have any ideas to solve this issue!
>
> Regards
> ZX
>
>
Article: 52756John Providenza <johnp3+nospam@probo.com> wrote in message 349ef8f4.0302200752.5afcc655@posting.google.com... > Here's code I've been using for several months with the 4.X web pack. > Thanks!!!Article: 52757
Hi No I only have one TCP/IP interface. Quartus WAS working fine and then suddenly it just stopped. Nothing has changed on the PC hardware-wise or software-wise and it's not a license error either because other computers on the network can still run quartus. Thanx for your input tho. Regards ZX "Thorsten Bunte" <t.bunte@beckhoff.de> wrote in message news:b32plj$1ic1ki$1@ID-22362.news.dfncis.de... > Hi, > > do you have two active TCP/IP ethernet NICs? If so, disconnect one cable or > disbale TCP/IP binding to one of the cards. > > Thorsten > "ZX" <ZX@TheEmail.com> schrieb im Newsbeitrag > news:b32ktu$2fs7$1@news.adamastor.ac.za... > > Have anyone else had this problem? Or does anyone have a possible > solution? > > > > This morning Quartus II (Ver 2.1 SP1 for PC) decided to stop compiling. > > Whenever I click on "Start Analysis & Synthesis" or "Start Compilation" or > > use the menu commands to do the same, the compiler start to initialize and > > then ends with the message "Netlist Extraction and synthesis was NOT > > successive" but the actual compilation has never started and there are no > > error messages or warnings in the messages window. > > > > This happens for ALL designs (the tutorials that came with Quartus, some > old > > designs that I haven't touched in a few months and some small test-designs > I > > created to test what is going on) and it seems to happen for all device > > selections too. I'm not using any third party EDA tools so this is a > Quartus > > problem. > > > > A full uninstall (and registry wipe) and then reinstallation didn't solve > > the problem. The only other solution I can think of (while I wait for > Altera > > to respond to my service request) is to reinstall windows, but I really > > don't want to do that unless it is absolutely necessary! > > > > Please let me know if you have any ideas to solve this issue! > > > > Regards > > ZX > > > > > >Article: 52758
What a tempest in a teapot! Just one tiny nosy question, and Altera blows up... The original request was for a • low-performance, • low-volume, • not cost-sensitive application • at high temperature extremes. In this case, it would be silly and irresponsible to go for the cheapest, barely available product family. Proper risk management calls for something mature and with a proven track record in a hostile environment. I often compare the life of an IC family with the life of a human being, and the IC gets obsolete fifteen times faster than a human ages. So, an IC family that was first announced 2 years ago is now like a 30-year old, at the prime of its strength, and readily available to face any task. A family announced 4 years ago, is now like a 60-year old senior citizen, wise and experienced, but often not competitive for the most demanding tasks. A 6-year old IC family is like a 90-year old grand-daddy, and should be fondly remembered, but not used for new designs. The younger families are so much better... This refers to design ins, not availability or reliability. We keep our parts in manufacturing often for 10 years. And, unless overstressed, ICs live and perform for 20 years and more. Peter Alfke ============== Fredrik wrote: > > Hi Peter and David. > Is Cyclone realy abvalible it is! That a cheep shoot Peter and not > worhy comming from a competitor to Altera (contact some of your > customers if you would like to see one :) <snip>.......Article: 52759
Hello.. What other tools are currently available that will simulate designs created using CUPL (Atmel WinCupl). Atmel supplies a tool call WinSim, which leaves much to be desired. Does ModelSim,etc recognize the output format(s) of CUPL? Your thoughts would be appreciated.. Thanks.. Jim -- Jim Flanagan Raytheon,Inc. james_r_flanagan@raytheon.comArticle: 52760
"Joze Dedic" <joze.dedic@fe.uni-lj.si> schrieb im Newsbeitrag news:b3339v$f4p$1@planja.arnes.si... > I'm driving clock buffer BUFGS with combinatorial logic (multiplexer > output -> BUFGS). > No mather what I do I always see a warning: > >Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) > generated by combinatorial logic. > As seen from floorplanner the signal is corectly routed to BUFGS. > Should I ignore the warning? Is it necesary to set attribute clock_signal? > (It doesn't make any difference) > Thanks for any help. If a clock is generated by a combinatorical logic, it can inhibit glitches. If the combinatorical logic is just a quasi static mux for clock selection, an the incomming clocks to the mux are clean, everything is OK. But take care when switching between the clock, this can cause glitches too if done impropper. -- MfG FalkArticle: 52761
In my Spartan2 design, I am using BRAMs as a synchronous FIFO, and I have tied their enable inputs true for the read port. As a result, Modelsim gives me lots and lots of warnings like: # ** Warning: */RAMB4_S4_S4 SETUP High VIOLATION ON CLKB WITH RESPECT TO CLKA; # Expected := 0.01 ns; Observed := 0 ns; At : 8821.04 ns # Time: 8821040 ps Iteration: 2 Instance: /adctrigger/server/uut/u10/adcdatafifo/bram_gen__0/bram # ** Warning: */RAMB4_S4_S4 SETUP High VIOLATION ON CLKA WITH RESPECT TO CLKB; # Expected := 0.01 ns; Observed := 0 ns; At : 8821.04 ns # Time: 8821040 ps Iteration: 2 Instance: /adctrigger/server/uut/u10/adcdatafifo/bram_gen__0/bram # ** Warning: Attempting to read some or all of contents of address 0000000000 from port A while writing from port B in instance * # Time: 8821040 ps Iteration: 2 Instance: /adctrigger/server/uut/u10/adcdatafifo/bram_gen__0/bram My design works fine, I'm not really trying to read and write the same location simultaneously, but I would like to get rid of all these distracting warnings if possible. Does anyone know of a switch for vsim, or anything else that might disable these warnings? TIA, Barry BrownArticle: 52762
Hi Steve, > The USER1 and USER2 Jtag commands have nothing with the rdbk symbol or > function. Yes, I know, I just meant I wanted to know more about that both issues: JTAG USER commands and readback. > One of the commands is the USER commands. These will allow you to read and > write to an internal register that you hook up to the BSCAN symbol. OK, but I would like to see a simple example... >You can use the player but it is simple to use the Jtag interface if you read up on > it a little. It is a 16 tap state machine with TMS and TCK controling which > state you are in. TDI and TDO are the data in and out. When can I find a clear and simple tutorial on this? > > TI has a nice little demo and simulator for Jtag. I think it is at... > http://www-s.ti.com/sc/psheets/satb002a/satb002a.zip > Very interesting interactive demo! > Steve Thank you for your help, FredericArticle: 52764
All, Calyptech has released a tool for entering the footprints on large Virtex-II FPGA designs. Features include: * Net name entry through a spreadsheet interface * Generation of UCF file for implementation tools * Support for all Virtex-II family packages * Basic checking of footprint validity including differential pin names correctly assigned, no assignments to illegal pins and reporting on use of dedicated pins such as clocks. The tool is intended to simplify the task of optimising an FPGA pin-out to aid in PCB layout. This is provided as-is for use by anyone and any feedback is welcome via the email address provided on the download web-page. The tool uses a spreadsheet interface for pin entry. Goto the following address for more information and to download: http://www.calyptech.com/products_fpgatool.htm regards, Chris Rosewarne Design EngineerArticle: 52765
Hi Paul, Have you ever seen this done (even outside of a commercial setting) ? I would be interested in seeing the circuit that implements this. Charge pumps are switched cap circuits, so you would need to have a clock in order to implement a transmition gate ? Anyhow why would anyone do this rather than just use a transmition gate (with a n-ch and p-ch transistor), or, if they really dont want to use a pass- gate, use a pull-up/bleeder transistor like the ones used in some dynamic logic circuits ? As far as I know charge-pumps are generally only used in digital circuits in order to generate the high(-er than supply) voltage necessary for programming (E)PROM, or maybe level shifting (like for interfacing to a computer serial port if you dont have 12v supply on your board). Ljubisa Bajic, VLSI Design Engineer, Oak Technology, Teralogic Group "Paul Leventis \(at home\)" <paul.leventis@utoronto.ca> wrote in message news:<GC45a.21129$b8v1.5651@news04.bloor.is.net.cable.rogers.com>... > If I understand your question, then it's when you overdrive the gate a pass > transistor to make sure it *really* turns on. > > The big problem with pass-transistor logic is that you get a Vth drop across > an nmos pass transistor when you drive through it. This degrades the signal > passing through the pass gate, causing reduced performance. There are also > power implications. However the voltage drop is relative to the value > applied to the gate. By driving the gate with a higher voltage than you use > for the signal that is passing through the pass gate, you reduce the > magnitude of the degradation -- potential completely removing it, if you can > tolereate voltages that high. > > The cons are that you need to generate this higher gate voltage (you now > have two different Vcc values) off chip or on chip via charge pumps. And > you need to route an extra power network. And most importantly, the amount > you can overdrive your gates by depends on the process technology you are > using -- the stronger your overdrive, the more likely you will run into > reliability issues with the transistor. > > Do companies do this? I don't know and/or can't say :-) > > Regards, > > Paul > > "digari" <digari@dacafe.com> wrote in message > news:e0855517.0302190344.5bce1783@posting.google.com... > > What is gate boosting? what are the pros and cons of the technology? > > Does is it being used in any FPGA device?Article: 52766
David, You mentioned possibly needing a microcontroller in your application. I work in the embedded processor group at Altera, and I can't really address the device tempurature issues, but I can give you advice regarding the Nios processor. First off, Nios is delivered as part of an embedded system development kit. Several new kits were just announced, so soon you'll have your choice of Stratix, Cyclone, or APEX based dev kits. Our baseline kit goes for $995, and includes a board, power supply, cables, compiler & debugger (GNU), hardware tools (Quartus), complete documentation, and several reference designs (with source). See the Altera web site for literature including tutorials, user guides, data sheets, application notes, and more. Nios is flexible enough for a very wide range of applications, but some of the more common ones include: state machine replacement, I/O processing, MCU replacement (16 or 32-bits), and custom MCUs (imagine taking a requirement for 6 UARTs to Motorola. With Nios it's easy). Nios is differentiated from other soft processor solutions in several ways: 1) ease of use - uses a simple GUI used to build custom systems. With 3 years of consistent improvement based on user feedback, SOPC Builder is the easiest possible way to create custom SOCs. 2) flexibility - Nios is highly configurable. Even the CPU has a 32- or 16-bit user selected data path. With dynamic bus sizing, instruction set extensions, custom multi-master data paths, and many other size/performance trade off settings, you should be able to create your optimal system. 3) performance - Nios runs at well over 100MHz in Stratix and Cyclone devices, and contains performance features not offered by competing solutions: custom instructions, DMA engines, hardware accelerator blocks, instruction & data cache, 100MHz+ SDRAM execution, and more. 4) price - Nios and Cyclone provide a perfect cost reduction tandem. Comparing effective LE costs versus discrete MCUs, a 32-bit Nios system implemented on a Cyclone device forms an extremely cost effective solution. Visit www.altera.com/nios to learn about the $2 RISC processor. Finally, Nios has been shipping to customers since late 2000, with many thousands of licensed design seats active today. It is very stable and very widely accepted. Don't take my word for it though. Poll the newsgroup for opinions of Nios. I'd be happy to answer any questions you might have. Alan Calac Embedded Systems Altera Petter Gustad <newsmailcomp4@gustad.com> wrote in message news:<m37kbvnzzv.fsf@scimul.dolphinics.no>... > "David Brown" <david@no.westcontrol.spam.com> writes: > > > be very interesting to look at soft cpus. Speed is not really an > > issue, but temperature is - we would like components rated as high a > > temperature as possible. > > I would investigate the temperature issue. Contact Memec (Xilinx) and > EBV or Arrow (Altera). The Memec Xilinx FAE is very knowledgeable. The > EBV guys are very helpful and good at getting you in contact with the > right people at Altera. > > I'm working on the larger devices where there are multiple engineers > working on the same design. Most of our tools runs under Linux, e.g. > Synopsys VCS, Synopsys DC, Cadence signalscan, etc. For our > environment Altera fits better since the Quartus tools runs under > Linux (without Wine emulation). But if you're using Windows in a > one-engineer-one-design this is not an issue. > > PetterArticle: 52767
"Paul Leventis \(at home\)" <paul.leventis@utoronto.ca> wrote in message news:<GC45a.21129$b8v1.5651@news04.bloor.is.net.cable.rogers.com>... > If I understand your question, then it's when you overdrive the gate a pass > transistor to make sure it *really* turns on. > > The big problem with pass-transistor logic is that you get a Vth drop across > an nmos pass transistor when you drive through it. This degrades the signal > passing through the pass gate, causing reduced performance. There are also > power implications. However the voltage drop is relative to the value > applied to the gate. By driving the gate with a higher voltage than you use > for the signal that is passing through the pass gate, you reduce the > magnitude of the degradation -- potential completely removing it, if you can > tolereate voltages that high. > > The cons are that you need to generate this higher gate voltage (you now > have two different Vcc values) off chip or on chip via charge pumps. And > you need to route an extra power network. And most importantly, the amount > you can overdrive your gates by depends on the process technology you are > using -- the stronger your overdrive, the more likely you will run into > reliability issues with the transistor. > > Do companies do this? I don't know and/or can't say :-) > > Regards, > > Paul > Some what off topic If you refer to other meaning of gate boosting, please ignore When we were all doing NMOS, and CMOS was for those calculator/watch people, almost everyone used this gate boosting technique esp DRAMS & high speed SRAMs. I refer you to the classic designs for the 4116 16K DRAM. Even when DRAMS went to CMOS, it was & I believe is still used because there is no room for complimentary mos structures in the pitches used on DRAM either row or column. IE 1 NMOS device fits in 1.5 metal pitch has to perform several jobs, both selective pull up to the VCC rail (requires boosting) and pull down (easy). The 8086 & 68K and many familiar NMOS chips used it for clock drivers & other uses till CMOS took over. I remember even CMOS designers used it quite a bit until the process device guys insisted on ridding us of high voltage circuits, gate oxides couldn't be both HV tolerant & high speed and they didn't want multiple V type devices unless absolutely necessary. There are some excellent but pricey text books on DRAM design that are current to modern CMOS DRAM, also look at older ISSC papers for these gate boosting circuits. I suspect gate boosting is used only in critical pitch situations. In most other places, there is enough space to throw logic transisters at the job. The basic DRAM row line though only switches either all NMOS or all PMOS devices to connect the storage caps to the bitlines. The P's leak less so would be -ve boosted. Either way, if the rowline is boosted, the caps can be written with a full rail signal, otherwise the caps can only be written with 2/3 rail and more slowly. More cap signal = better data retention. Also higher than normal threshold devices can be used to store data more reliably for less leakage, but require boosting to get past the higher Vth drop. As for FPGAs, it could be possible to use boosted NMOS devices also for switching fabric but I am pretty sure fast CMOS circuit techniques can do a much better job with active circuits. I suspect that some ancient NMOS FPGAs may have used it. When asynchronous signals pass through a NMOS switch that is boosted, the signal passes through faster, but it also couples with the gate so the booster needs to handle feedback. One way to handle that is to use HV logic to selectively overdrive gates. In NMOS, HV gate boosting logic was all about steering precharged caps, and oh what fun that was. Fast manchester carry chains can still benefit from selective gate boosted (P/G) since the carry time per bit can be the NMOS transit time, but this is best used in clocked adders, ie the clk is gated to all the carry ins. Regards John VLSI historical rambling societyArticle: 52768
Don't forget the tools supplied by the manufacturers... "Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg> wrote in message news:Z97vBzM2CHA.2248@exchnews1.main.ntu.edu.sg... I observed, there are 3 synthesis tools for FPGA : - Leonardo Spectrum from Mentor Graphics - Precisions (new version of Leonardo Spectrum) - Symplify Pro from Simplicity Anyone here has experience which some of them ? What is the major difference among them ? Thanks :) Cheers, BuzzArticle: 52769
I'm not much of a circuits guy, so I can't answer your questions on charge pumps and the like -- the bottom line is that you somehow have to generate/supply Vcc + delta for gate boosting, and I imagine that could be a challenge. The downside to fully CMOS transmission gates is that they burn area. So it becomes an area/delay trade-off of how you build your transmission gates/multiplexors/demultiplexors in your FPGA routing fabric. The FPGA has oodles of transistors dedicated to switching functions, and you can pack them pretty tight if you don't need wells -- the moment you throw some PMOS devices into the mix, you (a) need more area for the second transistor and (b) burn area for well spacing, etc. Regards, Paul "Ljubisa Bajic" <eternal_nan@yahoo.com> wrote in message news:9b0afb2c.0302201503.3c186dbf@posting.google.com... > Hi Paul, > > Have you ever seen this done (even outside of a commercial setting) ? > I would be interested in seeing the circuit that implements this. Charge > pumps are switched cap circuits, so you would need to have a clock in order > to implement a transmition gate ? > Anyhow why would anyone do this rather than just use a transmition gate > (with a n-ch and p-ch transistor), or, if they really dont want to use a pass- > gate, use a pull-up/bleeder transistor like the ones used in some dynamic logic > circuits ? > As far as I know charge-pumps are generally only used in digital circuits > in order to generate the high(-er than supply) voltage necessary for > programming (E)PROM, or maybe level shifting (like for interfacing to a > computer serial port if you dont have 12v supply on your board). > > Ljubisa Bajic, > VLSI Design Engineer, > Oak Technology, Teralogic Group > > "Paul Leventis \(at home\)" <paul.leventis@utoronto.ca> wrote in message news:<GC45a.21129$b8v1.5651@news04.bloor.is.net.cable.rogers.com>... > > If I understand your question, then it's when you overdrive the gate a pass > > transistor to make sure it *really* turns on. > > > > The big problem with pass-transistor logic is that you get a Vth drop across > > an nmos pass transistor when you drive through it. This degrades the signal > > passing through the pass gate, causing reduced performance. There are also > > power implications. However the voltage drop is relative to the value > > applied to the gate. By driving the gate with a higher voltage than you use > > for the signal that is passing through the pass gate, you reduce the > > magnitude of the degradation -- potential completely removing it, if you can > > tolereate voltages that high. > > > > The cons are that you need to generate this higher gate voltage (you now > > have two different Vcc values) off chip or on chip via charge pumps. And > > you need to route an extra power network. And most importantly, the amount > > you can overdrive your gates by depends on the process technology you are > > using -- the stronger your overdrive, the more likely you will run into > > reliability issues with the transistor. > > > > Do companies do this? I don't know and/or can't say :-) > > > > Regards, > > > > Paul > > > > "digari" <digari@dacafe.com> wrote in message > > news:e0855517.0302190344.5bce1783@posting.google.com... > > > What is gate boosting? what are the pros and cons of the technology? > > > Does is it being used in any FPGA device?Article: 52770
Thanks for the reply. But how do you do this? Is this in the settings or do you have to explicitly write this in your constraint file? -ron "Bob" <nimby1_not_spmmm@earthlink.net> wrote in message news:<RdZ4a.10931$_c6.1132582@newsread2.prod.itd.earthlink.net>... > You must not be using the global clock nets to route your clock. > > Use the global clock nets (i.e., output of the BUFG). > > Bob > > "ron" <rathanon99@yahoo.com> wrote in message > news:c661162.0302191707.260209f1@posting.google.com... > > I got this message from the static timing analyzer of xilinx ISE. > > Apparently, I have 3 hold violations. One of them has the following > > information. How do you solve this? Thank you and hope to hear from > > you soon. > > > > Hold Violations: Default period analysis > > > > -------------------------------------------------------------------------- > ------ > > Hold Violation: -8.816ns (data path - positive clock skew) > > Source: inst_id_ex_inst_block_im8_out_2 > > Destination: u_shift_mux_reg_out_sig_2 > > Data Path Delay: 8.315ns (Levels of Logic = 4) > > Positive Clock Skew: 17.131ns > > Source Clock: inst_clk_out_inst_block_I_cp15clk_11 falling > > Destination Clock: inst_clk_out_inst_block_I_cp15clk_13 falling > > Timing Improvement Wizard > > Data Path: inst_id_ex_inst_block_im8_out_2 to > > u_shift_mux_reg_out_sig_2 > > Delay type Delay(ns) Logical Resource(s) > > ---------------------------- ------------------- > > Tcko 0.772 inst_id_ex_inst_block_im8_out_2 > > net (fanout=1) 0.357 inst_id_ex_inst_block_im8_out_2 > > Tilo 0.398 u_bmux_Mmux_b_out_sig_inst_lut3_225 > > net (fanout=3) 0.658 > > u_bmux_Mmux_b_out_sig_xstmacro_int_tempname303 > > Tif5 0.752 > > u_bmux_Mmux_b_out_sig_xstmacro_int_tempname303_rt > > > > u_bmux_Mmux_b_out_sig_inst_mux_f5_100 > > net (fanout=20) 4.781 > > u_bmux_Mmux_b_out_sig_xstmacro_int_tempname304 > > Tcki (-Th) -0.597 u_shift_mux_I_shift_sig_2_1 > > u_shift_mux_reg_out_sig_2 > > ---------------------------- ------------------------------ > > Total 8.315ns (2.519ns logic, 5.796ns route) > >Article: 52771
> Another layout possibility is to put a ring on the bottom layer > directly under the pads. With only 2 layers, that will block > routes from vias in the inside of the pad ring. At 8 MHz you can set the slew rates slow enough to use two layers. Especially if you only have 16 switching signals. We use loops on the bottom layer for each power supply. The loops have small capacitors between them. Each fpga pin connects from the inside to one of the loops by a via. There is a ground plane below the chip on the top layer to connect GND. This also has coupling caps to the power supply loops. Using this scheme we have PCI running reliable on two layer boards. But we probably do not meet the PCI specifiation. (We also have som 250MHz data aquistion stuff runnning on two layers, also) Peter: 4-Layer boards are not a lot more expensive than two layer boards in production, but you have to pay a couple of hundred $ upfront, which you do not have for two layers. For a hobby project it is a big difference whether the first prototype costs $40 or $300. Kolja SulimmaArticle: 52772
I agree with u paul. gate boosting saves some silicon area. I feel it also depends on febrication unit that how much overdrive u can support. I have seen one example in betz thesis. He has mentioned that xilinx uses gate boosting. "Paul Leventis \(at home\)" <paul.leventis@utoronto.ca> wrote in message news:<pui5a.28516$UXa.8171@news02.bloor.is.net.cable.rogers.com>... > I'm not much of a circuits guy, so I can't answer your questions on charge > pumps and the like -- the bottom line is that you somehow have to > generate/supply Vcc + delta for gate boosting, and I imagine that could be a > challenge. > > The downside to fully CMOS transmission gates is that they burn area. So it > becomes an area/delay trade-off of how you build your transmission > gates/multiplexors/demultiplexors in your FPGA routing fabric. The FPGA has > oodles of transistors dedicated to switching functions, and you can pack > them pretty tight if you don't need wells -- the moment you throw some PMOS > devices into the mix, you (a) need more area for the second transistor and > (b) burn area for well spacing, etc. > > Regards, > > Paul > > > "Ljubisa Bajic" <eternal_nan@yahoo.com> wrote in message > news:9b0afb2c.0302201503.3c186dbf@posting.google.com... > > Hi Paul, > > > > Have you ever seen this done (even outside of a commercial setting) ? > > I would be interested in seeing the circuit that implements this. Charge > > pumps are switched cap circuits, so you would need to have a clock in > order > > to implement a transmition gate ? > > Anyhow why would anyone do this rather than just use a transmition gate > > (with a n-ch and p-ch transistor), or, if they really dont want to use a > pass- > > gate, use a pull-up/bleeder transistor like the ones used in some dynamic > logic > > circuits ? > > As far as I know charge-pumps are generally only used in digital circuits > > in order to generate the high(-er than supply) voltage necessary for > > programming (E)PROM, or maybe level shifting (like for interfacing to a > > computer serial port if you dont have 12v supply on your board). > > > > Ljubisa Bajic, > > VLSI Design Engineer, > > Oak Technology, Teralogic Group > > > > "Paul Leventis \(at home\)" <paul.leventis@utoronto.ca> wrote in message > news:<GC45a.21129$b8v1.5651@news04.bloor.is.net.cable.rogers.com>... > > > If I understand your question, then it's when you overdrive the gate a > pass > > > transistor to make sure it *really* turns on. > > > > > > The big problem with pass-transistor logic is that you get a Vth drop > across > > > an nmos pass transistor when you drive through it. This degrades the > signal > > > passing through the pass gate, causing reduced performance. There are > also > > > power implications. However the voltage drop is relative to the value > > > applied to the gate. By driving the gate with a higher voltage than you > use > > > for the signal that is passing through the pass gate, you reduce the > > > magnitude of the degradation -- potential completely removing it, if you > can > > > tolereate voltages that high. > > > > > > The cons are that you need to generate this higher gate voltage (you now > > > have two different Vcc values) off chip or on chip via charge pumps. > And > > > you need to route an extra power network. And most importantly, the > amount > > > you can overdrive your gates by depends on the process technology you > are > > > using -- the stronger your overdrive, the more likely you will run into > > > reliability issues with the transistor. > > > > > > Do companies do this? I don't know and/or can't say :-) > > > > > > Regards, > > > > > > Paul > > > > > > "digari" <digari@dacafe.com> wrote in message > > > news:e0855517.0302190344.5bce1783@posting.google.com... > > > > What is gate boosting? what are the pros and cons of the technology? > > > > Does is it being used in any FPGA device?Article: 52773
Try to run vsim with +no_tchk_msg, +nospecify, and +notimingchecks options. HTH, Jim "Barry Brown" <barry_brown@agilent.com> wrote in message news:<1045776349.578259@cswreg.cos.agilent.com>... > In my Spartan2 design, I am using BRAMs as a synchronous FIFO, and I have > tied their enable inputs true for the read port. As a result, Modelsim > gives me lots and lots of warnings like: > > # ** Warning: */RAMB4_S4_S4 SETUP High VIOLATION ON CLKB WITH RESPECT TO > CLKA; > # Expected := 0.01 ns; Observed := 0 ns; At : 8821.04 ns > # Time: 8821040 ps Iteration: 2 Instance: > /adctrigger/server/uut/u10/adcdatafifo/bram_gen__0/bram > # ** Warning: */RAMB4_S4_S4 SETUP High VIOLATION ON CLKA WITH RESPECT TO > CLKB; > # Expected := 0.01 ns; Observed := 0 ns; At : 8821.04 ns > # Time: 8821040 ps Iteration: 2 Instance: > /adctrigger/server/uut/u10/adcdatafifo/bram_gen__0/bram > # ** Warning: Attempting to read some or all of contents of address > 0000000000 from port A while writing from port B in instance * > # Time: 8821040 ps Iteration: 2 Instance: > /adctrigger/server/uut/u10/adcdatafifo/bram_gen__0/bram > > My design works fine, I'm not really trying to read and write the same > location simultaneously, but I would like to get rid of all these > distracting warnings if possible. > > Does anyone know of a switch for vsim, or anything else that might disable > these warnings? > > TIA, > Barry BrownArticle: 52774
The BUFG (or BUFGMUX) is a component that must be hooked up in your code. Typically, the clock coming into your FPGA is connected to one of the IOB's which is also identified as a global clock input (because it's physically close to clock resources inside the chip). This type of IOB, when used for a clock input, is called an IBUFG component. If you're not using a DLL (or DCM for Virtex-II), then: IBUFG output->BUFG input If you are using a DLL/DCM, then: IBUFG output->DLL input DLL ouput->BUFG input BUFG output->DLL feedback input In both cases, the output of the BUFG is the low-skew global clock net. The name you assign to the BUFG's output is what you use to clock all of your processes (i.e., all of the flip flop clock inputs will be driven by the BUFG's output). I'm sure that Xilinx has some code examples on their website. Bob "ron" <rathanon99@yahoo.com> wrote in message news:c661162.0302210125.7f2e5422@posting.google.com... > Thanks for the reply. But how do you do this? Is this in the settings > or do you have to explicitly write this in your constraint file? > -ron > > "Bob" <nimby1_not_spmmm@earthlink.net> wrote in message news:<RdZ4a.10931$_c6.1132582@newsread2.prod.itd.earthlink.net>... > > You must not be using the global clock nets to route your clock. > > > > Use the global clock nets (i.e., output of the BUFG). > > > > Bob > > > > "ron" <rathanon99@yahoo.com> wrote in message > > news:c661162.0302191707.260209f1@posting.google.com... > > > I got this message from the static timing analyzer of xilinx ISE. > > > Apparently, I have 3 hold violations. One of them has the following > > > information. How do you solve this? Thank you and hope to hear from > > > you soon. > > > > > > Hold Violations: Default period analysis > > > > > > -------------------------------------------------------------------------- > > ------ > > > Hold Violation: -8.816ns (data path - positive clock skew) > > > Source: inst_id_ex_inst_block_im8_out_2 > > > Destination: u_shift_mux_reg_out_sig_2 > > > Data Path Delay: 8.315ns (Levels of Logic = 4) > > > Positive Clock Skew: 17.131ns > > > Source Clock: inst_clk_out_inst_block_I_cp15clk_11 falling > > > Destination Clock: inst_clk_out_inst_block_I_cp15clk_13 falling > > > Timing Improvement Wizard > > > Data Path: inst_id_ex_inst_block_im8_out_2 to > > > u_shift_mux_reg_out_sig_2 > > > Delay type Delay(ns) Logical Resource(s) > > > ---------------------------- ------------------- > > > Tcko 0.772 inst_id_ex_inst_block_im8_out_2 > > > net (fanout=1) 0.357 inst_id_ex_inst_block_im8_out_2 > > > Tilo 0.398 u_bmux_Mmux_b_out_sig_inst_lut3_225 > > > net (fanout=3) 0.658 > > > u_bmux_Mmux_b_out_sig_xstmacro_int_tempname303 > > > Tif5 0.752 > > > u_bmux_Mmux_b_out_sig_xstmacro_int_tempname303_rt > > > > > > u_bmux_Mmux_b_out_sig_inst_mux_f5_100 > > > net (fanout=20) 4.781 > > > u_bmux_Mmux_b_out_sig_xstmacro_int_tempname304 > > > Tcki (-Th) -0.597 u_shift_mux_I_shift_sig_2_1 > > > u_shift_mux_reg_out_sig_2 > > > ---------------------------- ------------------------------ > > > Total 8.315ns (2.519ns logic, 5.796ns route) > > > >
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