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I have just started a new design where I am looking to implement a FIR filter in a SPartan IIe FPGA (actually 4, all with identical characteristics) To start with filter characteristics input data is 9 bit samples at 33.325714 MHz (or possibly 31.104 MHz) 1 dB ripple allowed in pass band (0 - 7MHz), minimum of 65 dB down in the stop band. (8 MHz) data is output at a rate of 1/2 the sampling frequency (decimation by 2) - 9 bit I have a reasonable amount of freedom in the implementation of the design(the chip currently designed on the board is the XC2S150E) I am looking for suggestions on the implementation of the filter structure (eg multipliers, use of the block ram) and comments on the quality of dsp tools such as the tools from systolix and convern from Momentum Data Systems Has anyone used the filters in the Xilinx Core generator? What did you think of them? I am also happy to look at cores from other vendors if the pricing is reasonable. Garry AllenArticle: 52226
Is Clock Enable (CE) of Flip-Flop, Synchronous or Asynchronous signal ??? Pl. justify the answers. Thanks VsArticle: 52227
What did your teacher say in lecture?
Vishker wrote:
> Is Clock Enable (CE) of Flip-Flop, Synchronous or Asynchronous signal ???
> Pl. justify the answers.
>
> Thanks
>
> Vs
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52228
Prashant wrote:
> Robert,
>
> Use ROMs as Mike suggests. You can create ROMs very easily using the
> MEGAfunction wizard in the Quartus II toolset.
For those allergic to MEGAfunctions, a simple array of constants
also works fine as a rom.
RAM resources are used quite reasonably by leo or synplicity for
large arrays.
-- Mike Treseler
Article: 52229
As a straight filter, you are looking at somewhere in the neighborhood of
70 symmetric taps, and depending on how flexible you are with the clock
you could get 5 clocks per input sample without a huge amount of pain. If
you make it a polyphase decimator, then you get 10 clocks per sample on
each filter branch, which is achievable with a serial DA filter. The taps
are symmetric, so you can do the symmetry folding and get down to about 9
DA terms. If you can live with 6dB point being at exactly Fs/4 and a
symmetric response above and below that point, then you could use a
halfband filter. It is still around 70 taps, but half of those are zero
so it significantly simplifies the filter. See the distributed arithmetic
page on our website for a primer on DA.
The Xilinx filter cores are not bad as long as it comes in a flavor you
like. In this case, I am pretty sure the core will generate an
appropriate filter if you set everything up right. I don't know if the
Xilinx cores will hit 160 MHz or not. I know our filters will, but the
construction is a little different than the xilinx cores (we did our own
IP after running into enough cases early on that the coregen did not
address. The coregen coverage has gotten much better since then, but we
still use ours because we have access to the source).
Garry Allen wrote:
> I have just started a new design where I am looking to implement a FIR
> filter in a SPartan IIe FPGA (actually 4, all with identical
> characteristics)
> To start with
> filter characteristics
> input data is 9 bit samples at 33.325714 MHz (or possibly 31.104 MHz)
> 1 dB ripple allowed in pass band (0 - 7MHz), minimum of 65 dB down in
> the stop band. (8 MHz)
> data is output at a rate of 1/2 the sampling frequency (decimation by
> 2) - 9 bit
>
> I have a reasonable amount of freedom in the implementation of the
> design(the chip currently designed on the board is the XC2S150E)
> I am looking for suggestions on the implementation of the filter
> structure (eg multipliers, use of the block ram) and comments on the
> quality of dsp tools such as the tools from systolix and convern from
> Momentum Data Systems
> Has anyone used the filters in the Xilinx Core generator? What did you
> think of them? I am also happy to look at cores from other vendors if
> the pricing is reasonable.
> Garry Allen
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52230
The difference in left to right or right to left in 4000 series was negligable.
Basically within a few tens of ps difference as I recall. We ran our data paths
in both directions in 4K with no noticable difference. Depended much more which
side the pins were on relative to your logic.
ac wrote:
> I have asked this same questions to FAEs and they used to recomend left to
> right
> for data flow on the 4000s series since you didn't want the output of a flip
> flop to have to route
> "back". For Virtex they say that the improved routing resources make this a
> non-factor
> as usual you want to make sure that any adders, counters, etc make use of
> the carry chain
> which is vertically oriented.
>
> "douglas fast" <d@vcom.com> wrote in message
> news:981fe2ba.0302041214.42e759e6@posting.google.com...
> > Hello,
> >
> > I am in the process of floorplanning an FPGA design which contains an
> > adder tree. The Xilinx documentation mention that datapaths should
> > flow horizontally in order to make the best use of routing resources.
> > Is there also a preference for left to right flow vs right to left?
> >
> > Thanks,
> >
> > Doug
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52231Hi, I'm trying to implement regular dsp blocks (sigma-delta modulator, filters etc...) into an fpga and I'm having a hard time choosing the right design implementation / devices. For example, lets say you want to build a 3rd order sigma-delta modulator using 32 bits registers. There are about 5 multipliers and three integrators (adder + Dff). Implementing this system in vhdl with LPM multipliers simply doesn't fit in the fpga I have access to (EPF10k20RC240 - the one on the university board from altera). I wonder if this is because people simply do not blindly write code describing the system exactly as it appears in block diagram or if the fpga device I have is simply not used for this kind of work. I know there exist better multiplier than the LPM but say I stick with them. When doing this kind of design, do people usually use one or two multipliers with muxes and a state machine to save on hardware? I thought the whole idea of using an fpga was to increase speed --> avoid rebuilding some sort of a dsp processor. Thank you very much DavidArticle: 52232
Is this newsgroup deteriorating into a remedial help service for students who did not pay attention in class, or cannot read a text book or data sheet? CE controls a mux that makes the D input either look at the Q output ( clock disabled) or look at the incoming signal ( clock enabled). CE is, therefore, a synchronous signal. Peter Alfke ========================== Vishker wrote: > Is Clock Enable (CE) of Flip-Flop, Synchronous or Asynchronous signal ??? > Pl. justify the answers. > > Thanks > > VsArticle: 52233
Vishker wrote: > Is Clock Enable (CE) of Flip-Flop, Synchronous or Asynchronous signal ??? > Pl. justify the answers. wow! some of them don't even try to cover the fact that it's homework!Article: 52234
Bill, The Student Edition is actually the same as our BaseX configuration. The additional items included in BaseX that are not in WebPACK include: - FPGA Editor - CoreGen - Device support: 2S400E, 2S600E, Virtex There will be more devices support differences in the 6.1i release Steve Bill Turnip wrote: > Anyone care to comment on the differences between the two? Is the Student > Edition worth the expense as compared to the free WebPACK? If WebPACK is > free, why is the SE on the market? > > Just curious, > BTArticle: 52235
I suspect that there is no spec on VQM format. As for converting to VQM, do you have the source RTL? You can use the altera edition of Leonardo to make a EDIF file. -Xanatos "Young-Su Kwon" <yskwon@vslab.kaist.ac.kr> wrote in message news:b1oek4$m8$1@news.kreonet.re.kr... > > Dear experts, > > VQM(Verilog Quartus Mapping File) > is the Quartus II's input netlist format. > Does anybody know the spec. book of VQM? > Does anybody know how to convert VQM to EDIF netlist? > > Thanks, > Kwon. > > > -- > -*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-* > Young-Su Kwon > Ph. D Student. > VLSI Systems Lab, KAIST > yskwon@vslab.kaist.ac.kr > -*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-* > >Article: 52236
Quartus II 2.1, released mid 2002 and later versions have fixed this problem. The most recent version of Quartus II available is 2.2. Quartus II 1.0 is over two years old. - Subroto Datta Altera Corp. "sadik" <k0sadik@yahoo.com> wrote in message news:47c0f446.0302040424.113f6924@posting.google.com... > Hi, > When i run the tcl script quartus II 1.0 gives the error called > "Can't start server quartus_cmp Beginning attempt 1 of 3 attempts to start server" > But the same project got completed in when fired through GUI! > What could be the problem??? > thanks and regds > SadikArticle: 52237
"Jonathan Bromley" <jonathan@oxfordbromley.u-net.com> wrote in message news:b1o9mu$de9$1$8302bc10@news.demon.co.uk... > While Simon's gloss is clearly correct, it's perhaps not very > informative to a newby. A sideways view might be more helpful. > > How about... > CPLD: Middling-to-big programmable doohickey marketed by people > who still think 22V10s are a pretty neat idea. > FPGA: Big-to-huge programmable doohickey marketed by people who > think that it's a pretty neat idea to spend 75 million > transistors in order to create a million gates of logic. > ASIC: Huge-to-gigantic non-programmable doohickey designed by > machos who think that modifying a gate level netlist > with a 10,000-line Perl script in order to fix one missing > inverter is a pretty neat way of doing an ECO. > -- > Jonathan Bromley, Consultant Jonathan, I love your sarcasm of my sarcasm! SimonArticle: 52238
Hello Mr. kelvin, Thank you very much for ur tips. So i you started reading PCI specification (Mainly appendix B). I wanted to know how to start coding .Whether to start with configuration block or other block. Ok if i start with configuration block how can i test my block????....(simulation ...no i like that does not test my block???).... waiting for reply praveenArticle: 52239
Praveen, Start with the configuration register block first. That's how I did mine. Run the PCI interface with the configuration register block only on an HDL simulator (If you are poor like myself, use ModelSim XE-Starter which is free.), and make sure everything works fine. If you want to, you can synthesize the design with a synthesis tool, and map it to an FPGA (like Insight Electronics Spartan-II PCI card) see if it will work in a real computer. After that, implement the rest of the PLX's local bus. Kevin Brace (If someone wants to respond to what I wrote, I prefer if you will do so within the newsgroup.) praveen wrote: > > Hello Mr. kelvin, > Thank you very much for ur tips. So i you started reading PCI > specification (Mainly appendix B). I wanted to know how to start > coding .Whether to start with configuration block or other block. Ok > if i start with configuration block how can i test my > block????....(simulation ...no i like that does not test my > block???).... > > waiting for reply > praveenArticle: 52240
hello, Then why new revision ???????? waiting for reply praveenArticle: 52241
In article <ff8a3afb.0302030204.49d7e0bd@posting.google.com>, praveen <praveenkumar1979@rediffmail.com> wrote: >Hello Friends/Sir, >I wanted to know what is the difference between PCI rev 2.1 and PCI rev. 2.2. The difference is 0.1 Enjoy! -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 52242
In article <ff8a3afb.0302042308.10232564@posting.google.com>, praveen <praveenkumar1979@rediffmail.com> wrote: >hello, > >Then why new revision ???????? It's a plot by the secret kabal of standards-committees who has to push out revised versions in order to sell more copies of standards documents. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 52243
In comp.lang.vhdl Peter Alfke <peter@xilinx.com> wrote: I've always wondered why they call it CE (clock enable) when in fact its DE (data enable). In the wonderful world of ASICs gated clocks are often preferred, when power consumption is of concern. In these flip-flops clock signals are anded with CE. The hard task is controlling the CE signals... regards, juza : CE controls a mux that makes the D input either look at the Q output ( clock : disabled) or look at the incoming signal ( clock enabled). CE is, therefore, : a synchronous signal. : Peter Alfke : ========================== : Vishker wrote: :> Is Clock Enable (CE) of Flip-Flop, Synchronous or Asynchronous signal ??? :> Pl. justify the answers. :> :> Thanks :> :> Vs -- JuzaArticle: 52244
Gee, I always thought CE stands for Chip Enable... Jussi Lähteenmäki wrote: > > In comp.lang.vhdl Peter Alfke <peter@xilinx.com> wrote: > I've always wondered why they call it CE (clock enable) when in fact its > DE (data enable). In the wonderful world of ASICs gated clocks are > often preferred, when power consumption is of concern. In these flip-flops > clock signals are anded with CE. The hard task is controlling the CE > signals... > > regards, > juza > > : CE controls a mux that makes the D input either look at the Q output ( clock > : disabled) or look at the incoming signal ( clock enabled). CE is, therefore, > : a synchronous signal. > > : Peter Alfke > : ========================== > : Vishker wrote: > > :> Is Clock Enable (CE) of Flip-Flop, Synchronous or Asynchronous signal ??? > :> Pl. justify the answers. > :> > :> Thanks > :> > :> Vs > > -- > JuzaArticle: 52245
It requires a lot of multiplications done for each output sample. Try to make multiplier(s) pipelined (it seems 16x16bits would be enough). May be scheme with 15 redundant adders will provide high clock rate of the scheme with 1 cycle throughput multiplications. For A * B: (((A*B0+(A*B1<<1))+(A*B2+(A*B3<<1)))+ ((((A*B4+(A*B5<<1))+((A*B6+(A*B7<<1))<<2))<<4)+ ((((A*B8+(A*B9<<1))+(A*B10+(A*B11<<1)))+ ((((A*B12+(A*B13<<1))+((A*B14+(A*B15<<1))<<2))<<4)<<8) It has latency of 4 cycles. Unfortunately it requires a lot of gates. CONST*(8*17+4*19+2*23+31)~CONST*290 of adder's gates. And there is a lot of wires between adders that consume gates too. PS: I'm not HW designer, so if this is all rot just skip it. "Garry Allen" <garrya@ihug.com.au> wrote in message news:3abc4240.0302041459.5c1b3ef3@posting.google.com... > I have just started a new design where I am looking to implement a FIR > filter in a SPartan IIe FPGA (actually 4, all with identical > characteristics) > To start with > filter characteristics > input data is 9 bit samples at 33.325714 MHz (or possibly 31.104 MHz) > 1 dB ripple allowed in pass band (0 - 7MHz), minimum of 65 dB down in > the stop band. (8 MHz) > data is output at a rate of 1/2 the sampling frequency (decimation by > 2) - 9 bit > > I have a reasonable amount of freedom in the implementation of the > design(the chip currently designed on the board is the XC2S150E) > I am looking for suggestions on the implementation of the filter > structure (eg multipliers, use of the block ram) and comments on the > quality of dsp tools such as the tools from systolix and convern from > Momentum Data Systems > Has anyone used the filters in the Xilinx Core generator? What did you > think of them? I am also happy to look at cores from other vendors if > the pricing is reasonable. > Garry AllenArticle: 52246
Hi, Q: How to prevent the MAP tools from trimming a part of the design while still enabling the optimizer on the rest of the design? I have a design that part of it will be optimized away by MAP tools as loadless. But I need to keep that part. I know I can use the '-u' option to disable the trimming function. But I *do* want the optimizer to work on the rest of the design to get better performance. Is this possible (without going to FPGA Editor as I am doing)? Thanks in advance! -- Tsoi Kuen Hung (Brittle) CSE CUHKArticle: 52247
>I have a design that part of it will be optimized away by MAP tools >as loadless. But I need to keep that part. I know I can use the '-u' >option to disable the trimming function. But I *do* want the optimizer >to work on the rest of the design to get better performance. Is this >possible (without going to FPGA Editor as I am doing)? Take the "loadless" signals that you want to preserve and put a load on them, perhaps by connecting them to an output pin. Or AND several of them together and send that signal to a pin. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 52248
"Jan De Ceuster" <Jan.DeCeuster@elis.rug.ac.be> wrote > Gee, I always thought CE stands for Chip Enable... Nah, you're all wrong. It's the little logo they stick on toys to show that they are [allegedly] compliant with all the European consumer-protection legislation. Never let a sensible bit of technical usage get in the way of legislative fervour, that's what I say. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 52249
Hi All Anyone knows how to Mix VHDL with Verilog modules? I read that Leonardo Spectum can combine, but in this case which module must be the top level? Talal
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