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Hi all, is there a table showing approximate output impedance of the OBUF xmA drivers for the Spartan-II family FPGA's? best regards markus -- Mit freundlichen Grüssen Markus Meng P.S. Achtung wir haben eine neue FAX-Nummer ******************************************************************** ** Meng Engineering Telefon 056 222 44 10 ** ** Markus Meng Natel 079 230 93 86 ** ** Bruggerstr. 21 Telefax 056 222 44 34 <-- NEU !! ** ** CH-5400 Baden Email meng.engineering@bluewin.ch ** ** Web www.meng-engineering.ch ** ******************************************************************** ** You cannot create experience. You must undergo it. Albert Camus** -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 52151
Hi, Starting point for a profesional core is about 1500$ and up. There is a newly released "free" 8051 core avalible trough OPENCORES. But this question is difficult to answare sinces there is several more issues to consider. What family is the target for this design. Altera or Xilinx they have diffrent prices and diffrent support for this technolgies, core cost is a farily small part of the overall cost today if you have a disent volume application (5k units /year). I once did a calculation on a cyclone device (Altera) and a PCI core priced at 5k$ 5k volume giving that cost of core is 1$/device and then you have 1000LE roughly usage logic. Given in small volume silcon cost 4.5$ (this number is much more intressting since this is the cost for implementation). Same core in a Stratix is at 1000LEs 4 times more expensive. Second question you have to ask your self is what amount of support do you need a opencore is free, but there is no (best case limited) support and you might get access to the source code. A pice of IP sold trough a IP-supplier will never come with source code unless you pay top dollars (my initial estimate is not even close), but might be more resource efficent and will have a support struckture behind it. Best way to get a god estimate of price verus preformance is to talk to a sales rep or distributor for the FPGA vendor. They should also be able to supply you support. Cheers Fredrik anglomont@yahoo.com (TI) wrote in message news:<18a34598.0302021646.308dc61c@posting.google.com>... > Can smbdy please point me to a link or just give and estimate > how much does the stuff like :rake receiver, 8051 core, costs? > regards > TIArticle: 52152
Very happy to see your post. I found the FPGA-Editor help files in Xilinx.com, but I didn't find what you mentioned in it. Do I have to get the actural software to know the exact structure of the switchbox? Thanks a lot.Article: 52153
Yes, you do. It is part of the ISE software. Unfortunately, it is not
included in webpack.
Jing wrote:
> Very happy to see your post. I found the FPGA-Editor help files in
> Xilinx.com, but I didn't find what you mentioned in it. Do I have to
> get the actural software to know the exact structure of the switchbox?
> Thanks a lot.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52154
For outputs that last for several states in a one-hot machine, you can use a
synchronous set-reset flip-flop that is set at the initial state and then
cleared at the final state rather than decoding many one-hot states.
Ernest Jamro wrote:
> The choice between one hot and binary encoding should be also with
> respect to the output function. E.g. when you have about a hounded of
> outputs and each of then is 1 for only a single state - one hot is a
> good choice. Nevertheless if the outputs are '1' for roughly a half of
> all states it might be better to use the binary encoding. As the output
> logic might inquire on average 192/2 input OR gate!!!!!
>
> I
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52155In order to shorten the place and route processor time I am looking into ways to modulize the design. I'm using a virtex-II 8000, which have 168 multerpliers / block selectram, in a 28x6 layout. The design consists of 168 equivalent cell, which has exactly the same vhdl-code. All cells only talk to the neighboring cells so routing between cells should not be that hard. What I would like to do is to compile one of the cells as a module and do the local place and route once for all. One thing I've tried is to open floorplanner and set a constraint-box for each cell, save the file as .mpf and retry with place and route. Problem with this seems to be that place & route still takes very long time. Is there as possibility to generate a rpm for one module and then place the modules and only route them. I realize that if you look at the physical layout of the chip, there is 3 different cases. If all blocks have the same size, there is 3 different constraint-boxes. One with the multiplier to the left in the cell, one in the midle and one to the right. Since all cells just talk to there neighbors there should be a possibility of placing the 3 different cells and route them together. Is this a good approach, is it even possible to do? What are the alternatives? What about module something from xilinx? All response is welcome! Regards JohannesArticle: 52156
In floorplanner I've placed a constraint-box that is 4 CLBs high and with enough width containing a multiplier and block select ram. Both multiplier and RAM is constructed using CoreGen. In addition a 21-bit accumulator is also created. Without constraints there's no problem, the accum is 5 CLBs high. This seems to be a problem so I removed the rpm option in CoreGen in order to be able to place the accum in a constrainted world that is 4 CLBs high. This to no avail, since place & route fails when I try to constraint the design. I'm using ISE 4.2.03 SE and a virtexII8000. Regards JohannesArticle: 52157
I am interested in implementing a (soft) microprocessor core on Virtex just for education purposes (and latter on maybe, to use it in some applications). There are a lot of them available (e.g. OPENCORES). I do not know which one is the best choice. The microprocessor core should: 1) be free and open - its architecture should be well described so it would be easy to learn how it works and allows to simulate each part of the microprocessor or even observe the real time microprocessor's signals by ChipScope or Internal Logic Analyser (OpenCores). (It would be nice if the microprocessor has a WISHBONE compatible external bus) 2) Rather quick - to show the modern microprocessor architectures - pipelining, possible branch prediction, VLIW and superscalar execution, and working with high frequency (comparable to e.g. microBlaze) 3) With assembler and C compiler (and maybe even supported by Linux OS - a good wish only) 4) It would be nice if two or more microprocessors can be easily combined to work in parallel, and parallel work is supported by the C compiler or another associated tool (as C language does not directly support parallel processing) Is it better to use a free core or to buy a commersial one (e.g. microBlaze), as free cores are not well tested and described and/or analysising their internal structure might take too much time. Ernest JamroArticle: 52158
In article <3E3E8826.5070208@agh.edu.pl>, Ernest Jamro <jamro@agh.edu.pl> wrote: >I am interested in implementing a (soft) microprocessor core on Virtex >just for education purposes (and latter on maybe, to use it in some >applications). There are a lot of them available (e.g. OPENCORES). >I do not know which one is the best choice. > > The microprocessor core should: >1) be free and open - its architecture should be well described so it >would be easy to learn how it works and allows to simulate each part of >the microprocessor or even observe the real time microprocessor's >signals by ChipScope or Internal Logic Analyser (OpenCores). (It would >be nice if the microprocessor has a WISHBONE compatible external bus) > >2) Rather quick - to show the modern microprocessor architectures - >pipelining, possible branch prediction, VLIW and superscalar execution, >and working with high frequency (comparable to e.g. microBlaze) You won't get this, especially in an opencore. Microblaze is very highly optimized and finely pipelined, so it operates in a much higher frequency when compared with other options. >Is it better to use a free core or to buy a commersial one (e.g. >microBlaze), as free cores are not well tested and described and/or >analysising their internal structure might take too much time. If you want free, look at Leon, its a GPLed synthesized sparc. Not that fast (~20-25 MHz on a Virtex), and not that small (~6000 LUTs), but free and fully synthesized. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 52159
Markus, Look inside the IBIS files. The IV curves tell the whole story. If you do not have an IBIS modeling tool, you can use Excel to see the IV table in spreadsheet form. V/I=R Austin Markus Meng wrote: > Hi all, > > is there a table showing approximate output impedance of the OBUF xmA > drivers for > the Spartan-II family FPGA's? > > best regards > markus > > -- > Mit freundlichen Grüssen > Markus Meng > > P.S. Achtung wir haben eine neue FAX-Nummer > ******************************************************************** > ** Meng Engineering Telefon 056 222 44 10 ** > ** Markus Meng Natel 079 230 93 86 ** > ** Bruggerstr. 21 Telefax 056 222 44 34 <-- NEU !! ** > ** CH-5400 Baden Email meng.engineering@bluewin.ch ** > ** Web www.meng-engineering.ch ** > ******************************************************************** > ** You cannot create experience. You must undergo it. Albert Camus** > > -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- > http://www.newsfeeds.com - The #1 Newsgroup Service in the World! > -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 52160
Muthu wrote: > Steve Lass <lass@xilinx.com> wrote in message news:<3E3AEB96.4ECB7359@xilinx.com>... > > Muthu, > > > > Xilinx Foundation Series software has not been sold to new customers since > > Q4 of 2001. ISE replaced it. > > > > There are many differences between the Foundation Series and ISE. The > > main one is that Foundation Series uses the Aldec schematic editor and > > Aldec Project Manager. ISE uses the Xilinx ECS schematic editor and > > Project Navigator. > > > > Let me know if you have any specific questions. > > > > Steve > > > > Muthu wrote: > > > > > Hi, > > > > > > What is the difference between the Xilinx Foundation Series and the Xilinx ISE. > > > > > > Regards, > > > Muthu > > Here we have installed both Xilinx Foundation 4 and Xilinx ISE 4. Will > there be any differences in the performance wise? ie., If i run a same > .edf for place and Route will there be any difference? There will be no difference. The mapping, timing, and place and route tools are the same between Foundation and ISE. Steve > > > Regards, > MuthuArticle: 52161
I would like to get an update regarding the 3.3 volt tolerant I/Os in the Virtex II Pro family. On July 4/6/8 2002 there were a discussion in this group about this subject and from that discussion I concluded that there is a limit on the amount of I/Os that are 3.3v tolerant. However, in the updated Virtex II Pro datasheet there is no mention about this limit. Has it been fixed? Any of you, specially any Xilinx guys, could you please give us any update in this regards? I will do appreciate it... Thanks very much, Paul Sereno Digital Design EngineerArticle: 52162
> It is rather difficult to type 192 >states without making an error!!!!!!!!!!!!!!!!!!!!! Write a program to write that chunk of logic. Or write a program to check what you write by hand. Or just give the states names that are easy to check with a good set of eyes. [Not saying that 192 states is the right way to solve your problem, just that being hard to do it without errors shouldn't be a problem.] -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 52163
It is an excellent approach, unfortunately, the xilinx tools do not support
it. Basically what you want is a hierarchical place and route so that each
identical submodule is placed and routed once, then those are stitched
together at the top level. It is a rather radical departure from the current
Xilinx strategy of flattening the design for place and route, so it is a
fairly major undertaking for Xilinx to change it. Please, Please, Please,
Please, open a case with Xilinx and make your case about needing this
capability. The more customers that ask for it, the more likely it will be
addressed in our lifetimes (this is something a number of frequent users have
been asking for for quite some time).
In the mean time, you can reduce the placement time by doing the
floorplanning. The 5.1 floorplanner includes a 'hierarchical' placement,
although I am not sure how well it really works. You can put placement in
your source code for the macro to make each instance into an RPM, and then
place the RPMs in the flat floorplanner or through a UCF file. Unfortunately,
there is little you can currently do about the routing. Also, the router in
4.1 and later won't necessarily make the direct route to neighboring cells
even though those are there. The router algorithm changed, and now only tries
to get a non-negative slack. As a result, the low hanging fruit in the
nearest neighbor connections is often overlooked and a long serpentine route
is used instead. See the floorplan for the sonar processor in the gallery on
my website for an example of a design that has many (in that case 50) similar
'tiles' that were floorplanned hierachically with RLOCs.
Johannes Sandvall wrote:
> In order to shorten the place and route processor time I am looking into
> ways to modulize the design.
> I'm using a virtex-II 8000, which have 168 multerpliers / block selectram,
> in a 28x6 layout. The design consists of 168 equivalent cell, which has
> exactly the same vhdl-code. All cells only talk to the neighboring cells
> so routing between cells should not be that hard.
>
> What I would like to do is to compile one of the cells as a module and
> do the local place and route once for all.
>
> One thing I've tried is to open floorplanner and set a constraint-box
> for each cell, save the file as .mpf and retry with place and route.
> Problem with this seems to be that place & route still takes very long
> time.
>
> Is there as possibility to generate a rpm for one module and then place
> the modules and only route them. I realize that if you look at the
> physical layout of the chip, there is 3 different cases. If all blocks
> have the same size, there is 3 different constraint-boxes. One with
> the multiplier to the left in the cell, one in the midle and one to
> the right.
>
> Since all cells just talk to there neighbors there should be a
> possibility of placing the 3 different cells and route them together.
>
> Is this a good approach, is it even possible to do?
> What are the alternatives? What about module something from xilinx?
>
> All response is welcome!
>
> Regards Johannes
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52164
There is also a free 68HC11 core from green mountain and a PIC 5x compatible
core on opencores.com. There are links to both on my website.
"Nicholas C. Weaver" wrote:
> In article <3E3E8826.5070208@agh.edu.pl>,
> Ernest Jamro <jamro@agh.edu.pl> wrote:
> >I am interested in implementing a (soft) microprocessor core on Virtex
> >just for education purposes (and latter on maybe, to use it in some
> >applications). There are a lot of them available (e.g. OPENCORES).
> >I do not know which one is the best choice.
> >
> > The microprocessor core should:
> >1) be free and open - its architecture should be well described so it
> >would be easy to learn how it works and allows to simulate each part of
> >the microprocessor or even observe the real time microprocessor's
> >signals by ChipScope or Internal Logic Analyser (OpenCores). (It would
> >be nice if the microprocessor has a WISHBONE compatible external bus)
> >
> >2) Rather quick - to show the modern microprocessor architectures -
> >pipelining, possible branch prediction, VLIW and superscalar execution,
> >and working with high frequency (comparable to e.g. microBlaze)
>
> You won't get this, especially in an opencore. Microblaze is very
> highly optimized and finely pipelined, so it operates in a much higher
> frequency when compared with other options.
>
> >Is it better to use a free core or to buy a commersial one (e.g.
> >microBlaze), as free cores are not well tested and described and/or
> >analysising their internal structure might take too much time.
>
> If you want free, look at Leon, its a GPLed synthesized sparc. Not
> that fast (~20-25 MHz on a Virtex), and not that small (~6000 LUTs),
> but free and fully synthesized.
>
> --
> Nicholas C. Weaver nweaver@cs.berkeley.edu
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52165Hi there, Has anyone been successful using Tcl to start a SignalTap analysis? Altera's documentation appears very vague to me. So far I can run: sld open_session <signal_tap_file> .. and that works. But the semantics for the "sld run" are a mystery to me: sld run <instance> <signal_set> <trigger> The instance is easy. But where do I find the signal_set and trigger names? Any help is greatly appreciated ... -- PeterArticle: 52166
Paul, Initially, the foundry rules for use of the IO transistors had some restrictions. These restrictions were relaxed (somewhat) by the foundries. What that means is that all material (we didn't change anything) now meets the new specifications as outlined in the latest on line data sheet. http://direct.xilinx.com/bvdocs/publications/ds083-3.pdf tables 1 and 2. also see answer 14965 http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=14965 Austin Paul Sereno wrote: > I would like to get an update regarding the 3.3 volt tolerant I/Os in > the Virtex II Pro family. On July 4/6/8 2002 there were a discussion > in this group about this subject and from that discussion I concluded > that there is a limit on the amount of I/Os that are 3.3v tolerant. > However, in the updated Virtex II Pro datasheet there is no mention > about this limit. Has it been fixed? > Any of you, specially any Xilinx guys, could you please give us any > update in this regards? > I will do appreciate it... > > Thanks very much, > > Paul Sereno > Digital Design EngineerArticle: 52167
Has anyone used the terminator technology in Altera Stratix FPGA's? Did it work? Was it reliable? I had heard some third hand news describing a problem configuring the terminator resistance value from the RUP/RDN pins. PaulArticle: 52168
"Steve" <NOSPAM@tin.it> schrieb im Newsbeitrag news:ODo%9.75995$YG2.2164405@twister1.libero.it... > > The signal quality from the parallel port is often not really good, so > using > > STROBE as a clock for a FPGA is a big NO-NO, the slow edges, ringing and > > reflections will cause doule clocking -> mess up of state machines. > > Thanks! I will consider this. > But what about input lines (Ack, Busy, PE...)??? Can a Spartan output > (LVTTL) drive these signals without problems? Should work fine with a 3.3V IO Bank. -- MfG FalkArticle: 52169
"john jakson" <johnjakson@yahoo.com> schrieb im Newsbeitrag news:adb3971c.0302021829.30facbf@posting.google.com... > One crazy idea would be to modulate the voltage, higher voltage would > give some extra speed boost, but would also stress the chip. If the > speed is only needed at very low duty cycles then the stress would be I think you gain some speed without leaving the legal ground of the specs. Turn up the core voltage to max (+5%) Cool the device down to -40 C. This may give ~ twice the speed of the usual worst case calulation used for static timing analyze (+85 C, -5%) -- MfG FalkArticle: 52170
Paul, Since they chose a reference value of 10X, it makes their solution 10 times more sensitive to noise, cross talk, ground bounce, and vcc bounce. I would be interested to hear if their solution is fussy, or difficult to use. Even if the rumor is unconfirmed, we can say that we chose reference resistors of 1X to prevent just such problems. Austin Paul Martek wrote: > Has anyone used the terminator technology in Altera Stratix FPGA's? > Did it work? Was it reliable? I had heard some third hand news > describing a problem configuring the terminator resistance value from > the RUP/RDN pins. > > PaulArticle: 52171
Further to this IO rating thread, this is what we are finding
wrt higher IO operating capable devices.
We need a relatively simple (by todays yardstick), low Iq,
currently available and supported QFP FPGA that can
replace parts of a 5V mixed signal system.
Nothing fancy, but it seems, not so simple..
As dies shrink, Voltage of the core goes down (quite understandable)
However, there are also two side effects :
a) Quiescent or static Icc has climbed, with 5-10mA now common, where
100uA was prev possible.
b) IO voltage ratings have dropped
Factor b) is what I'd call a lazy side effect of shrinks, and it seems
Lattice may have taken the trouble to find a solution.
I see that their new isp4000Z now states :
Absolute Maximum Ratings
ispMACH 4000C/Z ispMACH 4000B ispMACH 4000V
(1.8V) (2.5V) (3.3V)
VCC -0.5 to 2.5V -0.5 to 5.5V -0.5 to 5.5V
VCCO -0.5 to 4.5V -0.5 to 4.5V -0.5 to 4.5V
i.o.ts -0.5 to 5.5V -0.5 to 5.5V -0.5 to 5.5V
#4. Undershoot of -2V and overshoot of (VIH (MAX) + 2V), up to a total
pin voltage of 6.0V, is permitted for a duration of < 20ns.
#5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed.
[IIH 3.6V < VIN = 5.5V, Tj = 130°C : < 20uA ]
[Iq 25'C 13.5uA typ ]
Their note #5 is interesting, and very similar to the OP question.
Q: Why limit the number of IO at higher IO - is the voltage stress
somehow strangely additive ?
Q: If there is a limit at all, does that mean that higher IO voltage
have a reliability/stress factor ?
Q: Is this done with thicker oxides on IO, or by a nudge of the
foundry rules ?
Comments anyone ?
This is not a FPGA, but it does indicate what can be done with 1.8V
core process.
-jg
Austin Lesea wrote:
>
> Paul,
>
> Initially, the foundry rules for use of the IO transistors had some
> restrictions. These restrictions were relaxed (somewhat) by the
> foundries.
>
> What that means is that all material (we didn't change anything) now
> meets the new specifications as outlined in the latest on line data
> sheet.
>
> http://direct.xilinx.com/bvdocs/publications/ds083-3.pdf tables 1
> and 2.
>
> also see answer 14965
>
> http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=14965
>
> Austin
>
> Paul Sereno wrote:
>
> I would like to get an update regarding the 3.3 volt
> tolerant I/Os in
> the Virtex II Pro family. On July 4/6/8 2002 there were a
> discussion
> in this group about this subject and from that discussion I
> concluded
> that there is a limit on the amount of I/Os that are 3.3v
> tolerant.
> However, in the updated Virtex II Pro datasheet there is no
> mention
> about this limit. Has it been fixed?
> Any of you, specially any Xilinx guys, could you please give
> us any
> update in this regards?
> I will do appreciate it...
>
> Thanks very much,
>
> Paul Sereno
> Digital Design Engineer
Article: 52173
Hello there,
I am desiging a device that uses table lookups on processing of
information (Writing an AES core). However as many as sixteen 256x8 bits
tables should be used. These tables are equal in content, however they have
independent indexing.
I was wondering about how to group them, so that I could use FPGA´s
memory intead of registers. Is it possible to use a multi-output memory? How
to?
I am using a APEX20K200 with Quartus II 2.0 and Leonardo and writing in
VHDL.
Thank you,
Roberto Gallo.
Article: 52174I want to know if we can convert a schematic design to a VHDL file inside a xilinx project.Do I need any external software to do that? --bams
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