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"David Brown" <david@no.westcontrol.spam.com> writes: > be very interesting to look at soft cpus. Speed is not really an > issue, but temperature is - we would like components rated as high a > temperature as possible. I would investigate the temperature issue. Contact Memec (Xilinx) and EBV or Arrow (Altera). The Memec Xilinx FAE is very knowledgeable. The EBV guys are very helpful and good at getting you in contact with the right people at Altera. I'm working on the larger devices where there are multiple engineers working on the same design. Most of our tools runs under Linux, e.g. Synopsys VCS, Synopsys DC, Cadence signalscan, etc. For our environment Altera fits better since the Quartus tools runs under Linux (without Wine emulation). But if you're using Windows in a one-engineer-one-design this is not an issue. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 52726
> > Hi Jan > > I am not so much worried about AHB interface any way it is a standard.I am > > confused with the design of the core.The core will finally > > become the part of an SoC which has ARM processor core .I want to get some > > guidlines to the core design so as to make the core programmable by the ARM > > processor.Any refrerence design or documents about a core design for an Soc > > Hmm, what kind of a core are you designing ? > > Perhaps you should take a look at www.opencores.org, there > you will find many, many different IP cores. Perhaps doing > some research on your own will answer your question. > > Regards, > rudi Huh, wierd I can't see your reply Geeko. Maybe because it's posted in one of the other newsgroups? Oh well, I can see it in Rudi's reply. So you want to create a peripheral that can be configured (to some extend) by the ARM processor. That is quite easy to do. You're peripheral will be addressed by the ARM with an unique address. Well nothing stops you from using an addressrange. According to the ABH spec an AHB peripheral occupies the memorymap in blocks of 1024 bytes (check the spec because I'm not sure about this number). So when the peripheral is activated you only need to check the lowest bits of the address. In this way you can easily put data into some registers. This data can be anything from setting the behaviour to parameters for some sort of calculation. The software is responsible to put the correct data into this register. From software point of view it's just pointer accesses to certain locations in memory. If your peripheral is located at base address 0x1000000 and it occupies 800 bytes then the memory range for that peripheral is 0x1000000 to 0x1000319 or base + 0x0 to base + 0x319. And the peripheral only checks the lowest bits so 0x0 to 0x319 (just ignor the upper part of the address). Mind that for the AHB there are some restrictions on the boundaries of that 1024 bytes block (burst mode I think). Also try to limit the number of real bus accesses. Writing 4 bytes on a 32 bit bus to address 0x1000000 is faster than writing the same to 0x1000001. Hope this answers your questions? kind regards, JanArticle: 52727
chris Shaw schrieb: > I'm trying to rebuild an old ABEL file and I don't seem to be able to > get any of the tools - abl2pld, abl2edif, etc - to produce an output > netlist. They all fail from 2.1i to 4.1i. > > What I *do* get is a warning message saying that the tools can't find > some file called Xabel.msg > I dont know your software environment, but webpack does all the ABEL very well e.g. for the XILINX 9500 devices greetings, BertramArticle: 52728
Dear Neeraj, On Wed, 19 Feb 2003, Neeraj Varma wrote: > If you can use OTP device, Xilinx has XC17V08 (8 Mbits) and XC17V16 > (16Mbits). If you want reprogrammable, you can look at Xilinx System ACE in > which they have an MPM module which integrates an AMD flash memory, which > can give 16, 32 and 64 Mbits of configuration memory in a single chip. > Here's the link > http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=system_ace I'm afraid we can't use the Xilinx System ACE, because we'll need a new board to integrate this solution. I try to find a programmable PROM, which fits in the same place as the old XC18V04. Thank you for you help anyway. Lars. -- GnuPG public key: http://www.ida.ing.tu-bs.de/~larsu/larsu_ida_ing_tu-bs_de.keyArticle: 52729
Hi Peter and David. Is Cyclone realy abvalible it is! That a cheep shoot Peter and not worhy comming from a competitor to Altera (contact some of your customers if you would like to see one :) Or shall we start discussing the delays involved with Virtex2-Pro and All copper I do have a statement from your CEO that is rather funny (pls step out of the sandbox). All chips will have difficulties meeting spec at elevated temperature booth Altera and Xilinx is using founderies so as someone wrote flip a coin they booth would be likely to work or not work on same temp. Coming back to tools from that point of things Altera SOPC builder is better than Microblaze dev. tools (alltough I have never used the tools for MicroBlaze), there is a complete dev kit to Nios cost roughly 1k$ including everything licens and so forth. There will also be a kit with a cyclone part on it coming out in a few weeks (another chance for you Peter to see one). Please look at Nios Home page at: http://www.altera.com/products/devices/nios/nio-index.html Cheers Fredrik Peter Alfke <peter@xilinx.com> wrote in message news:<3E53BB44.8EFDDEC0@xilinx.com>... > David, > when I read "highest temperature" and "Norway", I assume this is for a > down-hole oil-exploration drilling application. Xilinx devices have been used > for such applications for many years. I remember that users reported week-long > operation at 175 degr C, but that may have been a ceramic-packaged hybrid > circuit. They also intended to try 200 degr C, but I never heard the results. > Silicon usually works fine at 175, but timing parameters are slower, and of > course not guaranteed. The plastic package material is usually the first one to > give problems at very high temperatures. > Xilinx offers MicroBlaze as a soft microprocessor. > > You mention Spartan and Cyyclone. These are the low-cost FPGA families from the > two vendors ( Is Cyclone really available?). > In your case, where the absolute lowest component cost is not the issue, you > should also consider Virtex-II from Xilinx. But the Spartan-II family goes down > to smaller chip sizes. > You can download the software :-) > > Greetings > Peter Alfke, Xilinx Applications > > David Brown wrote: > > > We are going to be using an fpga in a future product, and are trying to > > decide which family to use. The most likely candidates seem to be Xilinx > > Spartan or Altera Cyclone. The application will involve a error checking > > and correcting for a communications link, plus a few other bits of control > > logic. There is nothing too complex in it, nor do we need very high speed > > (we are talking 100 kHz max), but it is more than I would like to fit into a > > small microcontroller, which would be the alternative solution. We also > > need a microcontroller on the board for a few other functions, so it could > > be very interesting to look at soft cpus. Speed is not really an issue, but > > temperature is - we would like components rated as high a temperature as > > possible. > > > > The price of the chips themselves is not a major issue, since we would only > > be looking at a few systems, but the price of development kits (simple demo > > card, programming cabel, basic developement tools) is correspondingly more > > relevant - especially since we will probably need two sets. > > > > I have had some experiance using a cpld (Mach 4), and would prefer to work > > in VHDL, with Verilog as a second choice. If we go for an embedded cpu, > > then I am quite happy working with gcc and gdb ports, as long as I can get > > some basic debugging access to the processor (via jtag, or a serial port) to > > start/stop the processor, read and write memory, and (hopefully) at least > > one hardware breakpoint. > > > > We can expect good support from our distributers for either Xilinx or > > Altera, but I would value any opinions others here may have about which we > > should choose, or pointers to any web pages that could help us decide. > > > > David Brown > > NorwayArticle: 52730
Bertram Geiger wrote: > chris Shaw schrieb: > > I'm trying to rebuild an old ABEL file and I don't seem to be able to > > get any of the tools - abl2pld, abl2edif, etc - to produce an output > > netlist. They all fail from 2.1i to 4.1i. > > > > What I *do* get is a warning message saying that the tools can't find > > some file called Xabel.msg > > > > I dont know your software environment, but webpack does all the ABEL > very well e.g. for the XILINX 9500 devices > greetings, Bertram Thanks to both you & Jim. I've now found out, sort of, whats going on. The old BLIF flow that I used to use via the command line + makefiles is now obsolete and has been replaced by ABEL-XST. Deeply embedded in it is one of the old programs - ahdl2blf - but it no longer seems possible to run it from a command line so I've had to go by the &^%$)**ing GUI. Not only that but our main tool set is Alliance so we don't actually have XST so I had to download 100MB+ of WebPACK to get it all to work. No too bad while I'm in the office on a 2Mb link but its going to be tedious to do from home! All I wanted to do was to produce a .pld file which I could convert to a Verilog simulation model via NGDBUILD/NGD2VER ... sigh.Article: 52731
Does anyone have any experience of Inventra/Mentor USB function controller IP? More specifically, has anyone had any problems with servicing interrupts too fast (!!!) and/or problems receiving extra data on endpoint zero (ie. packets with data out phases). Thanks in advance, Gary PartisArticle: 52732
"Fredrik" <fredrik_he_lang@hotmail.com> wrote in message news:77a94d51.0302200139.193a8ad1@posting.google.com... > Hi Peter and David. > Is Cyclone realy abvalible it is! That a cheep shoot Peter and not > worhy comming from a competitor to Altera (contact some of your > customers if you would like to see one :) Or shall we start discussing There's nothing like a bit of healthy competition to improve the products :-) > the delays involved with Virtex2-Pro and All copper I do have a > statement from your CEO that is rather funny (pls step out of the > sandbox). All chips will have difficulties meeting spec at elevated > temperature booth Altera and Xilinx is using founderies so as someone > wrote flip a coin they booth would be likely to work or not work on > same temp. Coming back to tools from that point of things Altera SOPC > builder is better than Microblaze dev. tools (alltough I have never > used the tools for MicroBlaze), there is a complete dev kit to Nios > cost roughly 1k$ including everything licens and so forth. There will > also be a kit with a cyclone part on it coming out in a few weeks > (another chance for you Peter to see one). > Please look at Nios Home page at: > http://www.altera.com/products/devices/nios/nio-index.html > Cheers > Fredrik I've had a look at the web pages for both Xilinx and Altera, but as another poster said, both will do the job we need. > > Peter Alfke <peter@xilinx.com> wrote in message news:<3E53BB44.8EFDDEC0@xilinx.com>... > > David, > > when I read "highest temperature" and "Norway", I assume this is for a > > down-hole oil-exploration drilling application. Xilinx devices have been used > > for such applications for many years. I remember that users reported week-long > > operation at 175 degr C, but that may have been a ceramic-packaged hybrid > > circuit. They also intended to try 200 degr C, but I never heard the results. > > Silicon usually works fine at 175, but timing parameters are slower, and of > > course not guaranteed. The plastic package material is usually the first one to > > give problems at very high temperatures. > > Xilinx offers MicroBlaze as a soft microprocessor. > > > > You mention Spartan and Cyyclone. These are the low-cost FPGA families from the > > two vendors ( Is Cyclone really available?). > > In your case, where the absolute lowest component cost is not the issue, you > > should also consider Virtex-II from Xilinx. But the Spartan-II family goes down > > to smaller chip sizes. > > You can download the software :-) > > > > Greetings > > Peter Alfke, Xilinx Applications > > > > David Brown wrote: > > > > > We are going to be using an fpga in a future product, and are trying to > > > decide which family to use. The most likely candidates seem to be Xilinx > > > Spartan or Altera Cyclone. The application will involve a error checking > > > and correcting for a communications link, plus a few other bits of control > > > logic. There is nothing too complex in it, nor do we need very high speed > > > (we are talking 100 kHz max), but it is more than I would like to fit into a > > > small microcontroller, which would be the alternative solution. We also > > > need a microcontroller on the board for a few other functions, so it could > > > be very interesting to look at soft cpus. Speed is not really an issue, but > > > temperature is - we would like components rated as high a temperature as > > > possible. > > > > > > The price of the chips themselves is not a major issue, since we would only > > > be looking at a few systems, but the price of development kits (simple demo > > > card, programming cabel, basic developement tools) is correspondingly more > > > relevant - especially since we will probably need two sets. > > > > > > I have had some experiance using a cpld (Mach 4), and would prefer to work > > > in VHDL, with Verilog as a second choice. If we go for an embedded cpu, > > > then I am quite happy working with gcc and gdb ports, as long as I can get > > > some basic debugging access to the processor (via jtag, or a serial port) to > > > start/stop the processor, read and write memory, and (hopefully) at least > > > one hardware breakpoint. > > > > > > We can expect good support from our distributers for either Xilinx or > > > Altera, but I would value any opinions others here may have about which we > > > should choose, or pointers to any web pages that could help us decide. > > > > > > David Brown > > > NorwayArticle: 52733
"Peter Alfke" <peter@xilinx.com> wrote in message news:3E53BB44.8EFDDEC0@xilinx.com... > David, > when I read "highest temperature" and "Norway", I assume this is for a > down-hole oil-exploration drilling application. Xilinx devices have been used I'm not sure how much I'm allowed to reveal about the application, but your post was very helpful :-) > for such applications for many years. I remember that users reported week-long > operation at 175 degr C, but that may have been a ceramic-packaged hybrid > circuit. They also intended to try 200 degr C, but I never heard the results. > Silicon usually works fine at 175, but timing parameters are slower, and of > course not guaranteed. The plastic package material is usually the first one to > give problems at very high temperatures. We intend to underclock the fpga quite significantly, so timing should not be a problem (this will also avoid generating heat in the fpga die itself). > Xilinx offers MicroBlaze as a soft microprocessor. > > You mention Spartan and Cyyclone. These are the low-cost FPGA families from the > two vendors ( Is Cyclone really available?). > In your case, where the absolute lowest component cost is not the issue, you > should also consider Virtex-II from Xilinx. But the Spartan-II family goes down > to smaller chip sizes. Smaller chip size is important - are there any particular reasons for suggesting Virtex-II, assuming the design will fit it a Spartan? mvh. David > You can download the software :-) > > Greetings > Peter Alfke, Xilinx Applications > > David Brown wrote: > > > We are going to be using an fpga in a future product, and are trying to > > decide which family to use. The most likely candidates seem to be Xilinx > > Spartan or Altera Cyclone. The application will involve a error checking > > and correcting for a communications link, plus a few other bits of control > > logic. There is nothing too complex in it, nor do we need very high speed > > (we are talking 100 kHz max), but it is more than I would like to fit into a > > small microcontroller, which would be the alternative solution. We also > > need a microcontroller on the board for a few other functions, so it could > > be very interesting to look at soft cpus. Speed is not really an issue, but > > temperature is - we would like components rated as high a temperature as > > possible. > > > > The price of the chips themselves is not a major issue, since we would only > > be looking at a few systems, but the price of development kits (simple demo > > card, programming cabel, basic developement tools) is correspondingly more > > relevant - especially since we will probably need two sets. > > > > I have had some experiance using a cpld (Mach 4), and would prefer to work > > in VHDL, with Verilog as a second choice. If we go for an embedded cpu, > > then I am quite happy working with gcc and gdb ports, as long as I can get > > some basic debugging access to the processor (via jtag, or a serial port) to > > start/stop the processor, read and write memory, and (hopefully) at least > > one hardware breakpoint. > > > > We can expect good support from our distributers for either Xilinx or > > Altera, but I would value any opinions others here may have about which we > > should choose, or pointers to any web pages that could help us decide. > > > > David Brown > > Norway >Article: 52734
"Petter Gustad" <newsmailcomp4@gustad.com> wrote in message news:m37kbvnzzv.fsf@scimul.dolphinics.no... > "David Brown" <david@no.westcontrol.spam.com> writes: > > > be very interesting to look at soft cpus. Speed is not really an > > issue, but temperature is - we would like components rated as high a > > temperature as possible. > > I would investigate the temperature issue. Contact Memec (Xilinx) and > EBV or Arrow (Altera). The Memec Xilinx FAE is very knowledgeable. The > EBV guys are very helpful and good at getting you in contact with the > right people at Altera. > We had EBV guys here a couple of weeks ago, and Memic a few days ago - both appeared to have a good level of technical support (and we've been very happy with their support on other products in the past), and both are very keen on selling us their preferred fpga family. It would be a lot easier if one of them had been a bit less compentent or enthusiastic to help :-) > I'm working on the larger devices where there are multiple engineers > working on the same design. Most of our tools runs under Linux, e.g. > Synopsys VCS, Synopsys DC, Cadence signalscan, etc. For our > environment Altera fits better since the Quartus tools runs under > Linux (without Wine emulation). But if you're using Windows in a > one-engineer-one-design this is not an issue. We will be a couple of engineers using the tools, running mainly Windows. I run linux at home and may one day use it at work, but in the mean time wine emulation is probably good enough. > > Petter > -- > ________________________________________________________________________ > Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 52735
I observed, there are 3 synthesis tools for FPGA : - Leonardo Spectrum from Mentor Graphics - Precisions (new version of Leonardo Spectrum) - Symplify Pro from Simplicity =20 Anyone here has experience which some of them ? What is the major = difference among them ? =20 Thanks :) =20 Cheers, =20 BuzzArticle: 52736
> You will need to provide more details, but from what you wrote, it
> sounds to me what you are trying to do is to convert some kind of bus
> protocol to PCI's protocol.
Well, at the moment I've got a data bus and an event bus in my
device. I had originally planned on using one of SMSC's 100mbit
ethernet MAC/PHY combos (really nice little chips) which would have
allowed me to essentially just clock in and clock out ethernet frames.
> If someone has already developed such a bridge chip (an ASSP), you
> should use that instead of developing one from scratch.
Well, so PLX appears to have developed some bridges that would at
least make things slightly easier. However, 1. they are not cheap (and
I'm on a bit of a budget for total project cost) and 2. I fear that
figuring out how to interface them to the device and then interface
them to my side of things will take just as long as developing the PCI
IO myself.
> else.), and how many people will be working on this project (It's nice
> to let someone else do the testbench because the circuit designer
> won't want to work on the testbench.).
It's just me here. It looks like it's going to be a long weekend
ahead...
> Since your PCI bridge is going to have a point-to-point
> connection to the PCI gigabit ethernet chip, you might be able to
> relax the standard setup time of 7ns for 33MHz PCI and 3ns for 66MHz
> PCI to 10ns and 5ns, respectively, although no such timing parameters
> are officially defined by the PCI specification.
Okay, I'm looking at 32-bit 33 MHz. I care less about developing a
reusable PCI IP core and more about getting a self-contained MAC
interface.
> Considering the complexity of PCI, and the trouble of writing
> the testbench code, anyone smart enough to develop a PCI interface has
> turned into a business (I am thinking of doing that, too.).
I've noticed that, perhaps I should take it as a hint.
> Other than Opencores.org PCI IP core
> (http://www.opencores.org/projects/pci/), there aren't too many free
> or open source designs related to PCI.
I've had a bit of difficulty figuring out exactly how their core
works, although that might just be because I'm a VHDL guy.
> If you have to develop a PCI bridge from scratch, obtain a copy of the
> PCI specification, and take a look at Appendix B of it.
> Appendix B has an example target and initiator state machine, and that
> should be your starting point.
Actually I found one on the web -- thank you google!
> You should never try to copy the entire Appendix B because if you do
> so, you will see signal glitches coming out of the chip, and several
> protocol rules aren't being followed in the Appendix B example.
Could you maybe give a bit more insight into this? What if I
register the outputs?
> Steve, does your project have to deal with 5V PCI?
> If that's the case, you will have to use the older Spartan-II instead
> because Spartan-IIE doesn't support 5V PCI, although 3.3V PCI is still
> supported.
Nope, just 3.3v on this IC. The data sheet appears to give pretty
reasonable explanation of how the PCI IO works for the device...
http://www.national.com/ds/DP/DP83820.pdf seems to suggest there might
be some places where I can cut corners.
I'm also curious about how people implemented things like FIFOs
when they developed their interfaces. I've been spoiled before, always
doing FIFOs in spartan-II blockselect+ ram blocks, which are dual
ported. But it would seem that to get a decent-size (say, 256 KB) FIFO
in dual-ported ram would be really expensive, and so I need to go with
standard (although cheap!) SRAM. I've been thinking about clocking the
actual FPGA at 66 MHz and interleaving FIFO read-write access. Might
anyone have had any experience with this sort of thing ?
Thanks again for all the help,
Steve
Article: 52737Sorry, just a terminology mix-up. I'm trying to send about 12 MB/sec of data from my device to a rack of 4 PCs. Its just barely over 100mbit spec (although in reality, it would be quite a bit over). I'm using UDP broadcast with a really simple packet sequence-number-resend scheme should any packets be dropped in the process. Gigabit is a bit overkill, but it should still work. The NS DP83820 has a nice sister PHY, and a good app note about gluing them together. hmurray@suespammers.org (Hal Murray) wrote in message news:<v58jn1fsifvpb9@corp.supernews.com>... > > I'm trying to interface my project to a gigabit ethernet > >transceiver (DP83820) but alas, the interface is only PCI. Has anyone > >ever tried doing this sort of quick-hack PCI interface, just to talk > >to a single PCI peripheral? What timing constraints become less of an > >issue in this situation? Might anyone know of any example code for > >this sort of thing? Any general suggestions? > > That chip is a packet processor, not a transceiver. > > What are you really looking for? Do you just want to use > ethernet to get some data from your chip to someplace else? > (Just a fast RS-232.) >Article: 52738
There is not an error,just the warnings bellow I saw the Synthesis Report as well:no errors What is exit code 0002? (Done: failed with exit code: 0002.)Article: 52739
Lars Unger wrote: > Hi there, > > Currently we are using a board with a Virtex XCV600 and a XC18V04 in system > programmable configuration PROM. The XC18V04 (4-MBit) comes in a VQ44 package. > As we want to upgrade to a Virtex XCV800 we need a larger configuration device. > Referring to the Xilinx documentation we need an additional device for this > purpose. However we don't want to change the board layout. > > Does anyone know if there is a pin compatible configuration PROM in the give > package with a greater memory size ? Or even know another solution ? > > Any help is much appreciated. > > Best wishes, > Lars. Have you already taken a look at the Atmel AT17 parts? They have an Xilinx Virtex compatible 8MBit-Device that could be usable for you. Pinout is not exactly the same. Atmel has some NCs where Xilinx has Vcc and some Control inputs where Xilinx has NCs or Data I/Os and In-System-Programming is done via I2C instead JTAG. Depends on your Design if the part is usable. HTH, JensArticle: 52740
Peter Alfke wrote: > David, > when I read "highest temperature" and "Norway", I assume this is for a > down-hole oil-exploration drilling application. Xilinx devices have been used > for such applications for many years. I remember that users reported week-long > operation at 175 degr C, but that may have been a ceramic-packaged hybrid > circuit. They also intended to try 200 degr C, but I never heard the results. > Silicon usually works fine at 175, but timing parameters are slower, and of > course not guaranteed. The plastic package material is usually the first one to > give problems at very high temperatures. > Xilinx offers MicroBlaze as a soft microprocessor. Hmm. Any micro would be soft at 200degC ;)Article: 52741
Ron, Looking at this it would appear that you have a path crossing two clock domains (I noticed something about a falling edge in there too) - this is quite risky in an FPGA. You may need to revisit the design and check that this is the case, and if so how can it be avoided. Sorry that this doesn't really solve the problem as stated, but this sort of problem is better prevented than cured. Online resources about synchronous FPGA design will give information on the coding style necessary to achieve this. regards, Chris rathanon99@yahoo.com (ron) wrote in message news:<c661162.0302190111.502bb520@posting.google.com>... > I got this message from the static timing analyzer of xilinx ISE. > Apparently, I have 3 hold violations. One of them has the following > information. How do you solve this? Thank you and hope to hear from > you soon. > > Hold Violations: Default period analysis > > -------------------------------------------------------------------------------- > Hold Violation: -8.816ns (data path - positive clock skew) > Source: inst_id_ex_inst_block_im8_out_2 > Destination: u_shift_mux_reg_out_sig_2 > Data Path Delay: 8.315ns (Levels of Logic = 4) > Positive Clock Skew: 17.131ns > Source Clock: inst_clk_out_inst_block_I_cp15clk_11 falling > Destination Clock: inst_clk_out_inst_block_I_cp15clk_13 falling > Timing Improvement Wizard > Data Path: inst_id_ex_inst_block_im8_out_2 to > u_shift_mux_reg_out_sig_2 > Delay type Delay(ns) Logical Resource(s) > ---------------------------- ------------------- > Tcko 0.772 inst_id_ex_inst_block_im8_out_2 > net (fanout=1) 0.357 inst_id_ex_inst_block_im8_out_2 > Tilo 0.398 u_bmux_Mmux_b_out_sig_inst_lut3_225 > net (fanout=3) 0.658 > u_bmux_Mmux_b_out_sig_xstmacro_int_tempname303 > Tif5 0.752 > u_bmux_Mmux_b_out_sig_xstmacro_int_tempname303_rt > > u_bmux_Mmux_b_out_sig_inst_mux_f5_100 > net (fanout=20) 4.781 > u_bmux_Mmux_b_out_sig_xstmacro_int_tempname304 > Tcki (-Th) -0.597 u_shift_mux_I_shift_sig_2_1 > u_shift_mux_reg_out_sig_2 > ---------------------------- ------------------------------ > Total 8.315ns (2.519ns logic, 5.796ns route) > (30.3% logic, 69.7% route)Article: 52742
If I understand your question, then it's when you overdrive the gate a pass transistor to make sure it *really* turns on. The big problem with pass-transistor logic is that you get a Vth drop across an nmos pass transistor when you drive through it. This degrades the signal passing through the pass gate, causing reduced performance. There are also power implications. However the voltage drop is relative to the value applied to the gate. By driving the gate with a higher voltage than you use for the signal that is passing through the pass gate, you reduce the magnitude of the degradation -- potential completely removing it, if you can tolereate voltages that high. The cons are that you need to generate this higher gate voltage (you now have two different Vcc values) off chip or on chip via charge pumps. And you need to route an extra power network. And most importantly, the amount you can overdrive your gates by depends on the process technology you are using -- the stronger your overdrive, the more likely you will run into reliability issues with the transistor. Do companies do this? I don't know and/or can't say :-) Regards, Paul "digari" <digari@dacafe.com> wrote in message news:e0855517.0302190344.5bce1783@posting.google.com... > What is gate boosting? what are the pros and cons of the technology? > Does is it being used in any FPGA device?Article: 52743
Have anyone else had this problem? Or does anyone have a possible solution? This morning Quartus II (Ver 2.1 SP1 for PC) decided to stop compiling. Whenever I click on "Start Analysis & Synthesis" or "Start Compilation" or use the menu commands to do the same, the compiler start to initialize and then ends with the message "Netlist Extraction and synthesis was NOT successive" but the actual compilation has never started and there are no error messages or warnings in the messages window. This happens for ALL designs (the tutorials that came with Quartus, some old designs that I haven't touched in a few months and some small test-designs I created to test what is going on) and it seems to happen for all device selections too. I'm not using any third party EDA tools so this is a Quartus problem. A full uninstall (and registry wipe) and then reinstallation didn't solve the problem. The only other solution I can think of (while I wait for Altera to respond to my service request) is to reinstall windows, but I really don't want to do that unless it is absolutely necessary! Please let me know if you have any ideas to solve this issue! Regards ZXArticle: 52744
Usually the megafunctions are a pretty decent implimentation. When the structure it implements requires memory it will automatically use the memory bits in the FPGA to implement this. Also, if you use a Stratix device, the LPM_Multiplier will be implemented using a hardware multiplier. I would say that unless you're looking to make a small multiplier (say 4bit x 4bit) you're probably not going to get a better implementation in a reasonable time. ZX "jonno" <jjacox@NULLpmdi.com> wrote in message news:OtT4a.29940$na.792646@news2.calgary.shaw.ca... > How good in terms of size and speed are built-in MegaFunctions (such as > divide, multiply, etc)? Are they implemented well for most applications or > are they too general for a "tight" design? > > If I want this: > /**************/ > in_a[9..0]; > in_b[11..0]; > out[21..0]; > > out = in_a * in_b; > /**************/ > > When I compile this, the multiply uses LPM_MULTIPLY but I wonder how optimal > it is. Is it worth my time to make my own multiply routine? > >Article: 52745
nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) wrote in message news:<b30mul$24jg$1@agate.berkeley.edu>... > In article <3E53D682.FDC2F186@xilinx.com>, > Peter Alfke <peter@xilinx.com> wrote: > >I agree with Hal's comments. > >And let me ask: Is a 2-layer board really any cheaper than a 4-layer > >board? I know it was in the past century, but is there really a > >significant price difference nowadays ? > > Yes. By a fair amount. > > A 2 layer board is really, REALLY cheap, with prototype to production > techniques for 1-3 day turnaround and quick rampup to large volumes. > > The price difference between 2 and 4 layer is over 50% for something > like PCBpro (2x3" board, 100 pieces, 1 week turnaround). Its $448 for > a 2 layer board and $783 for a 4 layer board. Holy moly that's expensive! $783 for ONE two layer board? Oh, wait - you must mean $783 for 100 of them. In that case, HOLY MOLY THAT's cheap! For comparison, I just had ~10 PCB's made on a 1 week turn. They are 6x16", 12 layers, with small vias, small line widths, and small line spacing. They were in the $600's. Each. The part with the highest pin density is a Spartan IIE in a FG456 package with most of the I/O used up - it only needed four routing layers. At the same time, we turned a different version of the same sized PCB, same rules, but with 16 layers. It was in the $800's, each. So each layer on a quick turn, in low quantity, is costing us ~$50. Obviously as the number of layers drop, the % of cost savings goes up for each additional layer. > However, given the cost of designer time and all, unless you really > NEED the 1 day board-fabrication turnaround time you can get with a 2 > layer board, or that the part cost on the board really REALLY matters, > 4 layers seem like cheap insurance. I agree. You don't want to have to be guessing that the problem is poor ground or power (and then somehow improving it on the PCB you have in your hands). MarcArticle: 52746
Hi, do you have two active TCP/IP ethernet NICs? If so, disconnect one cable or disbale TCP/IP binding to one of the cards. Thorsten "ZX" <ZX@TheEmail.com> schrieb im Newsbeitrag news:b32ktu$2fs7$1@news.adamastor.ac.za... > Have anyone else had this problem? Or does anyone have a possible solution? > > This morning Quartus II (Ver 2.1 SP1 for PC) decided to stop compiling. > Whenever I click on "Start Analysis & Synthesis" or "Start Compilation" or > use the menu commands to do the same, the compiler start to initialize and > then ends with the message "Netlist Extraction and synthesis was NOT > successive" but the actual compilation has never started and there are no > error messages or warnings in the messages window. > > This happens for ALL designs (the tutorials that came with Quartus, some old > designs that I haven't touched in a few months and some small test-designs I > created to test what is going on) and it seems to happen for all device > selections too. I'm not using any third party EDA tools so this is a Quartus > problem. > > A full uninstall (and registry wipe) and then reinstallation didn't solve > the problem. The only other solution I can think of (while I wait for Altera > to respond to my service request) is to reinstall windows, but I really > don't want to do that unless it is absolutely necessary! > > Please let me know if you have any ideas to solve this issue! > > Regards > ZX > >Article: 52747
You may also be getting into an unstable region beyond the number of samples you simulated. Can you capture
samples immediately after reset to see if that matches your simulation. If that matches, then your algorithm
likely does not have long term stability (long term stability can be difficult to achieve in htis type of set-up
without a correction term) and you are simply looking at it after it has gone into the weeds. If the initial
samples do not match, then you need to do some digging to find out why. Make sure the fpga really got configured,
check for a clock, reset released etc.
Andy Peters wrote:
> akshaymishra@rediffmail.com (Akshay) wrote in message news:<937606cb.0302170535.2347978a@posting.google.com>...
> > Hello,
> > We are trying to generate a sine wave using the dsp iir filter
> > method but not able to get a sine wave. The vhdl code simulates a
> > correct sine wave output but the synthesized code does not give any
> > output on the fpga (xilinx virtex 2, xv2000).
>
> 1) Does the synthesis tool give you any errors or warnings?
>
> 2) The multiplier may be eating up a lot of area, and you may not be
> meeting timing. What's your clock speed? Have you set any timing
> constraints? Are you meeting the constraints?
>
> -ap
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52748
The difference is in ordering of the operations in the algorithm. A MAC fir uses one or more full parallel multipliers and an accumulator
(and an adder tree if more than one multiplier) to do the FIR computation in the familiar way done with software approaches. input sample
rate decreases as the number of taps increases for a fixed number of multipliers. The multipliers are fairly area intensive unless your
device has dedicated multipliers in it (the mac fir option is meant for virtex II). A MAC FIR can also suffer from loss of precision due to
truncation of multiplier outputs.
The distributed arithmetic version is a rearrangement of the arithmetic at a bit level to take advantage of the LUT structure of the FPGA.
See the distributed arithmetic page on my website for a detailed description of the algorithm.
Basuki Endah Priyanto wrote:
> Hi all,
>
> Could anyone tell me the differences between Distributed Arithmetic FIR Filter and and MAC Filter ? Both are obtained from Xilinx Coregen.
>
> What is the pros/cons ?
>
> Thx.
>
> Buzz
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52749
Here's code I've been using for several months with the 4.X web pack.
It synthesizes into Block ram with XST. Note that the read address
is pipelined - this was essential to getting XST to infer BRAM.
I hope this helps.
John P
// The following is the Verilog code for a dual-port RAM with synchronous
// read (read through). the Xilinx doc says that XST will infer this into
// block ram
module ram512b (
clk,
we,
wr_a,
rd_a,
di,
do
);
input clk;
input we;
input [8:0] wr_a;
input [8:0] rd_a;
input [7:0] di;
output [7:0] do;
reg [7:0] ram [511:0];
reg [8:0] read_a;
always @(posedge clk)
begin
if (we)
ram[wr_a] <= di;
read_a <= rd_a;
end
assign do = ram[read_a];
endmodule
"Dr. Jones" <#?!@tin.it> wrote in message news:<w%_4a.137352$ZE.3932175@twister2.libero.it>...
> Jim Wu <jimwu88NOOOSPAM@yahoo.com> wrote in message
> PJR4a.13695$_k4.3071@nwrddc03.gnilink.net...
> > > When my Block RAM exceeds 128 bits, the XST synthesizer seems to not
> >
> > Did you mean 128K bits block RAM?
> >
>
> No, no, 128 bits!!!
> [the device I use has a total of 64Kbits of block RAM]
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