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The errata sheet says to leave unconnected the VBATT pin to ensure meeting
the 750V HBM ESD spec.
Does this mean that the VBATT function is unusable in these chips, or can I
connect (and use) the VBATT function and just live with the ESD degradation?
Bill
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Article: 45201--------------FD5093FB9E194F8C1805F273 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit You may want to look at the first circuit in http://support.xilinx.com/support/techxclusives/MovingData-techX16.htm Peter Alfke ==================== Benjamin Todd wrote: > isn't that just a j-k flip flop? > > host controller is always setting > processor is always resetting > > --or something like this > interrupt_register : process (clock, reset) > if Reset = RESET_ACTIVE then > Interrupt <= '0'; > elsif rising_edge (clock) then > if Host_Controller_Interrupt = '1' then > Interrupt <= '1'; > elsif Processor_Interrupt_acknowledge = '1' then > Interrupt <= '0'; > end if; > end if; > end process interrupt_register; > > "Marcel" <marcelgl@hatespam.xs4all.nl> wrote in message > news:3d32f623$0$12305$e4fe514c@dreader4.news.xs4all.nl... > > > > I was wondering which is the best way to make some register with settable > > and clearable bits in VHDL. > > > > Suppose I have an embedded processor and a host controller. Host > controller > > sets a flag in a register, which causes in interrupt at the embedded one. > > When the interrupts is processed the embedded one clears the flag. > > > > This means that both sides must have access to the same flag. This can be > > solved with an asyncrhonous clear of the flipflop, but I was wondering > which > > is most commonly done in this kind of situations. > > > > Any suggestions ? > > > > > > Marcel > > > > > > > > > > > >Article: 45202
> >> In my application I need to let the FPGA communicate with the PC. (I want > >to write a small C++ program where you can enter some values) > >> The demo board I use offers an serial RS-232 port but only with TXin and > >RXout pins. So I suppose I must use some software handshake? > >> And i have to implement a serial/parallel converter within the FPGA (vhdl > >code?). > > Use Jtag. In the Xilinx you can have 2 custom user registers of any lenght. You can read and write to them. With Xilinx if you work out the Jtag protocals you can do things like partial reconfiguration, update look up tables or block ram at run time. We have a package for $69 that will let you write the 5 lines of code you need to talk to the Tx and Rx ports you mentioned. Steve Virtual Computer Corporation www.vcc.com > Implementing a simple SPI or JTAG type synchronous interface should > take a lot less space in the FPGA, and you could simply bit-bang on > the PC side via either the parallel port or serial port. > > Regards > Anton Erasmus > > > >Article: 45203
For Sale: XILINX xcs20xl-5pq208c 1550 pcs. PLD FPGA 20KGTS 3.3V XCS20XL-5 D/C 12/28/00 In Trays - Factory Packed Take All $30,000 USD (please email offer to bob@perecycle.com)Article: 45204
Hello all, What are good designs for mapping registers in an FPGA (Altera Flex 10KE in my case) into a microprocessors address space, to operate like asynchronous ram in terms of bus timing. For instance a module that will have 32 registers that can be read and written from the DSP (although for status registers the write will have no effect). The module should also generate synchronized single cycle write/read pulses after the data has been written to the register. The read part seems pretty easy just output enable the FPGA based upon the \CS and \RD signal, and a MUX to select the right register to put on the data bus. There is a synchronization issue if the register might be changing during a read. For my application read is either from a FIFO(So data is only updated immediately after a read, or from a bank of status bits , or read/write config registers. I guess there is a concern of metastability when a status bit is changing during a read, is this a problem I should be concerned with? For writing the situation seems more complicated. What are good techniques for latching the data on a write. It is especially complicated in my case because the FPGA clock is slower than the memory bus, such that it would be possible to do multiple writes per FPGA clock cycle. Naturally the microprocessor program should have waits to avoid writing multiple times per FPGA clock cycle, and the results of such a double write need not be meaningful, but it would all the same be possible. I've heard that FPGA have to build latches up from combinatorial logic, and that their performance is quite poor? I haven't tested this theory myself. Is The Timing diagrams for the microprocessors I've looked at make it look like I can use the \WR signal as a rising edge clock, and then decode the \CS and ADDR lines for an ENABLE signal for D-FF registers. Is this a good technique? I can also see how one could use the embedded memory in asynch mode to implement the registers. This would certainly be a very low overhead technique for the bus side, but would make it more complicated accessing the data inside the FPGA. I would probably have extra logic on the back that would take the synchronized write signal and use it to read the written memory to an internal register to hold for access by other modules in the design. I'm sure this is a very common issue in many designs, but I haven't seen it addressed in any books or online resources. If any of your know of some good resources on this issue, or are willing to share some insight, I'd love to hear it. Thanks, Joey NelsonArticle: 45205
Muzaffer Kal <kal@dspia.com> wrote in message news:<phk4jukqmu5t30f35ubcpaksbu4al5snda@4ax.com>... > On 14 Jul 2002 15:16:38 -0700, jdl1291@njit.edu (Joe Lawrence) wrote: > > >Greetings all, I am a newbie to FPGA & VHDL (currently a junior CoE at > >NJIT). I have a Xess XSA-50 protoboard with a XC2S50 FPGA and am > >using the latest Xilinx Webpack to create simple VHDL models like > >comparators, d-q FFs, carry bit adders, etc to get a feel for things. > >I run into trouble when I try to assign a signal in a process > >sensitivity list to various FPGA locations such as buttons, parallel > >port locations, etc. With my d-q FF, for example, I had wanted to use > >the push button as a 'clock' input. My code seems straightforward and > >simple enough: > > > >process (clk) > >begin > > > > if (clk'EVENT) AND (clk = '1') THEN > > -- flip flop code here > > end if; > > > >end process; > > > >However, if I assign clk to pin 93, the pushbutton, I receive the > >following error during the "Map" stage of "Implement Design": > > > >ERROR:MapLib:93 - Illegal LOC on symbol "clk" (pad signal=clk) or > >BUFGP symbol > > "clk_BUFGP" (output signal=clk_BUFGP), IPAD-IBUFG should only be > >LOCed to > > GCLKIOB site. > > > In FPGAs, the clock tree is already built-in and the input pin to it > can only be made from a limited set of pins. The mapper is telling you > that the pin you chose is not one of these. Also using the output of a > mechanical button as a clock is probably not a good idea. It would be > better to properly debounce the button input and use it as an enable > to the flop. > > Muzaffer Kal > > http://www.dspia.com > ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations Dear Muzaffer, one is not required to use a dedicated clock pin in order to use an input pin as a clock. Some of the disadvantages of not using a dedicated clock pin are: 1) The clock will get an additional delay due to propagation through non-dedicated resources. 2) The synthesis tools/P&R tools may give you an error (just like they did above). One way to overcome the error would be to explicitely instantiate the IBUF and the BUFG. One would possibly need to use the location constraints to select the approprite BUFG (there are 2 or more them). Another way, of course, would be to use the dedicated clock pin, just like you pointed out. Regards, YuryArticle: 45206
Hi. Is anyone aware of 3rd party place & route tools for Atmels AT40K and FPSLIC series? I know that their own "Figaro IDS" is available on the web site. I'm looking for alternatives. MarcArticle: 45207
I just checked the library guide, and it seems BUFG can only be used for clocks. One thing I can say about synthesis tools is that if you are trying to do something unusual, you will likely end up, 1) Instantiating Xilinx specific primitives in your code, or 2) You will have to edit the EDIF netlist generated with a text editor. In my case, in order to push a FF into an IOB, that FF needs to have a fanout of 1, but in the case of XST (Or perhaps all synthesis tools.), it refuses to do the automatic duplication of a FF when an I/O pad is not inserted. That's a big problem when developing an I/O padless IP core. The only way I found to get around this problem was to edit the EDIF netlist generated by XST with a text editor. I will love to have synthesis tools do an automatic FF duplication even when an I/O pad isn't there, but I doubt it will be supported. Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) Anthony Ellis wrote: > > Accept that. So how does one generate a global reset from an internal > signal. > > "Ray Andraka" <ray@andraka.com> wrote in message > news:3D32B59E.AC71B00C@andraka.com... > > Because the BUFGP is a clock buffer, not intended for other signals. > >Article: 45208
What about uCLinux and Microblaze? If somebody has tried ... please let me know a feedback? Laurent Gauch www.amontec.comArticle: 45209
Hi all, anybody knows a source for a configuration software for the HP16500B / HP16510 logic analyzer, which displays JTAG State Information and JTAG State Mnemonics? Thanks a lot in advance AlexanderArticle: 45210
vikinger@uni.de wrote: > Hello at all, > > i need 4 Xilinx XCV300-6PQ240C or XCV300-6BG352C. > Heer in germany say me a person in a regional dealer it cost 328,00 EUR (~ $300)! For ONE! > I think its to many. > Who kann me say that is the real price for a this FPGA and where can i buy it. > > Bye > Erik. > > The price is quite normal. You can, for instance, make a search at www.avnet.com (products&services/electronic components/purchasing sevices). The "old" Virtex is a little bit outdated, so if you need exactly that chip you have to pay that price. Try a XCV300E and you'll come to 50...60% of the $300 you mentioned. If you want it even cheaper, see if you can fit your design into one or two SpartanII/SpartanIIE. JensArticle: 45211
Uwe Bonnes wrote: > Troy Schultz <tschultz@canada.com> wrote: > : Arrigo Benedetti wrote: > :> Does the most recent version of the Webpack run well under Linux/Wine? > :> I am interested in the command tools only. > :> > :> Thanks, > :> > :> -Arrigo > > : It works very well under VMware 3.1 running Win98 as a guest OS, I have > : not tried Wine. Since it works so well under VMware I did not see the > : sense in even trying Wine. > > : I have had no problems whatsoever and am also able to use the Xilinx > : Parallel Cable IV to program my parts. > > Did you ever start the chipviewer? For me it only crunched CPU cycles. > > Bye I have tried the chipviewer and it does work, a bit choppy but quite workable. I haven't installed it in a pure windows machine so I am not sure if this is the way it should be. The one thing I have done on my notebook, where I am also running the ACPI patches, is to hack the CPU idle handler and dissable it. There are some conflicts since the idle hanlder does not always properly see when the guest OS is using the CPU. This does not happen with all guest OSs but Win98 has a very poor CPU idle handler to begin with. - TroyArticle: 45212
"Pawe=B3 J. Rajda" wrote: > Hi, > > Is it possible to use Spartan XL PROM (XC17S50XL) > instead of Spartan 2 PROM (XC17S30A)? > My programmer does not support the former... No, you must use XC17S00A devices for Spartan-II. You can't use XL PROMs for Spartan-II. Look at thread: "XC17S00A programmable as XC17S00 for 2 XC2Ss?" of this newsgroup news:comp.arch.fpga in http://groups.google.com > -- > Regards, > Pawel J. Rajda UtkuArticle: 45213
Hello, In my design, there is a FPGA to perform a large number of DSP functions. A CPU will finally read the results from the FPGA. The problem is that FPGA's output will be a frame of data with the size of 1024Kbytes. Now as the clock of the CPU and FPGA are totally independent, in the previous version of the design I used an Altera device and used a block of RAM, with synchronous write (as the FPGA only needs to write the data) and asynchronous read (as CPU only reads the data). The problem is this approach is not portable to Xilinx devices as they do not feature asynchronous RAM (as far as I know...) So what's your suggestion to make this architecture portable? What should I use instead of that block of RAM with sync. write and async. read? (as the size of the RAM is not small, it's not wise to waste lots of CLBs in a Xilinx device to emulate it....) Regards ArashArticle: 45214
oooops! in my original post I mistakenly wrote a "1024Kbytes RAM" which is certainly a 1024bytes RAM.... Regards ArashArticle: 45215
"jetmarc" <jetmarc@hotmail.com> wrote in message news:af3f5bb5.0207151541.3188ca0a@posting.google.com... > Hi. > > Is anyone aware of 3rd party place & route tools for Atmels AT40K and FPSLIC > series? I know that their own "Figaro IDS" is available on the web site. I'm > looking for alternatives. > I'm in doubt that you'd succeed to find such a tool. Generally as the exact configuration of the LUTs and switch boxes inside a FPGA device is kept secret; there is no 3rd party place and route tool for any FPGA family. So basically you're bound to use the vendors tool for this stage of the design.... Regards ArashArticle: 45216
hows about a dual port ram? fpga writes with one clock, in one side. computer reads, with its clock, out of the other side. you might have to do some fiddling to prevent conflicts, but it sounds like its definitely worth a go. you can probably use one of the primitives, so that block ram is used (depending on the device) and in that case you'll make good use of area. "Arash Salarian" <arash.salarian@epfl.ch> wrote in message news:3d343639$1@epflnews.epfl.ch... > oooops! > > in my original post I mistakenly wrote a "1024Kbytes RAM" which is certainly > a 1024bytes RAM.... > > Regards > Arash > >Article: 45217
Arash Salarian wrote: > "jetmarc" <jetmarc@hotmail.com> wrote in message > news:af3f5bb5.0207151541.3188ca0a@posting.google.com... > >>Hi. >> >>Is anyone aware of 3rd party place & route tools for Atmels AT40K and >> > FPSLIC > >>series? I know that their own "Figaro IDS" is available on the web site. >> > I'm > >>looking for alternatives. >> >> > > I'm in doubt that you'd succeed to find such a tool. Generally as the exact > configuration of the LUTs and switch boxes inside a FPGA device is kept > secret; there is no 3rd party place and route tool for any FPGA family. So This isn't actually true. Amplify (a physical synthesis tool) contains a placer for Virtex devices. > basically you're bound to use the vendors tool for this stage of the > design.. > > Regards > Arash > > >Article: 45218
Arash, your problem is easily solved. The Xilinx BlockRAMs in Spartan-II, and the various Virtex families are dual-ported. So you simply dedicate one port to the writing, and the other port to the reading. Your microprocessor surely issues some kind of address strobe or read enable signal. Use that as the read clock for the XILINX BlockRAM's read port. If you have no access to such a strobe signal, you have to fabricate it yourself by identity-comparing the incoming address against the registered previous address. Should take 2 or 3 CLBs and a free-running clock, worst case. Peter Alfke, Xilinx Applications Arash Salarian wrote: > Hello, > > In my design, there is a FPGA to perform a large number of DSP functions. A > CPU will finally read the results from the FPGA. The problem is that FPGA's > output will be a frame of data with the size of 1024Kbytes. Now as the clock > of the CPU and FPGA are totally independent, in the previous version of the > design I used an Altera device and used a block of RAM, with synchronous > write (as the FPGA only needs to write the data) and asynchronous read (as > CPU only reads the data). > The problem is this approach is not portable to Xilinx devices as they do > not feature asynchronous RAM (as far as I know...) > So what's your suggestion to make this architecture portable? What should I > use instead of that block of RAM with sync. write and async. read? > (as the size of the RAM is not small, it's not wise to waste lots of CLBs in > a Xilinx device to emulate it....) > > Regards > ArashArticle: 45219
If its a limited quantity kind of project, and your time is cheaper than the parts, you can get some great deals on E-bay. For example, right now there are 18 XCV300E going at $46 (10am PST 7/16/02). Regards <vikinger@uni.de> wrote in message news:<ah0gth$bu7$01$1@news.t-online.com>... > Hello at all, > > i need 4 Xilinx XCV300-6PQ240C or XCV300-6BG352C. > Heer in germany say me a person in a regional dealer it cost 328,00 EUR (~ $300)! For ONE! > I think its to many. > Who kann me say that is the real price for a this FPGA and where can i buy it. > > Bye > Erik.Article: 45220
Hello Jens, > The price is quite normal. Real? I can become from Insight a complett SpartanII-Development-Kit for this Price but i can't use it. > You can, for instance, make a search at www.avnet.com ... $497 !! > The "old" Virtex is a little bit outdated, ... That do you mean? The original Virtex is the fastest Chip that will do 5V-PCI. I need it for a speazial interface-card with a high bandwitch for communication. For the bandwitch, that i need, i must overclock the PCI-bus and a SpartanII is not fast enough for 50MHz-PCI. I have a mainboard with a configuration-option for clock-ratio betwen frontside-bus and pci-bus. The Virtex will do 66MHz-PCI and is the best solution for my problem (better clock-DLL, faster slices and faster io-buffers). Its an privat project and then i buy a SpartanII-PCI-Kit and at the middle of the work i see the Spartan is not fast enough i have lost my money. In my opinion is the better way i have at the end a working project with a littel bit reserve. ErikArticle: 45221
This is a multi-part message in MIME format. --------------1A02AF101031688C9A97F9EF Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit It sounds like your programmer supports only XC17S00XL PROMs so you are asking if you can program an XC17S00XL PROM on your programmer to configure your Spartan-II FPGA. (I assume your FPGA target is a Spartan-II FPGA.) You can use a Spartan-XL PROM to configure a Spartan-II FPGA. The downside is just that the XC17S00XL PROMs cost more than the XC17S00A PROMs. You just need to make sure the capacity of the XC17S00XL PROM can fit the Spartan-II FPGA bitstream. Randal "Paweł J. Rajda" wrote: > Hi, > > Is it possible to use Spartan XL PROM (XC17S50XL) > instead of Spartan 2 PROM (XC17S30A)? > My programmer does not support the former... > > -- > Regards, > Pawel J. RajdaArticle: 45222
I'm designing an system which requires a 622Mbps LVDS interface (4 differential pairs). The signal has to pass between two boards a few inches apart. Space on the boards isn't an issue (it's a prototype). We would like to use any widely-available connector format. The LVDS signal is output from the TI SLK2501, i.e. not a line driver device. Currently I'm planning on using 16-way twisted pair ribbon cable, on a narrow-pitch header, with a hefty sprinkling of grounds, and termination as per the data sheet. What would the group recommend?Article: 45223
In comp.arch.fpga Pootle <Pootle(AT)mooses(DOT)co(DOT)uk> wrote: : I'm designing an system which requires a 622Mbps LVDS interface (4 : differential pairs). The signal has to pass between two boards a few inches : apart. Space on the boards isn't an issue (it's a prototype). We would : like to use any widely-available connector format. : The LVDS signal is output from the TI SLK2501, i.e. not a line driver : device. : Currently I'm planning on using 16-way twisted pair ribbon cable, on a : narrow-pitch header, with a hefty sprinkling of grounds, and termination as : per the data sheet. What about a CAT5 or better Cat6/7 twisted pair cable? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 45224
Erik wrote:
>
> Hello Jens,
>
> Real? I can become from Insight a complett SpartanII-Development-Kit for this Price but i can't use it.
>
Are you using Insight Electronics Spartan-II PCI Development Kit
to do 66MHz PCI?
Whether it is the older PCI kit (The one that uses XC2S150-5CPQ208) or
the newer PCI kit (The one that uses XC2S200-5CFG456), I doubt you will
meet 66MHz PCI's timings assuming that you want to do zero wait state
transfer, considering that they use the slower -5 part, not the faster
-6 part.
Plus, both cards don't have the M66EN pin needed for a motherboard to
detect the presence of a 66MHz PCI card.
> > You can, for instance, make a search at www.avnet.com ...
> $497 !!
>
> > The "old" Virtex is a little bit outdated, ...
> That do you mean?
>
> The original Virtex is the fastest Chip that will do 5V-PCI.
> I need it for a speazial interface-card with a high bandwitch for communication.
> For the bandwitch, that i need, i must overclock the PCI-bus and a SpartanII is not fast enough for 50MHz-PCI.
> I have a mainboard with a configuration-option for clock-ratio betwen frontside-bus and pci-bus.
> The Virtex will do 66MHz-PCI and is the best solution for my problem
> (better clock-DLL, faster slices and faster io-buffers).
>
First of all, to do a universal PCI card (A PCI card that
supports both 3.3V and 5V PCI.), you need to have a chip that detects
+VIO pin voltage and two bitstream images.
Secondly, although no official timing specification for 50MHz PCI
exists, according to PCI Specification 2.2 Page 236, unofficially the
Tsu and Tval remain same as 66MHz PCI (3ns and 6ns respectively.), which
means that the difficulty meeting timings is as bad as 66MHz PCI.
Thirdly, I am not sure if you are using LogiCORE PCI, licensed a PCI IP
core from a third-party IP core developer, or did your own PCI IP core,
but unless you licensed LogiCORE PCI, I will say the chance of meeting
66MHz PCI timings is pretty slim even if you used Virtex-6 or
Spartan-II-6.
The thing is that, Xilinx has an upper hand compared to a third-party
developer when it comes to 66MHz PCI because they know how to use two
crucial undocumented (secret) features of Virtex silicon (PCILOGIC and
BITGEN's /Gclkdel option.).
Someone before me has figured out how to instantiate PCILOGIC from
user's design (i.e., By instantiating a blackbox of PCILOGIC in HDL
code.), so based on that information, I attached PCILOGIC to my PCI IP
core, and PCILOGIC worked fine with my PCI IP core, but /Gclkdel is much
harder to use considering that Static Timing Analyzer is not aware of
BITGEN's /Gclkdel option.
Still, one Xilinx employee posted a way to figure out how /Gclkdel
option works by measuring the delay with an oscilloscope, but it doesn't
help me because I don't have an oscilloscope.
> Its an privat project and then i buy a SpartanII-PCI-Kit and at the middle of the work
> i see the Spartan is not fast enough i have lost my money.
> In my opinion is the better way i have at the end a working project with a littel bit reserve.
>
> Erik
Is Spartan-II-6 that slower than Virtex-6?
Comparing a 4-input LUT delay, it's about the same (about 0.6ns),
although I have never targeted Virtex-6 (Because ISE WebPACK doesn't
support Virtex.), so I am not sure how Virtex-6 fares.
Although it cannot not do 66MHz PCI, Insight Electronics Spartan-II PCI
Development Kit is a fine 33MHz PCI card, so if you can put it up on an
auction site, I am sure someone will buy it.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
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