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Which resources do you use on PLX : -only slave?, DMA?, master?, burst ... If you're using only the slave part of PLX, we have a solution for you! Contact us Bonne fin de journée Laurent Gauch www.amontec.com BROTO Laurent wrote: > Today, we've a Spartan with a PLX. We would like to introduce Logicore in > Spartan to replace PLX but IO aren't the same (excuse me for my english... > I'm french). > Do you know an interface to use my old VHDL program (with PLX IO) with a > logicore without modification ? > > Thanks a lot, > > BROTO Laurent > > >Article: 45101
Paul, In Virtex II, there is a battery backed up key memory for keys for triple DES decryption of the bitstream. Austin Paul wrote: > Hi All, > Are there any security features in FPGA's that I can use to protect > software? > > regards > PaulArticle: 45102
Mike, Keys are programmed in thru the JTAG port. Once programmed with keys and placed in the 'secure' more, you can no longer do a readback of the memory (obvious), and you can not use the internal reconfiguration access port, etc. The softare tools supports creation of the key files, the downloading, and the choice of encryption for the bitstream (starting position of the first key - 1, 2 or 3 of 6 keys) and key generation. All of the back doors are closed. If the battery backed up ram for the keys are lost (Vbatt drops below ~ 0.4 V), then the part will revert to the non-secure mode, and can not be programmed with the bitstream until the keys are re-programmed. Key memory requires only pA (they are only 6 sets of 56 bit registers). One 150 mAHr lithium coin cell would last 10 to 15 years. While in operation, the key memory runs off the internal supplies. Austin Mike Rosing wrote: > Paul wrote: > > Hi All, > > Are there any security features in FPGA's that I can use to protect > > software? > > Yes, check out Virtex-2. It uses triple DES keys so the rom data is > encrypted when you get the product into the field. You need to talk > to the Xilinx guys to find out how to get the keys into your chips tho. > > Patience, persistence, truth, > Dr. mike > > -- > Mike Rosing > www.beastrider.com BeastRider, LLC > SHARC debug toolsArticle: 45103
Use a "buffer" to change signal names (the buffer will be optimized out). I would use Vcc and Gnd and then 20 buffers to make a 20 bit bus that is a constant. Dan "Bob W" <fa@_NO_SPAM_AskTheOracle.com> wrote in message news:1motiugi2ulbfbmpjikig77d0jqkvmr47t@4ax.com... > > II need to enter a 20 bit constant as a value to load into counter > designed using the Schematic entry tool. How do I do that? I could > probably use Vcc and Gnd macros but I am hoping there is a cleaner > solution. > > In StateCad there is a constant function, in Altera there is an > LP_CONST macro. How do I do this in Xilinx? > > Also, I would like to create a block that swaps the order if the bits > in a byte from 7..0 to 0...7. In Altera MaxPlus I could create a block > with the input from Datain7 connected to Data 0 through a Soft Cell > that allows me to connect 2 wires without creating any logic. How do I > do this in Xilinx? > > BobArticle: 45104
Hi, A good start point for CPU on a FPGA is www.fpgacpu.org Since I design the MicroBlaze it's very possible to do high performance 3= 2-bit RISC in fpga. (150 MHz in VIIPro) The distributed RAM in xilinx FPGA make it easy to do a register file. G=F6ran res19j1c wrote: > Hi, > I'm new to FPGAs. I just have a few questions. I'm sure some of these h= ave > been asked already but I've been using the google archive to search old= > posts and couldn't find anything. > > 1.) Is it correct that I could design a CPU on a FPGA? > > 2.) It seems that the ability to create a certain design is measured in= > gates. So the more complex the design, the more gates it needs. Is this= > true, or at least partly true? > > 3.) If so, how many gates would it take to implement a CPU with > functionality about equivalent to an Intel IA-32 style chip (80386 - 80= 686). > > 4.) About how many MHz would this run at on a newer FPGA such as the > Virtex-II?Article: 45105
On Fri, 12 Jul 2002 01:37:45 -0400, "Rob Finch" <robfinch@sympatico.ca> wrote: >> 3.) If so, how many gates would it take to implement a CPU with >> functionality about equivalent to an Intel IA-32 style chip (80386 - >80686). > >It depends what you mean by equivalent functionality. The 80383+.. is an >incredibly complex chip. Implementing all the features of this type of chip >would require an enormous number of gates (eg hundreds of thousands). >Try >looking at the transistor count for the chip then dividing by the gate to >transistor ratio. This would be misleading. A very large number of transistors on any modern cpu are in the internal cache blocks and their shouldn't be counted during logic size calculations. Also the performance one designs for is a very big factor. A large part of the area in these processors are used to wring the last drop of performance out of x86 ISA. If one is just trying to duplicate functionality of an x86 without trying to get it to run at 2GHz and 6IPC, the size can be much smaller; obviously. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 45106
In article <3D2EF70C.A9DFC27@xilinx.com>, Goran Bilski <goran.bilski@xilinx.com> wrote: >Hi, > >A good start point for CPU on a FPGA is www.fpgacpu.org > >Since I design the MicroBlaze it's very possible to do high performance 3= >2-bit >RISC in fpga. (150 MHz in VIIPro) >The distributed RAM in xilinx FPGA make it easy to do a register file. And if you are willing to go with a 2 thread approach, you can take advantage of finer pipelining to get it even faster. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 45107
On Mon, 08 Jul 2002 13:18:52 +0100, Rick Filipkiewicz <rick@algor.co.uk> wrote: > > >Anton Erasmus wrote: > >> On Tue, 2 Jul 2002 16:47:13 +0200, "Falk Brunner" >> <Falk.Brunner@gmx.de> wrote: >> >> >"Thomas" <ThoLei@gmx.net> schrieb im Newsbeitrag >> >news:ee77a68.-1@WebX.sUN8CHnE... >> >> Dear Community! >> >> >> >> In my application I need to let the FPGA communicate with the PC. (I want >> >to write a small C++ program where you can enter some values) >> >> The demo board I use offers an serial RS-232 port but only with TXin and >> >RXout pins. So I suppose I must use some software handshake? >> >> And i have to implement a serial/parallel converter within the FPGA (vhdl >> >code?). >> > >> >A complete RS232 UART inluding 16 byte FIFO in both directions is ready to >> >use available for Spartan-II devices. Have a look at the xapps from Xilinx >> >(AFAIK 223 or so). For other families, you may try the UART from >> > >> >www.opencores.org >> > >> >If you need a intelligent salve inside the FPGA, I recommend having a look >> >at xapp213, which delivers a 8 bit RISC processor, ready to use. >> > >> >-- >> >MfG >> >Falk >> >> Hi, >> >> Implementing a simple SPI or JTAG type synchronous interface should >> take a lot less space in the FPGA, and you could simply bit-bang on >> the PC side via either the parallel port or serial port. >> >> Regards >> Anton Erasmus > >I'd say the MicroWire protocol (4 pin, used by the serial EEPROMs that hold >config info for e.g. Ethernet controllers. 93LC46 is an example) is probably >simpler than both. None of that tedious ACK/NACK stuff needed by SPI nor the >fairly complicated SM needed by JTAG. What ACK/NACK stuff with SPI ? AFAIK SPI is basically a shift register with MOSI connected to the input, MISO to the output, a clock line SCK and a chip select line that enables the MISO and SCK lines. You might be thinking of I2C ? Regards AntonArticle: 45108
"Goran Bilski" <goran.bilski@xilinx.com> schrieb im Newsbeitrag news:3D2EF70C.A9DFC27@xilinx.com... Hi, > A good start point for CPU on a FPGA is www.fpgacpu.org > Since I design the MicroBlaze it's very possible to do high performance 32-bit > RISC in fpga. (150 MHz in VIIPro) > The distributed RAM in xilinx FPGA make it easy to do a register file. Hello, the CPU hardware design is one part, but what is about the software like assembler,(C-)compiler and debugger? Who knows which commonly used processors like 8051 or even 16bit processors can be implemented in FPGA without copyright infringement? Best Regards HelmutArticle: 45109
In article <agn811$to8$01$1@news.t-online.com>, Helmut Sennewald <HelmutSennewald@t-online.de> wrote: >Hello, >the CPU hardware design is one part, but what is about the software >like assembler,(C-)compiler and debugger? > >Who knows which commonly used processors like 8051 or even 16bit >processors can be implemented in FPGA without copyright infringement? You do better with 32 bit, for a few reasons: First, they aren't more complicated and that much more area overall, since a processor datapath is relatively small. With the current "cheap" FPGAs so big, you can do ALOT more with a Spartan IIE when compared to the old 4003 days, so you might as well go with the larger datapath and get a more supported architecture. Second, MIPS and SPARC have plenty of freely available documentation and no patent encumberences that I know of for making implementations. ARM tends to get a bit, emm, feisty about free or unliscenced implementations (I think they have some ISA related patents). If you brew your own, an assembler is straightforward and LCC is a great (and limitedly free) resource for giving you a C compiler. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 45110
Hello, We're trying to use a Xilinx FPGA to map signals from a system bus to a PCMCIA socket. We're using Axis Communications' Etrax100LX, which has both serial ports and parallel ports. http://www.developer.axis.com We're trying to take the signals from the system bus and add some external logic and the FPGA to create appropriate signals for PCMCIA. Has anyone done this before with the Axis Etrax 100LX??? What about making PCMCIA signals from parallel port signals?? Thanks, Randy HolmanArticle: 45111
Hi, maybe it is a old story. I need to connect Actel proAsic FPGA and other 5V chip. After check datasheet, I found there is no way to connect them directly. Could I just use any IC to make them compatible? Thank advance, FrankArticle: 45112
There are three separate issues: 1. Can the 3.3-V part drive a reliable High level into the 5-V part. ( Is Voh high enough?) 2. Can the 3.3-V part receive a High level (from the 5-V part) without any damage? 3. What happens when the two supply voltages go active at different times? Peter Alfke, Xilinx Applications ======================================= Frank Zhifeng Yuan wrote: > Hi, maybe it is a old story. > I need to connect Actel proAsic FPGA and other 5V chip. After check > datasheet, I found there is no way to connect them directly. Could I just > use any IC to make them compatible? > Thank advance, > > FrankArticle: 45113
Hi! I'm going to build a DSO with 80 MSPS using a Xilinx FPGA (don't know which one yet, a small one with <= 200-300 Gates). Therefore I need a very accurate 80 MHz clock with low jitter and exact 50/50 duty cycle. When I feed the FPGA with an accurate 80 MHz clock and use the DLL to get 50/50 duty cycle, will the DLL introduce additional jitter/noise/inaccuracies? When I feed the FPGA with an accurate 40 MHz clock and use the DLL to double the frequency (and yielding 50/50 duty cycle), will that intruduce jitter/noise/inaccuracies? Is it better to generate an accurate clock outside without using any FPGA tools like the DLL and distributing it to the ADCs, the RAM and the FPGA? Thanks HansiArticle: 45114
Anton Erasmus wrote: > > Anton Erasmus > > > >I'd say the MicroWire protocol (4 pin, used by the serial EEPROMs that hold > >config info for e.g. Ethernet controllers. 93LC46 is an example) is probably > >simpler than both. None of that tedious ACK/NACK stuff needed by SPI nor the > >fairly complicated SM needed by JTAG. > > What ACK/NACK stuff with SPI ? AFAIK SPI is basically a shift register > with MOSI connected to the input, MISO to the output, a clock line SCK > and a chip select line that enables the MISO and SCK lines. > > You might be thinking of I2C ? > > Regards > Anton Ah. Sorry I was equating SPI with I2C. It looks like, really, SPI = what I call MicroWire.Article: 45115
Nicholas Weaver wrote: > In article <agn811$to8$01$1@news.t-online.com>, > Helmut Sennewald <HelmutSennewald@t-online.de> wrote: > >Hello, > >the CPU hardware design is one part, but what is about the software > >like assembler,(C-)compiler and debugger? > > > >Who knows which commonly used processors like 8051 or even 16bit > >processors can be implemented in FPGA without copyright infringement? > > You do better with 32 bit, for a few reasons: First, they aren't more > complicated and that much more area overall, since a processor > datapath is relatively small. With the current "cheap" FPGAs so big, > you can do ALOT more with a Spartan IIE when compared to the old 4003 > days, so you might as well go with the larger datapath and get a more > supported architecture. > > Second, MIPS and SPARC have plenty of freely available documentation > and no patent encumberences that I know of for making > implementations. > Be careful. The MIPS unaligned load/store instructions lwl/lwr swl/swr and their 64 bit analogues *are* patented ... and most MIPS ISA compilers do generate them for unaligned 32/64 bit accesses.Article: 45116
Hansi, you have to be more specific: What do you mean by 50% duty cycle? How much error can you tolerate? How much jitter can you tolerate? Whatever you do, the signal will never be perfect. Just feeding a signal through any type of buffer introduces duty-cycle distortion and jitter. Can you tolerate 10 picosecods, 50 picoseconds, or 100 picoseconds, or more ? Your clock period is 12 500 picoseconds. Give us an error budget... Peter Alfke, Xilinx Applications Johann Glaser wrote: > Hi! > > I'm going to build a DSO with 80 MSPS using a Xilinx FPGA (don't know > which one yet, a small one with <= 200-300 Gates). Therefore I need a very > accurate 80 MHz clock with low jitter and exact 50/50 duty cycle. > > When I feed the FPGA with an accurate 80 MHz clock and use the DLL to get > 50/50 duty cycle, will the DLL introduce additional > jitter/noise/inaccuracies? > > When I feed the FPGA with an accurate 40 MHz clock and use the DLL to > double the frequency (and yielding 50/50 duty cycle), will that intruduce > jitter/noise/inaccuracies? > > Is it better to generate an accurate clock outside without using any FPGA > tools like the DLL and distributing it to the ADCs, the RAM and the FPGA? > > Thanks > HansiArticle: 45117
Hi, The questions is not only if it's a copyright infringement but also if yo= u can stand a law suite. Some company which think they have a copyright on a ISA and may sue you e= ven if you are right. Many small company and single person don't have to money and time to hand= le that. So most of the existing processor today will have some suing hanging over= them. Specially if your copy is starting to make some money. If you only doing for your own hobby stuff or for research no one will su= e you. I know that ARM allows universities to do research on ARM clones for inte= rnal use only. The only commercial 32-RISC ISA which I know is free is the SPARC, I think that the LEON implementation is free to use. For the compiler part, the best way is to port the GNU tools. It takes time and resources to do the port but will produce a decent tool= set. The quickest way is to use LCC but it has some fee if you want to use it commercial and it doesn't produce high quality code like gcc. It is very fast to port to= a new target using LCC. G=F6ran Helmut Sennewald wrote: > "Goran Bilski" <goran.bilski@xilinx.com> schrieb im Newsbeitrag > news:3D2EF70C.A9DFC27@xilinx.com... > Hi, > > > A good start point for CPU on a FPGA is www.fpgacpu.org > > > Since I design the MicroBlaze it's very possible to do high performan= ce > 32-bit > > RISC in fpga. (150 MHz in VIIPro) > > The distributed RAM in xilinx FPGA make it easy to do a register file= =2E > > Hello, > the CPU hardware design is one part, but what is about the software > like assembler,(C-)compiler and debugger? > > Who knows which commonly used processors like 8051 or even 16bit > processors can be implemented in FPGA without copyright infringement? > > Best Regards > HelmutArticle: 45118
Depends on how much jitter is acceptable in your application. JItter at the
ADC clock translates to noise in your system. A DLL adds some jitter to your
clock, so it is usually not appropriate to use a clock that has gone through a
DLL to clock an ADC when you are sampling IF or RF signals. We try to use an
externally generated clock for clocking both the ADC and the FPGA. The RAM is
not nearly as critical, and can be clocked through the DLL (for that matter,
you can use the DLLs to generate a different clock for the RAM so that you can
run the RAM close to it's maximum clock rate in order to maximize the
bandwidth.
Johann Glaser wrote:
> Hi!
>
> I'm going to build a DSO with 80 MSPS using a Xilinx FPGA (don't know
> which one yet, a small one with <= 200-300 Gates). Therefore I need a very
> accurate 80 MHz clock with low jitter and exact 50/50 duty cycle.
>
> When I feed the FPGA with an accurate 80 MHz clock and use the DLL to get
> 50/50 duty cycle, will the DLL introduce additional
> jitter/noise/inaccuracies?
>
> When I feed the FPGA with an accurate 40 MHz clock and use the DLL to
> double the frequency (and yielding 50/50 duty cycle), will that intruduce
> jitter/noise/inaccuracies?
>
> Is it better to generate an accurate clock outside without using any FPGA
> tools like the DLL and distributing it to the ADCs, the RAM and the FPGA?
>
> Thanks
> Hansi
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45119Does Xilinx's Foundation 2.1i support the VertexII? (I only see Vertex & VertexE as options. I think I have the latest service packs). Am I just out of luck? Thanks. Mark.Article: 45120
Does the most recent version of the Webpack run well under Linux/Wine? I am interested in the command tools only. Thanks, -ArrigoArticle: 45121
Hi, I want to use the clock signal from an oscillator that is also feeding an Intel 8051. The problem is that the oscillator output is 5V. I read somewhere that standard inputs on Spartan2s can take 5V in, but it never mentioned anything about the CLOCK inputs. Can someone answer this? I'm at a critical point in the design phase and I need the answer soon. Thank you. LTArticle: 45122
When we say that inputs are 5-V tolerant, we mean that ALL inputs are 5-V tolerant. So you have no problem. Peter Alfke, Xilinx Applications ====================== Loi Tran wrote: > Hi, > > I want to use the clock signal from an oscillator that is also feeding an > Intel 8051. The problem is that the oscillator output is 5V. I read > somewhere that standard inputs on Spartan2s can take 5V in, but it never > mentioned anything about the CLOCK inputs. Can someone answer this? I'm at a > critical point in the design phase and I need the answer soon. > > Thank you. > > LTArticle: 45123
When we say that inputs are 5-V tolerant, we mean that ALL inputs are 5-V tolerant. So you have no problem. But next time give us a usable return address if you expect an answer. I have better things to do than editing your address! :-( Peter Alfke, Xilinx Applications ====================== Loi Tran wrote: > Hi, > > I want to use the clock signal from an oscillator that is also feeding an > Intel 8051. The problem is that the oscillator output is 5V. I read > somewhere that standard inputs on Spartan2s can take 5V in, but it never > mentioned anything about the CLOCK inputs. Can someone answer this? I'm at a > critical point in the design phase and I need the answer soon. > > Thank you. > > LTArticle: 45124
In article <3D2F86E6.7E8CDD56@xilinx.com>, Peter Alfke <peter@xilinx.com> wrote: >But next time give us a usable return address if you expect an answer. >I have better things to do than editing your address! :-( I'll keep that in mind next time, but just to let you know. I watch the newsgroup after I post a question. You don't need to send me an e-mail. > >Peter Alfke, Xilinx Applications >====================== Thanks again. LT
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Compare FPGA features and resources
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