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I have been using FPGA express with the Xilinx foundation software. I
found it to be a good tool. Unfortunately, Xilinx will no longer be
supplying FPGA express with its other software. Does anyone know if there
the Xilinx synthesis tool (XST) is comparable in performance to FPGA
Express? Is there an article comparing the performance of the major
synthesis tools for Xilinx (FPGA Express, Exemplar, Synplicity, XST, etc)?
The majority of the people I have spoken with seem to prefer Synplicity, but
the majority of them have very limited or no exposure to the other tools.
Thank you in advance,
Shawn Hineline
--
*******************************
Shawn Hineline
Optimum Engineering, Inc.
Article: 38776
Leo and Synplicity are more capable (and more expensive) tools. I personally
prefer Synplicity. I have used both FPGA express and XST some. XST has come a
long way since it was first introduced. It is comparable to, and in some
respects better than, the FPGA Express that had been packaged with foundation.
XST does handle inference of Xilinx structures better than FPGA express, but
don't try to use it with another vendor's stuff. My recommendation? If you
liked FPGA express, you will like XST and will probably be quite pleased with
its performance. If you've been used to Synplicity, then you may be frustrated
at times with XST.
Shawn wrote:
> I have been using FPGA express with the Xilinx foundation software. I
> found it to be a good tool. Unfortunately, Xilinx will no longer be
> supplying FPGA express with its other software. Does anyone know if there
> the Xilinx synthesis tool (XST) is comparable in performance to FPGA
> Express? Is there an article comparing the performance of the major
> synthesis tools for Xilinx (FPGA Express, Exemplar, Synplicity, XST, etc)?
> The majority of the people I have spoken with seem to prefer Synplicity, but
> the majority of them have very limited or no exposure to the other tools.
>
> Thank you in advance,
> Shawn Hineline
>
> --
> *******************************
> Shawn Hineline
> Optimum Engineering, Inc.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 38777See below: Alex Carreira wrote: > I am pretty sure the solution is to try this with a Virtex instead, but > first read XAPP 151 and all the others on the configuration architecture. > It may be possible on 4000 series No, XC4000 does not offer partial reconfiguration. > but I don't think so (I am guessing that > reconfiguration causes functionality to stop during reprogramming of the > configuration memory, yes > which is not the case for all scenarios with the > Virtex--of course I could be dead wrong about the 4000 series and if so > please excuse me). You are right on. Let me point out, however, that even good old XC3000, XC4000 and Spartan devices can initiate their own (complete) reconfiguration ( by pulling PROG Low) This may seem to violate some timing specs, but it works "by design". 100% ! > > > You can find out if it will work the the 4000 series for sure by digging up > an in depth ap. note on its configuration architecture (if one exists--I > think it does but my memory on the subject is weak right now). > > I have had discussions with numerous people about reconfiguring a Virtex > FPGA with its own resources. It would be particularly slick in RTR > (run-time-reconfigurable) applications. Reconfiguration can be initiated ( triggered) by any Xilinx device, partial reconfiguration only by Virtex (Spartan-II) devices. Peter Alfke, Xilinx ApplicationsArticle: 38778
Hello, The Spartan-II, Spartan-IIE, Virtex, and Virtex-E devices all have the same special resources for PCI. These resources are, however, intended primarily for use with the Xilinx PCI LogiCORE product -- particularly for 66 MHz designs. If you are building a PCI implementation, and elect to do it yourself (i.e. not buy a Xilinx PCI LogiCORE product) you should be able to get a 33 MHz design working if you are careful in your logic design. There are some previous posts on this newsgroup about another person's adventures with a PCI implementation. Good luck, Eric "Deli Geng (David)" wrote: > Hi, there, > > I'm new to Spartan-II FPGA chip. However, I need to use it in a PCI design. > So I was wondering if some pins are dedicated for PCI or any pin can be used > for PCI connection? BTW, can you also provide some advice on how to use > Spartan FPGA as PCI controller? > > Thanks a lot. > > Regards, > DavidArticle: 38779
Ray Andraka wrote: > > Yes, I had a frequency counter years ago that had bars with numbered windows. > Behind each was a neon bulb which would light up the correct digit. An > additional neon bulb lit up behind the range (Hz, kHz), and there was one > between each column to act as a decimal point. The display for a 59.703 Hz > input would look something like this: > > 9 > Hz > 7 > > 5 > > 3 > > > * 0 > Would that model 521? There's one in the next office. --aArticle: 38780
Yury wrote: > Implemented 1/2 Band 51-tap FIR using Coregen + Foundation. > Pre-synthesis simulation looks excellent, however when the filter is > loaded into Spartan-II the output looks like complete random junk. All > timing is met. You might want to look at the model and verify if it's correct. Watch out for timing information in the model (e.g., a <= b after 1 ns; etc) -- you may find that your state machines are off by one state, and it's the model's fault. --aArticle: 38781
I can't even remember who made it, much less the model number. It was about 19"
wide, maybe 10" tall. The front panel was light grey with a dark grey cabinet
whose top and bottom covers met half way down the sides (so there were no exposed
side panels). The edges where the top and bottom met the sides were curved with
about a 3/4" radius. I think there were steel handles on the sides where the top
and bottom covers met. The displays were offset to the left side of the front
panel. I vaguely remember a single digit counter module in the rear panel too, but
I don't recall what it was for. I wish I could remember who made it.
Andy Peters wrote:
> Ray Andraka wrote:
>
> >
> > Yes, I had a frequency counter years ago that had bars with numbered windows.
> > Behind each was a neon bulb which would light up the correct digit. An
> > additional neon bulb lit up behind the range (Hz, kHz), and there was one
> > between each column to act as a decimal point. The display for a 59.703 Hz
> > input would look something like this:
> >
> > 9
> > Hz
> > 7
> >
> > 5
> >
> > 3
> >
> >
> > * 0
> >
>
> Would that model 521? There's one in the next office.
>
> --a
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 38782Ray Andraka wrote: > I can't even remember who made it, much less the model number. Wasn't it by Beckman Instruments? Peter AlfkeArticle: 38783
oh, no, i didnt in fact, i was using non speacial function user I/O at first. its not working.. i tried using HDC, it can't work either.. and i even tried LDC, this is our of sense ya, and its not working (as expected).. one thing, i am using VHDL to design my logic, and in the contraints editor, i set the initiate user I/O to pull up.. so, it should be pulled high once the configuration completed, shouldnt it? i did this for double security, as i already set it high in my VHDL code.. until reconfigure is necessary. any idea, anything wrongs that you find? thanks again. :) Ray Andraka <ray@andraka.com> wrote in message news:3C505D92.3A099E8A@andraka.com... > Sounds like you randomly selected LDC or one of the other dual use pins that > goes low during configuration. If you did that, then as soon as the chip starts > configuring, LDC goes low, pulling the program pin low, which restarts > reconfiguration. While program is low, the LDC goes high so it releases program > and the configuration starts until LDC goes low again. I kind of figured > something like that was going on. Since you only have two configurations, this > should work fine as long as you avoid pins that go low during configuration. It > may be best to use HDC to get a solid high level during configuration. > > Fong Chii Biao wrote: > > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 38784
Greetings , Peter so, do you have any idea about my problems in start-up configuration? i tried to reconfigure (completely) XC4010 by initiating it using one of the I/O (non special function), when i connect it directly to PROG, the start-up can't work.. its working once i disconnect it Peter Alfke <peter.alfke@xilinx.com> wrote in message news:3C509241.1AF3B12A@xilinx.com... > See below: > > Alex Carreira wrote: > > > I am pretty sure the solution is to try this with a Virtex instead, but > > first read XAPP 151 and all the others on the configuration architecture. > > It may be possible on 4000 series > > No, XC4000 does not offer partial reconfiguration. > > > but I don't think so (I am guessing that > > reconfiguration causes functionality to stop during reprogramming of the > > configuration memory, > > yes > > > which is not the case for all scenarios with the > > Virtex--of course I could be dead wrong about the 4000 series and if so > > please excuse me). > > You are right on. > Let me point out, however, that even good old XC3000, XC4000 and Spartan devices > can initiate their own (complete) reconfiguration ( by pulling PROG Low) This > may seem to violate some timing specs, but it works "by design". 100% ! > > > > > > > You can find out if it will work the the 4000 series for sure by digging up > > an in depth ap. note on its configuration architecture (if one exists--I > > think it does but my memory on the subject is weak right now). > > > > I have had discussions with numerous people about reconfiguring a Virtex > > FPGA with its own resources. It would be particularly slick in RTR > > (run-time-reconfigurable) applications. > > Reconfiguration can be initiated ( triggered) by any Xilinx device, > partial reconfiguration only by Virtex (Spartan-II) devices. > > Peter Alfke, Xilinx Applications > >Article: 38785
You said the program pin was toggling. Any more detail? ONe of two things are
happening: either it is getting pulled low as soon as configuration begins, or
it is getting pulled low at the end of configuration. Make sure the pin you
have it connected to isn't set up to output a low on power up (ie when global
reset is active).
Check the start-up sequence. The default,IIRC, lets go of the configuration use
for the pins one CCLK before turning on the pin drivers. The weak internal
pullup on the user I/O may not be enough to keep program from going low. You
might consider an external pullup on the /program pin.
Do yourself a favor, open that loop and watch the pin you are driving program
with. If it goes low at all, then you you just have to figure out when it goes
low which should then tell you why. If it stays high like that, put an external
pull-down to load the output and see what it does then.
Fong Chii Biao wrote:
> oh, no, i didnt
> in fact, i was using non speacial function user I/O at first. its not
> working..
> i tried using HDC, it can't work either..
> and i even tried LDC, this is our of sense ya, and its not working (as
> expected)..
>
> one thing, i am using VHDL to design my logic,
> and in the contraints editor, i set the initiate user I/O to pull up..
> so, it should be pulled high once the configuration completed, shouldnt it?
> i did this for double security, as i already set it high in my VHDL code..
> until reconfigure is necessary.
>
> any idea, anything wrongs that you find?
> thanks again. :)
>
> Ray Andraka <ray@andraka.com> wrote in message
> news:3C505D92.3A099E8A@andraka.com...
> > Sounds like you randomly selected LDC or one of the other dual use pins
> that
> > goes low during configuration. If you did that, then as soon as the chip
> starts
> > configuring, LDC goes low, pulling the program pin low, which restarts
> > reconfiguration. While program is low, the LDC goes high so it releases
> program
> > and the configuration starts until LDC goes low again. I kind of figured
> > something like that was going on. Since you only have two configurations,
> this
> > should work fine as long as you avoid pins that go low during
> configuration. It
> > may be best to use HDC to get a solid high level during configuration.
> >
> > Fong Chii Biao wrote:
> >
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 38786Hi, I am wondering what wrong with www.fpga.org website. Is it shutdowned or what? ThanksArticle: 38787
> I am wondering how to determine the sampling frequency from the timing > diagram that I obtained after simulation? The sampling freq has nothing to do with simulation... The simulation relies on you specifying an external freq. What you'll have on the board is a BOM issue... If you are not sampling exactly at the main clock Freq (but below it indeed), and if your processing works 1 data in -> 1 data out per clock cycle, then it is probably not optimal, but you can simply use a global "Enable" which will be your "sampling freq". This way, you can easily apply input data in a non-real time way. You know that sampling freq is a very important Data Processing issue ! Your whole system must be built around this value ! > And how do I enter the required > frequency into the FPGA ? Through external crystal clock or just using > internal FPGA Board clock (in Altera UP-1 Board ,it is 25.175MHz) ? Again, it's you who knows what your processing is doing and at what rate. If you are dealing with low freq signals, then use any high speed oscillator and get the sampling freq by division. With high freq sampling, you must adopt a suitable main oscillator (a multiple of the sampling freq). Hope this helps, Bert Cuzeau http://www.alse-fr.com -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 38788
Hello. I own 2.1i Student version. I selected a device from the SPARTAN2 family, entered a Schematic, and "compiled" things. All went well. Next, I entered a VHDL entry and went to the "Synthesis/Implementation" menu to select the target device and FPGA synthesis options. However, whenever I select Run from the this menu, I instantly get an error dialog. For example, if I select: Family: XC4000E Device: 4003EPC83 I get the following error: "The specified part XC302A-6-PC68 is either invalid or not supported. This similar error occurs for all families I select, except the CPLD families XC9500,XC9500XL. Selecting these families allows me to continue with the synthesis. Why can I only synthesize for the XC9500 & XC9500XL families? I have gone back to the project libraries menu and added in additional libraries, but nothing helps. I cannot get any of the following familes to work for synthesis: XC3000, XC4000*, SPARTAN*, XC5200, VIRTEX* Finally, why doesn't the SPARTAN2 family an option at this menu? I was able to select it when doing a schematic. I have added this family as a project library. I am new to all of this. Any help is greatly appreciated. Mark.Article: 38789
Hi.. Thanks alot for all the suggestions... I am wondering how to determine the sampling frequency from the timing diagram that I obtained after simulation? And how do I enter the required frequency into the FPGA ? Through external crystal clock or just using internal FPGA Board clock (in Altera UP-1 Board ,it is 25.175MHz) ? Thanks again... regards, johnArticle: 38790
Why on certain flip-flop to flip-flop paths is the setup for the final flip flop defined as positive and in other cases negative. We have one component where the path finishes in a xilinx xla4000 ofdx pin ce and the setup requirement is given as 1.5ns, while the other component, the path finishes in FD pin D and the setup requirement is given as -1.5 ns. How are the setup requirements values calculated? Thanks PaulArticle: 38791
Hello Shawn, Since more than two years, I'm using Synplicity's Synplify and Synplify Pro. I bought this tool for the company I worked before, and when I started here, I also was involved in buying this tool again! I compared a design for both, FPGA Express and Synplify, and the results were incredible. In the morning I installed the tool with an evaluation license. Did the setup for my design in the afternoon and ... In a fraction of runtime I got a 20% smaller design which was running at 20% faster clock frequency! The same day in the evening my former boss got a request to buy this tool. If your budget allows it, I think this is the best tool to work with. For large designs may be Synplicity's Amplify has some featuers you will need. I'm still using Synplify Pro now and in the near future I want to try XST once. Best regards, Andreas. Shawn wrote: > I have been using FPGA express with the Xilinx foundation software. I > found it to be a good tool. Unfortunately, Xilinx will no longer be > supplying FPGA express with its other software. Does anyone know if there > the Xilinx synthesis tool (XST) is comparable in performance to FPGA > Express? Is there an article comparing the performance of the major > synthesis tools for Xilinx (FPGA Express, Exemplar, Synplicity, XST, etc)? > The majority of the people I have spoken with seem to prefer Synplicity, but > the majority of them have very limited or no exposure to the other tools. > > Thank you in advance, > Shawn Hineline > > -- > ******************************* > Shawn Hineline > Optimum Engineering, Inc.Article: 38792
"Mark Kinsley" <Mark.Kinsley@blueyonder.co.uk> writes: > Has anybody done any benchmarking of EDA software under different hardware > platforms... I'm a brand-name sucker and tend to buy Intel - but how does > AMD compare. And how does a Celeron compare to a similar speed P3. I'm > using ModelSim, Leonardo Spectrum & Quartus (all under Windows). > I benchmarked P3 vs P4 recently ... http://groups.google.com/groups?hl=en&selm=uu1xqjbud.fsf%40trw.com I recall testing a Celeron vs PII a long time ago and the Celeron was quicker due to the core speed L2 cache. I imagine PIII is somewhat quicker than an equivalent Celeron as is has a bigger cache IIRC. I'm awaiting an AMD system to test .... Cheers! Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 38793
Hi all, Does the free xilinx webpack come with a technology viewer? (shows a schematic equivalent of your vhdl) What is used for the vhdl compiler? Is it VHDL-93? How optimal is the routing generation, is it recommended to 'adjust' the output manually? (for sram based fpgas) Does it come with any timing analysis tools? Is there anything major omitted compared to a 'real' tool? What chip is smallish and sram based like an acex-1k30?Article: 38794
Hi all, the biggest part of Xilinx' Virtex-II family should be the XC2V10000 with 10 Mio. System gates. But I can't find anymore any information on this part on Xilinx' web. Only the press release: http://www.xilinx.com/prs_rls/silicon_vir/0207_EProd_PoY.html from Jan 23th 2002 still talks about 10 Mio. gates devices. Can anyone comment on this? Regards, MarkusArticle: 38795
Hi all, actually I need to 'fight' with the UCF File in order to decrease the delay until the databus buffers do open from tristate to drive. I have the following: When dsp_csn AND dsp_rdn are low, then open the buffers of the data bus. In the UCF-File I did the following setting, which seems impossible to meet. Each time I get 7.5..8.3ns until the buffers are open and driving. Can anybody give me an advice how I can improve it, without changing the pinning or the layout... -- Snip ucf-file ############################################################################ ### ## Trying to make to Main DSP output enable faster. 24.01.2002 -mm- TIMEGRP DSPRdDataPath = PADS(dsp_data(*)); ############################################################################ ### TIMEGRP DSPRdCtrlPath = PADS(dsp_csn : dsp_rdn); ############################################################################ ### TIMESPEC TSP2P = FROM : DSPRdCtrlPath: TO : DSPRdDataPath : 6ns; ############################################################################ ### ############################################################################ ### ## Increase Driver Strength 25.01.2002 -mm- NET "dsp_data(*)" IOSTANDARD = LVTTL; NET "dsp_data(*)" DRIVE = 12; -- Snip ucf-file markus -- ******************************************************************** ** Meng Engineering Telefon 056 222 44 10 ** ** Markus Meng Natel 079 230 93 86 ** ** Bruggerstr. 21 Telefax 056 222 44 10 ** ** CH-5400 Baden Email meng.engineering@bluewin.ch ** ******************************************************************** ** Theory may inform, but Practice convinces. -- George Bain **Article: 38796
Valid point. A couple of my customers asked the same question. They just want to connect the board to a 9V or 12 V supply and go. I will have to look at the cost, size and heat implications of adding it to the PCB. Victor "Nial Stewart" <nials@britain.agilent.com> wrote in message news:3C4FD9D8.57425BBC@britain.agilent.com... > Victor Schutte wrote: > > > > > > > Requirements: A PC with Win98 or Win2000, serial port and Power supply > > (2.5V, 3.3V and 5V). > > Victor, you might find the requirement for 3 power > supplies will put people off. > > Could you not add regulators for the 3.3 and 2.5v supplies? > > > Nial.Article: 38797
"Mark Kinsley" <Mark.Kinsley@blueyonder.co.uk> wrote in message news:<OrQ38.1033$J92.7659561@news-text.cableinet.net>... > Has anybody done any benchmarking of EDA software under different hardware > platforms... I'm a brand-name sucker and tend to buy Intel - but how does > AMD compare. And how does a Celeron compare to a similar speed P3. I'm > using ModelSim, Leonardo Spectrum & Quartus (all under Windows). > > I've seen loads of benchmarks on the web which talk about games, office > apps and perhaps DTP - which of these applications is most simliar to EDA > software ? > > Mark I'm currently using Xilinx's Foundation series software. I've had the pleasure of testing it on both my home machine, which is an AMD Duron 750 MHz w/ WinME and 512 MB of RAM, and a Dell PIII 800 MHz, w/ Win2000 and 512 MB or RAM at school. I can't say I've seen much difference between the two machines, though the PIII is just a bit faster. Cheers, Jim.Article: 38798
You're looking for input-logic-tristate_out times that are extremely low. Admirable. Tough. Can't get there with just a UCF constraint. I'm basing the info below on recent Spartan-II design efforts - different devices may have different characteristics: If there's no way your enables can work properly with registered control logic (Tristate register in each IOB) then the only way to get your times is to "trick" the IOB elements into giving you the routing without the intermediate logic. If you use IOB registers for the data and need the fast clock-to-out times you may not have a choice. If your outputs are combinatorial or if you can push the output registers out of the IOB you have a chance. By using the IOB tristate register as a latch (which means the output must be a latch or combinatorial) you can work with the control signals for the data, the enable, and/or the reset to "effectively" provide the logic you're looking for, replicated in every output as a separate tristate latch. The result is that the signals don't have to get from the pads to the LUTs and back out to the pads but can go straight from pads to pads. This is especially helpful if your control and data signals are on the same side of the device. Any other attempts at improvement that I can come up with involve pin changes. - John Markus Meng wrote: > Hi all, > > actually I need to 'fight' with the UCF File in order to decrease the delay > until the databus buffers do open from tristate to drive. I have the > following: > > When dsp_csn AND dsp_rdn are low, then open the buffers of the data bus. > In the UCF-File I did the following setting, which seems impossible to meet. > Each time I get 7.5..8.3ns until the buffers are open and driving. > > Can anybody give me an advice how I can improve it, without changing the > pinning or the layout... > > -- Snip ucf-file > > ############################################################################ > ### > ## Trying to make to Main DSP output enable faster. 24.01.2002 -mm- > TIMEGRP DSPRdDataPath = PADS(dsp_data(*)); > ############################################################################ > ### > > TIMEGRP DSPRdCtrlPath = PADS(dsp_csn : dsp_rdn); > > ############################################################################ > ### > > TIMESPEC TSP2P = FROM : DSPRdCtrlPath: TO : DSPRdDataPath : 6ns; > ############################################################################ > ### > > ############################################################################ > ### > ## Increase Driver Strength 25.01.2002 -mm- > NET "dsp_data(*)" IOSTANDARD = LVTTL; > NET "dsp_data(*)" DRIVE = 12; > -- Snip ucf-file > > markus > > -- > ******************************************************************** > ** Meng Engineering Telefon 056 222 44 10 ** > ** Markus Meng Natel 079 230 93 86 ** > ** Bruggerstr. 21 Telefax 056 222 44 10 ** > ** CH-5400 Baden Email meng.engineering@bluewin.ch ** > ******************************************************************** > ** Theory may inform, but Practice convinces. -- George Bain **Article: 38799
Markus.Wannemacher@FernUni-Hagen.De (Markus Wannemacher) wrote in message news:<a2rsoa$bu8$1@oak.fernuni-hagen.de>... > Hi all, > > the biggest part of Xilinx' Virtex-II family should be > the XC2V10000 with 10 Mio. System gates. > But I can't find anymore any information > on this part on Xilinx' web. > > Only the press release: > http://www.xilinx.com/prs_rls/silicon_vir/0207_EProd_PoY.html > from Jan 23th 2002 still talks about 10 Mio. gates devices. > > Can anyone comment on this? > > Regards, > Markus The CEO of Xilinx mentioned some timeframe in the latest XCELL from Xilinx. Can't remember the date. Newman
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