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glen herrmannsfeldt wrote: > In many cases you would want both an FPGA to implement the most > used logic operations, and a DSP or other programmable processor > to implement the control functions, things like I/O operations > and such. > > Some logic operations work well in FPGA's while others don't. > Something as common as floating point arithmetic is very hard > to implement well in an FPGA, but is supported well by many DSP. > > Pretty much, you have to look at each algorithm individually > to see what the best implementation would be. In a nutshell: FPGAs are good at parallel implementations, thousands ( ten thousands !) of little LUT-engines running simultaneously. That's why they can beat DSPs by orders of magnitude in performance, but not in versatility and ease of use. DSPs are good at executing code sequentially ( yes, I know, sometimes a few in parallel). Not so fast, but more complex. Traditionally, FPGAs have shied away from floating point, but Virtex-II with hundreds of multipliers may change that ( the multiplier can also be used as a shifter ). This invites simplified non-IEEE floating point. Peter Alfke, Xilinx ApplicationsArticle: 38676
"Davis Moore" <"dmoore"@(nospam)ieee.org> wrote in message news:a2hva9$rg82@cliff.xsj.xilinx.com... > Brian Philofsky wrote: > > > Hicks wrote: > > > > > "Davis Moore" <"dmoore"@(nospam)ieee.org> wrote in message > > > news:a2hnf0$sgb1@cliff.xsj.xilinx.com... > > > > First of all, the integer type should only be used in a stimulus > > > > or testbench file. It is not synthesizable. You need a wire input > > > > into this module to compare against. > > > > > > I am not sure about that statement. I seem to recall using integers as a > > > signal in a VHDL system with no problem. Is Verilog different? Note that I > > > would not use an integer as an input or output port as I might expect that > > > the compiler would not handle that correctly. > > > Thanks, > > > Theron > > > > Whether it is synthesizable or not I guess would depend on the synthesis tool > > however I still agree with that advice of limiting intergers to the testbench > > regardless of whether the construct is synthesizable or not. If memory serves, > > the biggest gotcha with intergers is that they default to 32-bits whether you > > use all the bits or not. This can obviously grow the size of the required > > hardware in certain situations (especially things like multipliers) and in my > > opinion, it is best to be explicit with the bus sizing for any function in the > > design so that you can ensure you get what you think you will get. I guess the > > opposite effect could happen (lost bits) as well if you were expecting your > > result to be greater than 32-bits however I am not positive on that. In a > > testbench, you just need a slight more memory allocation for the simulation (if > > you do not use all 32-bits) but for the design files, synthesis can have a far > > more drastic effect on the resulting hardware if it interprets the Verilog > > language to the letter. > > > > The only time I usually use intergers is for "for" loops in the testbench. > > Otherwise, I will reg or wire the value. > > > > -- Brian > > > > > > According to 'Verilog HDL' by Palnitkar (Sunsoft Press - Prentice Hall) > an integer defaults to the width of the host machine word size and > is at least 32 bits. Also an integer stores signed values while a reg stores > unsigned - this could really affect synthesis results if used incorrectly. > > -Davis > Must be that Xilinx ISE4.1 does not follow that approach. I ran the following code using XST and only used 5 flipflops (3 slices). I checked it out in the floorplanner and in the place and route report. By the way I am running a Dell P3-500 with WIN2K so I don't think that I have a 5 bit word size. Or am I missing something in the discussion? Thanks, TheronArticle: 38677
> There was a time when Atmel had re-programmable SPROMs and Xilinx did not. Then > it made sense to use the Atmel device and live with its quirks ( poorly > documented Reset polarity, unknown power-on-reset delay) which caused people > some grief. I have helped several designs out of trouble... Which was a long time and several chip revisions ago. > Now that Xilinx also has re-writable SPROMs, why would you take a chance? Why not get the non-volatile memory from the guys who knows how to build small and thus cost effective non-volatile memories run by the man who has his signature on the first patent application for EEPROM ;-) I think you need to look at some REAL issues. * What is the cost of the chip. * What is the board size you get. * Power consumption etc. etc. and try to get advice from non-partial sources. I think there are plenty of happy users of both Xilinx EPROM& Atmel Flash configurators. > > Does someone used the Atmel's FPGA configuration memories with Xilinx > > Spartan-2, > > I'd like one for XC2S200 or should I stay with the originals XC18Vxx from > > Xilinx? Thank you. -- Best Regards Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Sweden.Article: 38678
Paul, I rip off single bits off a bus in the BDF by using a single "narrow" net connected directly to the bus "wide" net. If the bus is Q[16..0], the single narrow net should be named something like Q[12] to rip bit 12. I haven't tried generating VHDL out of it, but would imagine it does not look pretty. -Steen (replace junk with tech for email reply) "Paul" <nospam@nospamplease.com> wrote in message news:<2XW18.38760$Hg7.4213028@news11-gui.server.ntli.net>... > Using Quartus 2 1.1SP2 on W2k > > In order to document some bits of my design I took the decision to start > with block diagrams and then generate the VHDL for Leonardo or the Altera > tools to work with. (the VHDL for top level simple blocks, not the core VHDL > code). > > I find the block diagrams easier to use as documentation and this way have > the virtue of staying in sync with the design. > > However I can't seem to rip a single bit from a bus to go to a single output > pin as well as to its other destination. > [In the old days I used to be able to instantiate a bus ripper symbol and > rip a single bit but can't find an equivalent method now.] > > > The instance I have is a megawizard-generated 24 bit counter. > > q[23..0] are fed to an AND gate instance with the other input connected to a > single wire signal 'pass_it_through'. > > I have named this bus countval[23..0]. The output of the AND is called > 'gated_count' and is generated OK. > > Now I want a single bit of q (say q[7]) to go to another output pin named > 'pulsing_signal'. > > In the BDF I can't seem to get this to generate the correct VHDL. The > 'pulsing_signal' output is named as an output port but has no logic > associated with it. > > I can easily go into the VHDL and add the necessary link and it works fine, > but I'd really like to be able to rip this single bit in the BDF to keep the > design files in step. > > Any help appreciated. > > PaulArticle: 38679
Hicks wrote: > "Davis Moore" <"dmoore"@(nospam)ieee.org> wrote in message > news:a2hva9$rg82@cliff.xsj.xilinx.com... > > Brian Philofsky wrote: > > > > > Hicks wrote: > > > > > > > "Davis Moore" <"dmoore"@(nospam)ieee.org> wrote in message > > > > news:a2hnf0$sgb1@cliff.xsj.xilinx.com... > > > > > First of all, the integer type should only be used in a stimulus > > > > > or testbench file. It is not synthesizable. You need a wire input > > > > > into this module to compare against. > > > > > > > > I am not sure about that statement. I seem to recall using integers > as a > > > > signal in a VHDL system with no problem. Is Verilog different? Note > that I > > > > would not use an integer as an input or output port as I might expect > that > > > > the compiler would not handle that correctly. > > > > Thanks, > > > > Theron > > > > > > Whether it is synthesizable or not I guess would depend on the synthesis > tool > > > however I still agree with that advice of limiting intergers to the > testbench > > > regardless of whether the construct is synthesizable or not. If memory > serves, > > > the biggest gotcha with intergers is that they default to 32-bits > whether you > > > use all the bits or not. This can obviously grow the size of the > required > > > hardware in certain situations (especially things like multipliers) and > in my > > > opinion, it is best to be explicit with the bus sizing for any function > in the > > > design so that you can ensure you get what you think you will get. I > guess the > > > opposite effect could happen (lost bits) as well if you were expecting > your > > > result to be greater than 32-bits however I am not positive on that. In > a > > > testbench, you just need a slight more memory allocation for the > simulation (if > > > you do not use all 32-bits) but for the design files, synthesis can have > a far > > > more drastic effect on the resulting hardware if it interprets the > Verilog > > > language to the letter. > > > > > > The only time I usually use intergers is for "for" loops in the > testbench. > > > Otherwise, I will reg or wire the value. > > > > > > -- Brian > > > > > > > > > > According to 'Verilog HDL' by Palnitkar (Sunsoft Press - Prentice Hall) > > an integer defaults to the width of the host machine word size and > > is at least 32 bits. Also an integer stores signed values while a reg > stores > > unsigned - this could really affect synthesis results if used incorrectly. > > > > -Davis > > > > Must be that Xilinx ISE4.1 does not follow that approach. I ran the > following code using XST and only used 5 flipflops (3 slices). I checked it > out in the floorplanner and in the place and route report. By the way I am > running a Dell P3-500 with WIN2K so I don't think that I have a 5 bit word > size. Or am I missing something in the discussion? > > Thanks, > Theron I misstated myself....I meant that the signed/unsugned could really affect simulation results if used incorrectly. I also should have added that Palnitkar also notes that the width of an integer is implementation specific, so I imagine that different vendors deal with the issue in different ways. I am also by no means intimate with the detailed specifications of the language... especially newer versions like Verilog 2000. Theron, I don't see the code you said you ran in your post. I'm curious to see what you ran, could you repost?Article: 38680
Peter Alfke <peter.alfke@xilinx.com> writes: > Traditionally, FPGAs have shied away from floating point, but > Virtex-II with hundreds of multipliers may change that ( the > multiplier can also be used as a shifter ). This invites simplified > non-IEEE floating point. What's the most efficient way to implement a priority encoder in a Virtex-II to compute the number of bits needed to shift for normalization after FP add/subtract?Article: 38681
There must be many different methods. Here is one 18-input priority encoder that seems "creative" Use a BlockRAM, configured 1k x 18. Feed 9 bits into port A, the other 9 bits into port B. This produces un-encoded outputs, 9 from portA, 9 from port B ( stagger the output wiring appropriately ). Now you need a wide NOR of all 9 inputs on A to act as an enable for port B. If the BlockRAM were combinatorial, we could hide this wide NOR inside the ROM, but the BlockRAM read is clocked, so we must use external logic ( 2 or 3 LUTs ) to enable the outputs from port B. But we save the encoder/decoder needed to control the multiplier. as a shifter. There is only a single 1 coming from this 18-input priority encoder. I thank Bernie New for the basic idea. Peter Alfke, Xilinx Applications ======================================= Eric Smith wrote: > Peter Alfke <peter.alfke@xilinx.com> writes: > > Traditionally, FPGAs have shied away from floating point, but > > Virtex-II with hundreds of multipliers may change that ( the > > multiplier can also be used as a shifter ). This invites simplified > > non-IEEE floating point. > > What's the most efficient way to implement a priority encoder in a > Virtex-II to compute the number of bits needed to shift for normalization > after FP add/subtract?Article: 38682
You can take the tcl script that is listed at
http://support.xilinx.com/techdocs/2561.htm
This will compile and map libraries for you.
Brian Philofsky wrote:
>
> You mention you have compiled the libraries. If this is true, then it sounds like the problem you are seeing is you have not properly mapped the libraries to tell the simulator where the libraries exist on the system. You may do this from
> the GUI using the pull-down menus but I will describe the commands on how to do this here since it is easier to describe.
>
> Within the ModelSim simulator, change to the project directory if you are not already there:
> cd <path_to_project>
>
> Use the vmap command to tell the simulator where to find the required libraries:
> vmap xilinxcorelib_ver <path_to_compiled_corgen_lib>
> vmap unisims_ver <path_to_compiled_unisim_lib>
> vmap simprims_ver <path_to_compiled_simprim_lib>
>
> That should hopefully clear up the library and linking errors.
>
> -- Brian
>
> Orlls wrote:
>
> > when i simulate with modelsim5.5e,it says:
> > # testbench
> > # vsim -lib work -t 1ps -L xilinxcorelib_ver -L unisims_ver -L simprims_ver -foreign {hdsInit f:/eda_tools/resources/downstream/modelsim/ModelSim_32Bit.dll} -pli f:/eda_tools/resources/downstream/modelsim/ModelSim_32Bit.dll testbench glbl
> > # Loading f:/eda_tools/resources/downstream/modelsim/ModelSim_32Bit.dll
> > # Loading work.testbench
> >
> > # ERROR: Could not open library xilinxcorelib_ver at xilinxcorelib_ver: No such file or directory
> > # ERROR: Could not open library unisims_ver at unisims_ver: No such file or directory
> > # ERROR: Could not open library simprims_ver at simprims_ver: No such file or directory
> > # Loading work.NA_Message_Generate
> > # ERROR: Could not open library xilinxcorelib_ver at xilinxcorelib_ver: No such file or directory
> > # ERROR: Could not open library unisims_ver at unisims_ver: No such file or directory
> > # ERROR: Could not open library simprims_ver at simprims_ver: No such file or directory
> > # Loading work.NA_Message_Receive
> > # ERROR: Could not open library xilinxcorelib_ver at xilinxcorelib_ver: No such file or directory
> > # ERROR: Could not open library unisims_ver at unisims_ver: No such file or directory
> > # ERROR: Could not open library simprims_ver at simprims_ver: No such file or directory
> > # Loading work.na_fifo16_256
> > # ERROR: Could not open library xilinxcorelib_ver at xilinxcorelib_ver: No such file or directory
> > # ERROR: Could not open library unisims_ver at unisims_ver: No such file or directory
> > # ERROR: Could not open library simprims_ver at simprims_ver: No such file or directory
> > # Loading work.SYNC_FIFO_V3_0
> > # ERROR: Could not open library xilinxcorelib_ver at xilinxcorelib_ver: No such file or directory
> > # ERROR: Could not open library unisims_ver at unisims_ver: No such file or directory
> > # ERROR: Could not open library simprims_ver at simprims_ver: No such file or directory
> > # Loading work.MEM_BLK
> > # Loading work.glbl
> >
> > after i compile xilinx lib,there is not simprims_ver/xilinxcorelib_ver /unisims_ver directory.why?
--
/ 7\'7 Paulo Dutra (paulo@xilinx.com)
\ \ ` Xilinx hotline@xilinx.com
/ / 2100 Logic Drive http://www.xilinx.com
\_\/.\ San Jose, California 95124-3450 USA
Article: 38683
You don't need a priority encoder for normalization. Instead use a merged tree
shifter and make the shift decision at each step:
This shifter consists of n layers of 2:1 muxes. For the normalizing shift, you
need to do the largest shift first, so in the case of a 16 bit normalizer you
have 4 levels of 2:1 muxes. The first layer shifts data left by 8 bits if there
are 8 redundant sign bits in the input (if sign-magnitude format, then if there
are 8 leading zeros, if 2's comp then if top 9 bits are the same), otherwise
passes the data unchanged. The next layer shifts the data from the first layer
left by 4 bits if the top four bits of that data are redundant sign or passes it
unchanged otherwise, and so on. No priority encode needed, you can deeply
pipeline it easily (and at no cost), less real estate and clock latency than the
priority encode plus shifter approach, and the shift decisions at each level,
when concatenated together indicate the total shift, which can be the exponent.
This is not unique to VirtexII, and when pipelined is much (nearly 3x) faster
than either the multipliers or the block RAM.
Eric Smith wrote:
> Peter Alfke <peter.alfke@xilinx.com> writes:
> > Traditionally, FPGAs have shied away from floating point, but
> > Virtex-II with hundreds of multipliers may change that ( the
> > multiplier can also be used as a shifter ). This invites simplified
> > non-IEEE floating point.
>
> What's the most efficient way to implement a priority encoder in a
> Virtex-II to compute the number of bits needed to shift for normalization
> after FP add/subtract?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 38684
Davis Moore wrote:
> Hicks wrote:
>
> > "Davis Moore" <"dmoore"@(nospam)ieee.org> wrote in message
> > news:a2hva9$rg82@cliff.xsj.xilinx.com...
> > > Brian Philofsky wrote:
> > >
> > > > Hicks wrote:
> > > >
> > > > > "Davis Moore" <"dmoore"@(nospam)ieee.org> wrote in message
> > > > > news:a2hnf0$sgb1@cliff.xsj.xilinx.com...
> > > > > > First of all, the integer type should only be used in a stimulus
> > > > > > or testbench file. It is not synthesizable. You need a wire input
> > > > > > into this module to compare against.
> > > > >
> > > > > I am not sure about that statement. I seem to recall using integers
> > as a
> > > > > signal in a VHDL system with no problem. Is Verilog different? Note
> > that I
> > > > > would not use an integer as an input or output port as I might expect
> > that
> > > > > the compiler would not handle that correctly.
> > > > > Thanks,
> > > > > Theron
> > > >
> > > > Whether it is synthesizable or not I guess would depend on the synthesis
> > tool
> > > > however I still agree with that advice of limiting intergers to the
> > testbench
> > > > regardless of whether the construct is synthesizable or not. If memory
> > serves,
> > > > the biggest gotcha with intergers is that they default to 32-bits
> > whether you
> > > > use all the bits or not. This can obviously grow the size of the
> > required
> > > > hardware in certain situations (especially things like multipliers) and
> > in my
> > > > opinion, it is best to be explicit with the bus sizing for any function
> > in the
> > > > design so that you can ensure you get what you think you will get. I
> > guess the
> > > > opposite effect could happen (lost bits) as well if you were expecting
> > your
> > > > result to be greater than 32-bits however I am not positive on that. In
> > a
> > > > testbench, you just need a slight more memory allocation for the
> > simulation (if
> > > > you do not use all 32-bits) but for the design files, synthesis can have
> > a far
> > > > more drastic effect on the resulting hardware if it interprets the
> > Verilog
> > > > language to the letter.
> > > >
> > > > The only time I usually use intergers is for "for" loops in the
> > testbench.
> > > > Otherwise, I will reg or wire the value.
> > > >
> > > > -- Brian
> > > >
> > > >
> > >
> > > According to 'Verilog HDL' by Palnitkar (Sunsoft Press - Prentice Hall)
> > > an integer defaults to the width of the host machine word size and
> > > is at least 32 bits. Also an integer stores signed values while a reg
> > stores
> > > unsigned - this could really affect synthesis results if used incorrectly.
> > >
> > > -Davis
> > >
> >
> > Must be that Xilinx ISE4.1 does not follow that approach. I ran the
> > following code using XST and only used 5 flipflops (3 slices). I checked it
> > out in the floorplanner and in the place and route report. By the way I am
> > running a Dell P3-500 with WIN2K so I don't think that I have a 5 bit word
> > size. Or am I missing something in the discussion?
> >
> > Thanks,
> > Theron
>
> I misstated myself....I meant that the signed/unsugned could really
> affect simulation results if used incorrectly. I also should have
> added that Palnitkar also notes that the width of an integer
> is implementation specific, so I imagine that different vendors
> deal with the issue in different ways. I am also by no means
> intimate with the detailed specifications of the language...
> especially newer versions like Verilog 2000.
>
> Theron,
>
> I don't see the code you said you ran in your post. I'm curious to see
> what you ran, could you repost?
My apollogies,
I forgot to paste it in. I will do so tomorrow A.M.
Article: 38685I'm a happy user of both Atmel and Xilinx (alphabetical order) chips. Nothing is perfect. (read: I'm gonna implement into my design whatever is _cheaper_). So, you two guys, cease the fire and help us out with usable advices. "Ulf Samuelsson" <ulf@atmel.REMOVE.com> wrote in message news:ki038.5981$O5.14821@nntpserver.swip.net... > > There was a time when Atmel had re-programmable SPROMs and Xilinx did not. > Then > > it made sense to use the Atmel device and live with its quirks ( poorly > > documented Reset polarity, unknown power-on-reset delay) which caused > people > > some grief. I have helped several designs out of trouble... > > Which was a long time and several chip revisions ago. > > > Now that Xilinx also has re-writable SPROMs, why would you take a chance? > > Why not get the non-volatile memory from the guys who knows how to build > small > and thus cost effective non-volatile memories run by the man who has > his signature on the first patent application for EEPROM ;-) > > I think you need to look at some REAL issues. > * What is the cost of the chip. > * What is the board size you get. > * Power consumption > etc. etc. > and try to get advice from non-partial sources. > I think there are plenty of happy users of both Xilinx EPROM& Atmel Flash > configurators. > > > > > Does someone used the Atmel's FPGA configuration memories with Xilinx > > > Spartan-2, > > > I'd like one for XC2S200 or should I stay with the originals XC18Vxx > from > > > Xilinx? Thank you. > > -- > Best Regards > Ulf at atmel dot com > These comments are intended to be my own opinion and they > may, or may not be shared by my employer, Atmel Sweden. > > > > > >Article: 38686
Hi everyone I am using synplicity6.2.4 to sythesis and then use quartus to P&R my design is an CPU(nnarm),I INFER a small rom to hold the small program for it. so I want to ask a question : if the content of the rom can affect the synthesis result of the whole cpu? because the syn and then p&r is a very long process(about 40 min), so when I only modify the program in the rom, I do not want to run the whole process, I want to regenerate the mif file , and then directly P&R with back annotated placemenmt information, this reduce the process to only 10 minArticle: 38687
Hi, gurus: I am encountering problems when I do gate-level simulation in ModelSim, with Spartan-II, I tried to use `uselib but it doesn't seem to work. I tried to compile all the gates into my library together with gatelevel netlist, it displays lot of error when load the design. -- Best Regards, kelvinArticle: 38688
I've posted a very small example project (and put a service request at Altera), but can you see any obvious thing I'm doing wrong with the enclosed bdf file. I've loaded at archived project (http://homepage.ntlworld.com/paul_baxter/bustest/bustest.qar ) http://homepage.ntlworld.com/paul_baxter/bustest/ for all the files themselves Its only a 9k archived project. Essentially I've created one arbitrary megafunction and connected q[23..0] to one output and tried to also connect q[7] to another single wire output called tickpulse. The BDF analyses OK and says it generates the VHDL OK, but there is no logic or connection generated for the tickpulse output. Thanks if you do manage to have a look Paul "Steen Larsen" <steen_junk@yahoo.com> wrote in message news:ba62bd8d.0201211417.62d989c1@posting.google.com... > Paul, I rip off single bits off a bus in the BDF by using a single > "narrow" net connected directly to the bus "wide" net. If the bus is > Q[16..0], the single narrow net should be named something like Q[12] > to rip bit 12. I haven't tried generating VHDL out of it, but would > imagine it does not look pretty. > -Steen > (replace junk with tech for email reply) > > "Paul" <nospam@nospamplease.com> wrote in message news:<2XW18.38760$Hg7.4213028@news11-gui.server.ntli.net>... > > Using Quartus 2 1.1SP2 on W2k > > > > In order to document some bits of my design I took the decision to start > > with block diagrams and then generate the VHDL for Leonardo or the Altera > > tools to work with. (the VHDL for top level simple blocks, not the core VHDL > > code). > > > > I find the block diagrams easier to use as documentation and this way have > > the virtue of staying in sync with the design. > > > > However I can't seem to rip a single bit from a bus to go to a single output > > pin as well as to its other destination. > > [In the old days I used to be able to instantiate a bus ripper symbol and > > rip a single bit but can't find an equivalent method now.] > > > > > > The instance I have is a megawizard-generated 24 bit counter. > > > > q[23..0] are fed to an AND gate instance with the other input connected to a > > single wire signal 'pass_it_through'. > > > > I have named this bus countval[23..0]. The output of the AND is called > > 'gated_count' and is generated OK. > > > > Now I want a single bit of q (say q[7]) to go to another output pin named > > 'pulsing_signal'. > > > > In the BDF I can't seem to get this to generate the correct VHDL. The > > 'pulsing_signal' output is named as an output port but has no logic > > associated with it. > > > > I can easily go into the VHDL and add the necessary link and it works fine, > > but I'd really like to be able to rip this single bit in the BDF to keep the > > design files in step. > > > > Any help appreciated. > > > > PaulArticle: 38689
At first I'd like to say, that the board, I start to design, is not commercial. It is just my hobby and Atmel sends me 3-4 free samples. May be Xilinx too, but I didn't found any page for sample request... Now I have 2x XC2S200 and would like to use something for configuration. What is the best type for this device? Thank you. Andrej "Peter Alfke" <peter.alfke@xilinx.com> schrieb im Newsbeitrag news:3C4C70B0.7F72F3E8@xilinx.com... > There was a time when Atmel had re-programmable SPROMs and Xilinx did not. Then > it made sense to use the Atmel device and live with its quirks ( poorly > documented Reset polarity, unknown power-on-reset delay) which caused people > some grief. I have helped several designs out of trouble... > Now that Xilinx also has re-writable SPROMs, why would you take a chance? > > Peter Alfke, Xilinx Applications > ================================== > Andrej Jancura wrote: > > > Does someone used the Atmel's FPGA configuration memories with Xilinx > > Spartan-2, > > I'd like one for XC2S200 or should I stay with the originals XC18Vxx from > > Xilinx? Thank you. > > > > Kinds regards, > > Andrej >Article: 38690
Hello, I don't know if this is the right place to post this message. If not, please redirect me to the right place. We are working with a XSV800 board and we want to capture images via RCA jack, and visualize them on a VGA monitor. We are using a standard B/W surveillance PAL TV camera. We are using the Foundation 3.1i and the latest version of GXStools. We have built a project from the University of Queensland. After compiling the design we download the .bit file on the board and then we try to program the SAA7113 via the parallel port (using the SAA7113.exe file and the DLPORTIO.dll). But we get the following message after executing each command line: -- call saa7113 w 1 8 saa7113 MINOR ERROR: Transmission NACK'ed -- It seems that we can't use the parallel port to program the SAA7113 video decoder after downloading the .bit file. If we program the video controller (in the same way) before downloading the .bit file, all works fine, but since the downloading of the .bit file resets the video decoder, it gets unprogrammed. Then, we have tried to program the video controller via harware by means of the I2C bus. We have used a project from the XESS site (uncommenting the:"u4: saa7113init " in the SAA7113.vhd as is specified in the project). We obtained some compiling and implementing errors and we were unable to use it. Has anyone programmed the SAA7113 video decoder from the XSV board via the parallel port or via the I2C bus? Any help would be grateful. Thank you very much in advance. David de Andrés.Article: 38691
> always @(posedge Clock or negedge Rst_N) > begin > if(!Rst_N) > k<=0; // or could be k<=A or k<= 32'b01010110...01 depending on your intention > else if(load_k) > k<=A; > else if(dec_k) > k<=k-1; > else > k<=k; // provided to avoid latch inference > end For what it's worth. I do not believe that the k<=k; statement is required to avoid a latch inference in a clocked "process". In Synplicity VHDL, the k<=k; statement will result in a note or a warning, and I am 75% confident that the same holds true for Verilog. NewmanArticle: 38692
shengyu_shen@hotmail.com (ssy) wrote in message news:<f4a5f64f.0201212341.40127c59@posting.google.com>... > Hi everyone > > I am using synplicity6.2.4 to sythesis and then use quartus to P&R > > my design is an CPU(nnarm),I INFER a small rom to hold the small > program for it. > so I want to ask a question : if the content of the rom can affect the > synthesis result of the whole cpu? > > because the syn and then p&r is a very long process(about 40 min), so > when I only modify the program in the rom, I do not want to run the > whole process, I want to regenerate the mif file , and then directly > P&R with back annotated placemenmt information, this reduce the > process to only 10 min My particular experience is with Xilinx Coregen Block ROM's instantiated (not inferred) in a Virtex part where I used initialization files to define the initial contents of the block RAM/ROM. I had no problems changing the the initialization file and then doing a place and route. There is rumour that one can even change the ROM contents in Xilinx without doing a place and route via JBITs. I cannot personally status that avenue. NewmanArticle: 38693
On 21 Jan 2002 23:41:04 -0800, shengyu_shen@hotmail.com (ssy) wrote: >Hi everyone > >I am using synplicity6.2.4 to sythesis and then use quartus to P&R > >my design is an CPU(nnarm),I INFER a small rom to hold the small >program for it. >so I want to ask a question : if the content of the rom can affect the >synthesis result of the whole cpu? Yes. Think what would happen if one of the (inferred) ROM outputs was a constant - the synthesiser would not generate any ROM; it would generate a fixed 0 or 1 instead. Similarly, if an output bit is a function of only a few address inputs, the synthesiser may decide to implement it as a logic function of those address inputs, instead of as a rom. Neglecting "optimisations" like that, there should be no difference. I would instantiate rather than infer a rom, as this is the only way to guarantee that you get what you want (even if the tools change). Regards, Allan.Article: 38694
Yes, depending on the ROM contents. If a bit is constant, that inferred
ROM bit may get optimized out. I've also seen cases where the ROM gets
replaced by logic. To avoid these, I find it better to instantiate the
ROM.
ssy wrote:
> Hi everyone
>
> I am using synplicity6.2.4 to sythesis and then use quartus to P&R
>
> my design is an CPU(nnarm),I INFER a small rom to hold the small
> program for it.
> so I want to ask a question : if the content of the rom can affect the
> synthesis result of the whole cpu?
>
> because the syn and then p&r is a very long process(about 40 min), so
> when I only modify the program in the rom, I do not want to run the
> whole process, I want to regenerate the mif file , and then directly
> P&R with back annotated placemenmt information, this reduce the
> process to only 10 min
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 38695Yeah, You can get the source code for 48bits crc-32 parallel calculation. Incase, if the all 48bits are not valid, How will you calculate the crc-32 for that valid bytes only. For example: Your code will take always 48bits ie., 6Bytes of data. If the incoming frame is not multiple of 6Bytes, atlast you will have some less bytes (<6Bytes). For that how will you use the same module. Regards, Muthu. Ray Andraka <ray@andraka.com> wrote in message news:<3C308D4E.280F00EA@andraka.com>... > Sure there is, but it is not obvious. check the 32 AND the 16 bit > boxes. That gives you the 48 bit variant. > > Kenily wrote: > > > Thanks! > > But there is not 48bit(width) > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 38696
Davis Moore wrote:
> Hicks wrote:
>
> > "Davis Moore" <"dmoore"@(nospam)ieee.org> wrote in message
> > news:a2hva9$rg82@cliff.xsj.xilinx.com...
> > > Brian Philofsky wrote:
> > >
> > > > Hicks wrote:
> > > >
> > > > > "Davis Moore" <"dmoore"@(nospam)ieee.org> wrote in message
> > > > > news:a2hnf0$sgb1@cliff.xsj.xilinx.com...
> > > > > > First of all, the integer type should only be used in a stimulus
> > > > > > or testbench file. It is not synthesizable. You need a wire input
> > > > > > into this module to compare against.
> > > > >
> > > > > I am not sure about that statement. I seem to recall using integers
> > as a
> > > > > signal in a VHDL system with no problem. Is Verilog different? Note
> > that I
> > > > > would not use an integer as an input or output port as I might expect
> > that
> > > > > the compiler would not handle that correctly.
> > > > > Thanks,
> > > > > Theron
> > > >
> > > > Whether it is synthesizable or not I guess would depend on the synthesis
> > tool
> > > > however I still agree with that advice of limiting intergers to the
> > testbench
> > > > regardless of whether the construct is synthesizable or not. If memory
> > serves,
> > > > the biggest gotcha with intergers is that they default to 32-bits
> > whether you
> > > > use all the bits or not. This can obviously grow the size of the
> > required
> > > > hardware in certain situations (especially things like multipliers) and
> > in my
> > > > opinion, it is best to be explicit with the bus sizing for any function
> > in the
> > > > design so that you can ensure you get what you think you will get. I
> > guess the
> > > > opposite effect could happen (lost bits) as well if you were expecting
> > your
> > > > result to be greater than 32-bits however I am not positive on that. In
> > a
> > > > testbench, you just need a slight more memory allocation for the
> > simulation (if
> > > > you do not use all 32-bits) but for the design files, synthesis can have
> > a far
> > > > more drastic effect on the resulting hardware if it interprets the
> > Verilog
> > > > language to the letter.
> > > >
> > > > The only time I usually use intergers is for "for" loops in the
> > testbench.
> > > > Otherwise, I will reg or wire the value.
> > > >
> > > > -- Brian
> > > >
> > > >
> > >
> > > According to 'Verilog HDL' by Palnitkar (Sunsoft Press - Prentice Hall)
> > > an integer defaults to the width of the host machine word size and
> > > is at least 32 bits. Also an integer stores signed values while a reg
> > stores
> > > unsigned - this could really affect synthesis results if used incorrectly.
> > >
> > > -Davis
> > >
> >
> > Must be that Xilinx ISE4.1 does not follow that approach. I ran the
> > following code using XST and only used 5 flipflops (3 slices). I checked it
> > out in the floorplanner and in the place and route report. By the way I am
> > running a Dell P3-500 with WIN2K so I don't think that I have a 5 bit word
> > size. Or am I missing something in the discussion?
> >
> > Thanks,
> > Theron
>
> I misstated myself....I meant that the signed/unsugned could really
> affect simulation results if used incorrectly. I also should have
> added that Palnitkar also notes that the width of an integer
> is implementation specific, so I imagine that different vendors
> deal with the issue in different ways. I am also by no means
> intimate with the detailed specifications of the language...
> especially newer versions like Verilog 2000.
>
> Theron,
>
> I don't see the code you said you ran in your post. I'm curious to see
> what you ran, could you repost?
Oops, I forgot to paste it in. I didn't implement reset, etc. so it isn't much of
a counter. It was just a test case. Here it is...
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port (
CLK: in STD_LOGIC;
COUNT: inout integer range 0 to 31);
end counter;
architecture Behavioral of counter is
begin
process(clk)
begin
if rising_edge(clk) then
count<=count+1;
end if;
end process;
end Behavioral;
Article: 38697
My current design requires using a counter to determine the width of a
pulse with relatively high accuracy. A while back, Peter Alfke recommended
that I look at using a couple of DCM's in a VirtexII to generate multiple
clock phases and then using each phase to clock a separate counter and then
summing the output of all counters to get a final count. It looks like a
winner for that particular application. Unfortunately, the target market
has changed. Now I need less resolution and lower cost so I am looking at
using a SpartanII. Can I still use the multiple phases (o, 890, 180, and
270 degrees) from the DLL in the same manner.
Also, I need a simple and reliable way to insure that the system does
not generate any runt clock pulses in the enable/disable count function. I
have seen circuitry that will allow the designer to switch from one clock to
another asyncronously. I need to switch from clock to no_clock without
generating any runt clocks. Can someone recommend a solution? Or perhaps I
should use a count enable input? It is not critical if the system misses
one clock pulse, as long as it does so somewhat consistently. I would
prefer to avoid any metastability.
Thanks,
Theron Hicks
Article: 38698
You need to decide how you will deal with these invalid bytes. I presume they should be
ignored (dropped) from the stream. If that is the case, then you'll have to buffer the
incoming data so that you can drop unwanted bytes. Masking the unwanted bytes at the CRC
is not trivial if you are presenting 6 bytes at a time. It is much easier if you present
a byte at a time, but it also means running the CRC at a 6x clock. If you can't do the 6x
clock, I'd opt for a fifo arrangement that stores bytes until you have at least 6 valid
ones and drops bad bytes. The holes left by bad bytes get grouped together so that you
skip over 6 bytes at a time at the CRC.
Muthu wrote:
> Yeah,
>
> You can get the source code for 48bits crc-32 parallel calculation.
> Incase, if the all 48bits are not valid, How will you calculate the
> crc-32 for that valid bytes only.
>
> For example:
>
> Your code will take always 48bits ie., 6Bytes of data. If the incoming
> frame is not multiple of 6Bytes, atlast you will have some less bytes
> (<6Bytes). For that how will you use the same module.
>
> Regards,
> Muthu.
>
> Ray Andraka <ray@andraka.com> wrote in message news:<3C308D4E.280F00EA@andraka.com>...
> > Sure there is, but it is not obvious. check the 32 AND the 16 bit
> > boxes. That gives you the 48 bit variant.
> >
> > Kenily wrote:
> >
> > > Thanks!
> > > But there is not 48bit(width)
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 38699This is a multi-part message in MIME format. --------------F4C08D5C34A5B542CD1C031C Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit I assume you are doing a Verilog simulation based on your `uselib usage. I suggest not to use `uselib and instead do the following steps to ensure you have properly compiled the libraries, mapped them, and are pointing to them: 1. Compile the SIMPRIM Libraries (also do the UNISIM and XilinxCoreLib libraries if you plan to use them) using the Xilinx library Tk/TCL script pointed to by: http://support.xilinx.com/techdocs/2561.htm They may be compiled to any directory on your system. (Not necessary or suggested if you are using Modelsim-XE) 2. Change to your project simulation directory and map to those compiled libraries. You can do this from the GUI or using the vmap command (Not necessary if you are using ModelSim-XE) vmap simprims_ver <path_to_compiled_simprim_library> 3. Compile simulation files and testbench to your working directory vlog <files> 4. When you invoke the simulation, point to the logical name for the compiled SIMPRIMs library you used for the mapping using the -L switch. vsim -L simprim_ver <testbench_module_name> If all of the above steps are done properly, you should not have any issues with linking the design to the library. If you need further assistance, I refer you to the Xilinx Synthesis and Simulation Design Guide which can be read online at: http://toolbox.xilinx.com/docsan/xilinx4/index.htm There are other ways to perform the above steps and you may use the `uselib if you prefer, I just think the above method is easier for most. The Xilinx Edition of ModelSim (ModelSim-XE) is much easier to use in this respect because the libraries are already pre-compiled and mapped for you. Good luck, -- Brian "X. Q." wrote: > Hi, gurus: > > I am encountering problems when I do gate-level simulation in ModelSim, with > Spartan-II, > I tried to use `uselib but it doesn't seem to work. > I tried to compile all the gates into my library together with gatelevel > netlist, it displays lot of error > when load the design. > > -- > Best Regards, > kelvin
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