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Hi, gurus: I am programming with Spartan-II chip. How come iMPACT indicates vcx100 when initializing the chain while my FPGA chip is actually an XC2S100-5PQ208. -- Best Regards, Qijun. ******************************************************************** Xu QijunArticle: 39602
"Paul Taylor" <p.taylor@ukonline.co.uk> wrote in message news:<T%Ga8.80$Jp6.82461@monolith.news.easynet.net>... > About 18 months ago, I etched a PCB for a XCS30XL-4TQ144C > header board. I now want to use it to start teaching myself VHDL, > but WebPACK doesn't support the SpartanXL. Is there a free version > of Foundation with VHDL available for playing with this? I can assure you that it does. You may need to install the various family files seperately when you have a WebPack CD. When you download from the web you need to make sure to select all the devices you care about up front. Achim Gratz.Article: 39603
chris wrote: > i am getting inconsistent results after my place and route of the asic > design i am prototyping. currently, i have declared all my clocks in > the static timing analyzer, and get about 97% coverage from it. the > same design is synthesized by synplicity on two different occasions. i > run it through the Xilinx Design Manager at an effort level of 5. the > problem is that only one of my runs out of about 15 multi-pass place > and routes works. the other runs exhibit different behaviors that seem > to be due to timing. the extra 3% is likely to be giving me trouble > since that area is an asynchronous portion of the circuit that is > important to its operation (clock recovery, etc...). is there a way to > make my design work consistently, assuming the code is correct? i > cannot continue to shoot blindly and pray that one run turns out okay. > can i constrain asynchronous parts of the circuit? > chris Chris, whether it is worth constraining the 3%, please try trce <design>.ncd <design>.pcf -o unconstr.twr -u 100 to dump the worst 100 unconstrained paths to unconstr.twr text file. The first 100 reports will be give you idea how to constrain this region. Yes, you can constrain, roughly said, whatever you want. You can use TPSYNC attribute. INST "chip/block/some_gate[*]" TPSYNC="gate_group" For further info, go: http://toolbox.xilinx.com/docsan/3_1i/data/common/dev/chap06/dev06009.htm UtkuArticle: 39604
I have got a PIII 800 MHZ with 784M of RAM and I simulate some VirtexII 3000 with no disk swapping but for Synthesis and implementation we have dedicated PC with 2 Gbyte memory and an ATHLON 1.3 GHz. So You can run TOP implementation and synthesis on a big PC with the maximum RAM and a burly processor ( near 2 GHz). You can run TOP simulation on it as well. And for module designing you can use 1Gbyte RAM upgradable to 2Gbyte and a little slower processor. This is a kind of resource sharing among the team!! It depends on what your purchase department allows you to have and I know that in THALES there are some typical configuration and it is difficult to have what we want. > Wow a P2? That's impressive. Consider getting a machine with one of > the newer memory achitectures like DDR or Rambus. The database that > the P&R tool is accessing is so large the processor is surely memory > bound. A 20kE400 probably needs a Gig minimum. > > As far as accellerating your sim times, consider running mini-frames > (1/4, 1/16, ...) untill you think everything is perfect, then > recompile with the full size and check. > > Regards > > "St?hane" <sjulhes@free.fr> wrote in message news:<3c6297a4$0$4618$626a54ce@news.free.fr>... > > Hello, > > > > I'm designing with Quartus II and Modelsim using VHDL on a DELL PII 450 Mhz > > with 256 Mo of RAM. > > The FPGA is an ALTERA APEX 20KE400 -2X in a FC672 package. > > > > I'm doing real time image treatment and i'm doing one frame simulation. > > > > The simulations times ( about 20mn ) and the Quartus working times ( about > > 12 mn for 12% of the APEX's ressources !! ) are quite long. > > > > I have the opportunity to buy a new PC, so what would be the best > > configuration to get a faster development workstation ??? > > > > Thanks. > > > > Stéphane. > > > > Thales Microelectronics.Article: 39605
Don't worry about that. When I programed a Spartan-II XC2S150-5CPQ208 while ago, ISE WebPACK 3.3's programmer told me that the chip I am programming is an XCV150. A manual that came with the prototype board said it is okay to ignore that message, so I just programmed a Configuration PROM attached to the Spartan-II XC2S150-5CPQ208, and the board worked fine. However, one thing worth mentioning is that a bitstream file for a Virtex XCV150 and for a Spartan-II XC2S150 are not guaranteed to be compatible. Kevin Brace (Don't respond to me directly, respond within the newsgroup.) "X. Q." wrote: > > Hi, gurus: > > I am programming with Spartan-II chip. > How come iMPACT indicates vcx100 when initializing the chain > while my FPGA chip is actually an XC2S100-5PQ208. > > -- > Best Regards, > Qijun. > > ******************************************************************** > Xu QijunArticle: 39606
Rick, Good points. Doesn't System Ace solve some of your problems? It must be good (as Altera has copied it, too!) Austin rickman wrote: > Austin Lesea wrote: > > > > Rick, > > > > Seriously, we didn't invent them, we just placed them in a fabric, and > > supported them in the FPGA. And as it turns out, you can get a patent for > > just that kind of assembly of non patentable items arranged in a new or > > novel way together to perform an improved function. Altera, and we have > > lots of patents, and now that the legal hassling is over, we can apply all > > of our efforts to supplying our customers with the best possible products. > > > > I appeciate all of the comments, and it is absolutely critical that Xilinx > > listen to customers, because that is what we did with Virtex, and Virtex II > > (and are still doing). > > > > No time to fiddle around, I have the next two product generations to help > > design, document, and support. > > > > Austin > > Be careful what you ask for, because you might just get it. You asked > for my input, so here it is. > > I am not a high speed data/telecom vendor and I don't do gigabit IO. I > use FPGAs for general purpose system "glue" and data movement > operations. There is sometimes a little DSP thrown in for good measure. > > As it turns out, the single biggest limitation in FPGAs that I am facing > is software. I need to be able to design a modular set of interfaces > that can be loaded into the chip in different combinations at run time. > There is no PC and no platform to run tools such as JBITS. There is a > small micro and a sizable hunk of Flash memory. If I could store a dozen > interchangable pieces that can be loaded into an FPGA in different > combinations, it would save me from having to design perhaps as many as > hundreds of different complete designs as distinct bit files. > > Any progress in this area? Not much point in making the chips bigger and > bigger if your software doesn't keep up. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 39607
"Theron Hicks" <hicksthe@egr.msu.edu> wrote in message news:3C641F90.FF4BADF0@egr.msu.edu... > > Also, I cannot get modelsim to recognize my coregen parts at the > behavioral level. How do I get that to work? Have you downloaded the latest ModelSim update from Xilinx. The Coregen models you want may not be in the distribution software. Good Luck Phil -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 39608
Hi! >> About 18 months ago, I etched a PCB for a XCS30XL-4TQ144C header board. >> I now want to use it to start teaching myself VHDL, but WebPACK doesn't >> support the SpartanXL. Is there a free version of Foundation with VHDL >> available for playing with this? > > I can assure you that it does. You may need to install the various > family files seperately when you have a WebPack CD. When you download > from the web you need to make sure to select all the devices you care > about up front. I have nearly the same problem. But Xilinx WebPACK does _not_ offer support for any Spartan or SpartanXL series FPGA. Only SpartanII and SpartanIIe are supported. But there are some free VHDL and Verilog programming environments available. For Verilog the Icarus project is available (at least for Linux) http://www.icarus.com/. But all available tools only give you an EDIF file which has to be translated to a .bit file, which is fed serially (or parallelly) into the SpartanXL FPGA. This translation is only made by Xilinx tools I am searching at the moment, too. Bye HansiArticle: 39609
Rick, Seriously, Altera has a product similar to System ACE (maybe better?). I apoloize for the cheap shot, it was not intended to come across the way some have told me it did. Thanks to those who let me know I was out of line. Does either solve some of your issues? Austin Austin Lesea wrote: > Rick, > > Good points. > > Doesn't System Ace solve some of your problems? It must be good (as Altera has > copied it, too!) > > Austin > > rickman wrote: > > > Austin Lesea wrote: > > > > > > Rick, > > > > > > Seriously, we didn't invent them, we just placed them in a fabric, and > > > supported them in the FPGA. And as it turns out, you can get a patent for > > > just that kind of assembly of non patentable items arranged in a new or > > > novel way together to perform an improved function. Altera, and we have > > > lots of patents, and now that the legal hassling is over, we can apply all > > > of our efforts to supplying our customers with the best possible products. > > > > > > I appeciate all of the comments, and it is absolutely critical that Xilinx > > > listen to customers, because that is what we did with Virtex, and Virtex II > > > (and are still doing). > > > > > > No time to fiddle around, I have the next two product generations to help > > > design, document, and support. > > > > > > Austin > > > > Be careful what you ask for, because you might just get it. You asked > > for my input, so here it is. > > > > I am not a high speed data/telecom vendor and I don't do gigabit IO. I > > use FPGAs for general purpose system "glue" and data movement > > operations. There is sometimes a little DSP thrown in for good measure. > > > > As it turns out, the single biggest limitation in FPGAs that I am facing > > is software. I need to be able to design a modular set of interfaces > > that can be loaded into the chip in different combinations at run time. > > There is no PC and no platform to run tools such as JBITS. There is a > > small micro and a sizable hunk of Flash memory. If I could store a dozen > > interchangable pieces that can be loaded into an FPGA in different > > combinations, it would save me from having to design perhaps as many as > > hundreds of different complete designs as distinct bit files. > > > > Any progress in this area? Not much point in making the chips bigger and > > bigger if your software doesn't keep up. > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 39610
You can buy a version of the 2.1i tools (2.1isp6) as part of the Xilinx Student Edition. This is a Prentice Hall product. Eric Albert Wang wrote: > > Hi, > > Does anybody have the Xilinx Foundation Series 2.1i newest not locked > license.dat file? My license file have already out of date and I need to go > back to a project which was designed under 2.1i for some detail matter. The > 3.1i also helpful. > > Thanks very much!Article: 39611
It is a good solution for someone that have a design and simulation as well. this is an advanced stage. But what should do a designer that have to choose a part much earlier ? Ray Andraka <ray@andraka.com> wrote in message news:<3C698A22.D81224EE@andraka.com>... > There is a tool in the 4.1 tools called xpower that will take the VCD > file from your simulation and the NCD from the place and route to > provide a more accurate power computation based on your simulation. > > Tamar Poker wrote: > > > Hi. > > I am looking for an excell sheet to do power estimation for virtex2 > > device. > > Unfortunately the excell sheet I found on the web is only for Virtex > > ane Virtex-E (xapp152). > > > > Is there something similiar for Virtex2 ? > > > > Tamar. > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 39612
FYI- I've worked with Xilinx support personnel Chris Arndt to determine the following behavior for "map" and "m1map": "map" will call the "sub-executable" called "m1map" for use when xc4k or spartan series devices are targeted. Additionally, if map is invoked with a -p switch to designate a device, that switch takes precedence over any information within the .ngd file. "Martin, Charles" <charles.w.martin@baesystems.com> wrote: > >Anyone know what the behavior of 4.1.02i ISE-Alliance software is with respect to the following >executables: >%XILINX%\bin\nt\map >%XILINX%\bin\nt\m1map > >I'm trying to determine the dependency utilized to determine which executable is utilized during the >mapping process. I suspect that it's device/architecture dependent, but wonder how the software >'knows' or 'decides' which executable to use. > >+ dependant upon the device (-p switch) identified when map called >+ dependant upon the .ngd file fed into map (-p switch also thrown during ngdbuild) >+ dependant upon the device specific Synthesis output (edif) fed into ngdbuild >+ other. > > >Article: 39614
tamar.poker@mailandnews.com (Tamar Poker) wrote in message news:<f77ba402.0202121007.47ce13c@posting.google.com>... > Hi. > I am looking for an excell sheet to do power estimation for virtex2 > device. > Unfortunately the excell sheet I found on the web is only for Virtex > ane Virtex-E (xapp152). > > Is there something similiar for Virtex2 ? > > Tamar. There is one available, but I didn't see it on their website. You should contact a Xilinx FAE and ask for the spreadsheet.Article: 39615
The bitstreams for virtex and spartanII for same size device are the same.
Kevin Brace wrote:
> Don't worry about that.
> When I programed a Spartan-II XC2S150-5CPQ208 while ago, ISE WebPACK
> 3.3's programmer told me that the chip I am programming is an XCV150.
> A manual that came with the prototype board said it is okay to ignore
> that message, so I just programmed a Configuration PROM attached to the
> Spartan-II XC2S150-5CPQ208, and the board worked fine.
> However, one thing worth mentioning is that a bitstream file for a
> Virtex XCV150 and for a Spartan-II XC2S150 are not guaranteed to be
> compatible.
>
> Kevin Brace (Don't respond to me directly, respond within the
> newsgroup.)
>
> "X. Q." wrote:
> >
> > Hi, gurus:
> >
> > I am programming with Spartan-II chip.
> > How come iMPACT indicates vcx100 when initializing the chain
> > while my FPGA chip is actually an XC2S100-5PQ208.
> >
> > --
> > Best Regards,
> > Qijun.
> >
> > ********************************************************************
> > Xu Qijun
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39616
I should probably cut and paste this into the FAQ, huh?
Falk Brunner wrote:
> "Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag
> news:3C6A719D.1E7A3E0F@andraka.com...
> > for 4K deep, it should be using 12 BRAMs arranged as 4Kx1 bit slices.
> > Just verify that it is doing that and not something silly with muxes. The
> > XCV***-4 parts' BRAM maxes out at about 125 MHz, but to get there you need
> > to put pipeline registers immediately before and after all the signals in
> > and out of the RAM. The worst timing is on the ENA and WE inputs. These
> > two really need a duplicated flip-flop driving them and located
> > immediately adjacent to the BRAM (1 FF per BRAM). Check your timing reprot
> > for the worst case paths. dollars to donuts the WE and/or ENA paths are
> > among the worst. Also, you should probably duplicate the address
> > generators, especially if you have not located all the RAMs close
> > together. One last thing, the automatic place and route does a lousy job
> > at placing the BRAMs, use the floorplanner to place the RAMs close
> > together and to place the pipeline registers adjacent to the BRAMs.
>
> Arnt you getting tired of repeating over and over again this BRAM issue? I
> think this is a VERY good entry for the FPGA FAQ, isnt it?
>
> --
> MfG
> Falk
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39617I have been provided with a schematics based project as well as an HDL based project, each of which were previously successfully implemented. I am tasked with re-implementing the project to a new working chip. So far, attempts at recreating the projects in Foundations 3.1 (for the schematics project) and ISE4.1 (for the HDL project) have failed. I have been able to recreate the HEX prom files from the provided bit strems and load these into the system active. However I have been unable to go from the code or schematic level to working HEX files. My new thought is to try creating a bit stream from the provided NCD files which would put me on track to figure out what implementation options were in use. Any ideas on how to go directly from an NCD to a BIT file for implementation?Article: 39618
I am working on an HDL project that uses a couple Logiblox modules (they happen to be DPRAM memories of size 16x8 and 128x8 with normal gates settings). I created the logiblox components by double clicking on in the ISE HDL instantiation tree and selecting a new Logiblox component, then entering the appropriate component specs. However, the HDL source icon remained a red question mark, although the module was listed in the the source files for the project (outisde of the VHDL flow portion of the project tree). I then right-clicked the HDL icon for the ram and selected add source and chose the appropriate VHD source file. The icon changed to the desired blue checkmark. However, during synthesis I receive warning that the logiblox cells are unconnected. A quick look at the schematic generator verifies that the RAM modules have not been placed in the synthesized design. I have verified my instantions and that the Logiblox module is creating xnf/ngc/netlists for the modules. Any ideas?Article: 39619
Talk to your FAE. There is a spreadsheet floating around, but I couldn't find it on the
website.
Tamar Poker wrote:
> It is a good solution for someone that have a design and simulation
> as well. this is an advanced stage.
>
> But what should do a designer that have to choose a part much earlier ?
>
> Ray Andraka <ray@andraka.com> wrote in message news:<3C698A22.D81224EE@andraka.com>...
> > There is a tool in the 4.1 tools called xpower that will take the VCD
> > file from your simulation and the NCD from the place and route to
> > provide a more accurate power computation based on your simulation.
> >
> > Tamar Poker wrote:
> >
> > > Hi.
> > > I am looking for an excell sheet to do power estimation for virtex2
> > > device.
> > > Unfortunately the excell sheet I found on the web is only for Virtex
> > > ane Virtex-E (xapp152).
> > >
> > > Is there something similiar for Virtex2 ?
> > >
> > > Tamar.
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39620
I should qualify my statement. ISE4.1 seems to do better and/or faster than 3.3 for push the big green pushbutton designs. For designs that have been floorplanned, 3.3 does a consistently better job routing. The floorplanner in 4.1 has some
problems that need to be resolved as well. SO if your design falls in the push the button flow category, then you'll probably be happy or even happier with 4.1. If you are pushing the envelope, then you'll find that 4.1 is a step backwards.
ZhengLin wrote:
> Ise supports language designs very well, and it will use less resource when doing the same thing in the foundatation when a projrct is designed by using language, so if you using language and you have time, you'd better to learn how to use ise!
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39621"Phil Connor" <p.connorXXX@optionYYY.com> wrote in message news:<d4ff0eda6b2213fa92f8bd957c3fa4f7.58911@mygate.mailgate.org>... > "Theron Hicks" <hicksthe@egr.msu.edu> wrote in message > news:3C641F90.FF4BADF0@egr.msu.edu... > > > > > > > Also, I cannot get modelsim to recognize my coregen parts at the > > behavioral level. How do I get that to work? > > > Have you downloaded the latest ModelSim update from Xilinx. The > Coregen models you want may not be in the distribution software. > > Good Luck > > Phil You have to compile the coregen xilinx source to a modelsim library and map the the library name to the compiled directory (VHDL Flow). I do not recall the exact steps, but there should be an appnote either at www.Xilinx.com or www.Model.com NewmanArticle: 39622
Hi. For a project I like to invent and implement a lean (co)processor that handles serial protocols (such as SPI, I2C, UART, etc). It should be software programmable like a processor, so that new protocols can be added without changes to the VHDL source / bitstream. On the other hand, it should be almost as lean and light weight as a simple state machine. I plan to fit several such processors (in parallel) into a small 50K gate FPGA. I'm not sure yet about the optimum instruction set, nor about the other characteristics of such a processor. I think about a structure where the PC addresses 64 instructions, and all instructions operate on bits (not bytes). The bits include 8 I/O pins, a byte-buffer register (possibly only MSB and LSB addressable), handshake lines from/to the host, and two temp bits. My idea is to have two parallel processors per serial channel, one for TX and one for RX. The instruction set of them can be biased towards the data direction (TX processor can read from byte-buffer and write to I/O pin, while RX processor reads from I/O pin and writes to byte-buffer). What do you think about this? Is there any code or other work available that might serve as inspiration for nailing down a good and practical instruction set? MarcArticle: 39623
> > About 18 months ago, I etched a PCB for a XCS30XL-4TQ144C > > header board. I now want to use it to start teaching myself VHDL, > > but WebPACK doesn't support the SpartanXL. Is there a free version > > of Foundation with VHDL available for playing with this? > > I can assure you that it does. You may need to install the various > family files seperately when you have a WebPack CD. When you download > from the web you need to make sure to select all the devices you care > about up front. Yes, I downloaded with all options selected, and there's spartanxl folders... C:\xilinx_webpack\spartanxl\bin\nt\libBsSxl_Bitstream.dll C:\xilinx_webpack\spartanxl\data\ (containing 38 files) But neither File-New Project, nor Source-Properties-Device Family allow me to choose SpartanXL, although SpartanXL is in the on-line help, e.g. "Configuration Property Options for Spartan-XL" etc. It seems strange to me for Xilinx to not bother supporting XL in this latest software, especially if they can't offer a free alternative for XL with VHDL?! I was going to try Altera's free software, but it doesn't run on Windows ME. Paul T.Article: 39624
jetmarc wrote: > > Hi. > > For a project I like to invent and implement a lean (co)processor that handles > serial protocols (such as SPI, I2C, UART, etc). It should be software > programmable like a processor, so that new protocols can be added without > changes to the VHDL source / bitstream. On the other hand, it should be > almost as lean and light weight as a simple state machine. I plan to fit > several such processors (in parallel) into a small 50K gate FPGA. > > I'm not sure yet about the optimum instruction set, nor about the other > characteristics of such a processor. I think about a structure where the > PC addresses 64 instructions, and all instructions operate on bits (not bytes). > The bits include 8 I/O pins, a byte-buffer register (possibly only MSB > and LSB addressable), handshake lines from/to the host, and two temp bits. > > My idea is to have two parallel processors per serial channel, one for TX > and one for RX. The instruction set of them can be biased towards the data > direction (TX processor can read from byte-buffer and write to I/O pin, while > RX processor reads from I/O pin and writes to byte-buffer). > > What do you think about this? Is there any code or other work available that > might serve as inspiration for nailing down a good and practical instruction > set? > > Marc Interesting idea. Scenix(ubicom) use a PIC 12 bit opcode variant core, and a Soft peripheral. You could also look at Bit-Slice processors - I have seen a number on the WEB. You could see if a subset-opcode of the PIC12 could be used, as even that small opcode has more 'reach' than you need - and then you can use the PIC or SX core tools and even silicon, as test vechicle. A simple 12 Bit Opcode -> Smaller Converter/error catcher pgm, would take any PIC file, and ready it for your FPGA engine. Code the tasks first, then see what subset of opcode and RAM coverage was needed, and use that subset for your 'state engine'. Some BYTE operations could be usefull for loop counters, and FIFO construction, and MACRO blocks can always be used if the PIC opcodes do not map well to this. ( here two/three/four... opcodes would map onto one of your new opcodes ) eg PIC uses a skip/jump construct, but more efficent is a short jump opcode as seen in COP8, and Fairchild ACE1101 IIRC, Philips also had some sort of communications engine chip, that made it to data a while ago, using a similar idea of a fast, state engine like core for data packet pumping ( tho this used underlying silicon as well ) -jg
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