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On Aug 26, 6:53=A0am, Bert_Paris <do_not_s...@me.com> wrote: > Dans son message pr=E9c=E9dent, Bert_Paris a =E9crit :> for Altera FPGAs. > > I don't assume it's going to be useful for Xilinx (or Actel or Lattice) > users, since most of the work is about undesrtanding how to use the > *Altera* Megafunction named "altremote_update"... > Bert Oh, I assumed that Startan III was an Alterinx product like Stratex 7 :)Article: 148801
Hi Guys, I'm trying to make a jtag adapter out of an 8-bit micro-controller and a usb-serial adapter. So far, I can connect to my target and read it's IDCODE upon power up, due to it being automatically loaded on the data register, and being it the same as specified in the data sheet. However, I'm encountring problems when shifting data into the tap. Initially, my attempt is to shift the IDCODE instruction into the shift-ir register so I can read it back again, and to know that I can both, send and receive data from the tap. However, having tried several different things I'm done a bit of a mess (plus that I don't fully yet understand jtag), so I'd appreciate if somebody could give me a hand with my questions. When I phisically reset the device and go to the shift-dr state in order to grab devices's IDCODE. Some data (concretely a 0x1) is put by the tap on TDI while I'm shifting out of TDO. Am I wrong if I just ignore data put into the i/o register I'm not currently working with (TDI or TDO)? or is it needed to store it and feed it back somehow for things to work properly? My whole proccess right now is as follows: * I reset the device. * Go to the shift-dr state, and grab the device's IDCODE. * From update-dr (which is where the shift-out operation leaves me) I move to the shift-ir state, and start shifting in the IDCODE instruction. * From update-ir, I move into shift-dr again, so as to read it back. Then I always read the same bytes, but these hasn't got nothing to do with the IDCODE read initally. Regards,Article: 148802
On Aug 1, 11:56=A0am, Jonathan Bromley <s...@oxfordbromley.plus.com> wrote: > On Sun, 1 Aug 2010 01:06:16 +0000 (UTC), Giorgos Tzampanakis wrote: > >Where can I find a listing of the features that were added to > >Verilog in the 2001 version, and then of the ones added in > >SystemVerilog? > Verilog 95 to 2001 differences are summarized in http://www.sutherland-hdl.com/papers/2001-SNUG-paper_Verilog-2000_standard.= pdf . Verilog 2001 to SystemVerilog is described in the overview section of the SV LRM 1800-2005 (page 15). The SV LRM only describes the SV extensions to Verilog 2001.Article: 148803
Hi, While studying the MIG ref design for Spartan-6 I was surprised to find a IODRP2_MCB which doesn't have any documentation. Any information about it? ThanksArticle: 148804
Hi,
I am working on establishing Client-Server module over TCP.I have put a set
up such that my PC acts as a normal server where I can connect it from some
other PC's on my LAN using 'telnet ipaddress port' command and once I get
connected with the server and can give some input from client computer so
that it gets displayed on my server window(connection is established and
data exchange takes place).
Until here I can say that the server is working fine and what i wanted to
implement is that now I wrote a code using lwIP API for the Altium
Nanaboard so that my NB3000 acts like a client and i wanted it to get
connected to my PC Server.
Here goes my code for the client part which gets connected to the Server
with given IPaddress.
int tcp_client(void)
{
char data[] = "Hello World";
struct netconn *conn;
struct ip_addr ServAddr;
err_t err;
u16_t port;
port = 7777;
conn = netconn_new(NETCONN_TCP);
IP4_ADDR(&ServAddr, 192,168,xx,xxx);
err = netconn_connect(conn, &ServAddr, port);
printf("err = %d", err); // here I am getting err = -4 as output when I
print it.
if(err == ERR_OK)
netconn_write(conn, data, sizeof(data), NETCONN_NOCOPY);
netconn_close(conn);
netconn_delete(conn);
}
}
here i open a new connection and connect it to Server using its IPaddress.
Before that I wanted to check the connection whether it is connected or
not, so what i did is i assigned a variable "err" and when I try to print
it out on the terminal instrument and see the value it gives a value of
"-4".
Is this correct what I am doing here so that if i get a negative value that
means the client is successfully connected to the server.
If so how can i transfer the data "Hello World" on to my server and get it
displayed there.
Kind Regards,
Greek
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 148805On Aug 26, 6:43=A0pm, GaLaKtIkUs=99 <taileb.me...@gmail.com> wrote: > Hi, > While studying the MIG ref design for Spartan-6 I was surprised to > find a IODRP2_MCB which doesn't have any documentation. > Any information about it? > > Thanks If you have a design using the hard memory controller block, you'll find these in the FPGA editor. I can see that they are located in the IODELAY sites but contain a big box with not very illuminating pin names. It's probably another one of those stunt logic boxes that can only be used by the core generator like the IRDY and TRDY PCI pins. Regards, GaborArticle: 148806
hi all, I'm using the codes generated by the xilinx logicore tool to obtain the rocketio ip.i did it successfully.now i need to communicate between two such rocketio's. can anybody suggest me what is to be done next..... --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148807
>Hi Guys, > >Then I always read the same bytes, but these hasn't got nothing to do >with the IDCODE read initally. > >Regards, > > Do you have the bsdl file? That will give you the expected IDCODE. I suspect the value you get after loading the IDCODE instruction is correct while the first value is coming from the instruction register. When you issue an instruction you always receive something ending in 01. Do a sanity check. Reset the chip and put it in BYPASS mode. Then check to see that you can shift bits through the BYPASS register. John Eaton --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148808
I'm simulating some filter hardware in Modelsim, and need
a way to display the output with a virtual anti-alias filter.
Is there a Matlab facility for this?
plot doesn't seem to have any good option for this.
I tried interp1, and it's better than nothing, but the
highest order interpolator seems to be 4-tap ('spline').
I could do a higher order filter myself, but feel that Matlab
probably has the ideal functionality already, if I only
knew how to invoke it.
Any thoughts.
Example:
Generate a DC to Nyquist sweep
>> t = 0:0.001:1;
>> y = chirp(t, 0, 1, 500);
>> plot(y)
Looks crunchy as hell.
>> ti = 0:0.0001:1;
>> yi = interp1(t, y, ti, 'spline');
>> plot(yi)
Now looks much better, but still quite aliased towards
Nyquist (as you'd expect from a 4-tap lpf).
Thanks
Pete
Article: 148809
"Pete Fraser" <pfraser@covad.net> writes:
> I'm simulating some filter hardware in Modelsim, and need
> a way to display the output with a virtual anti-alias filter.
>
> Is there a Matlab facility for this?
> plot doesn't seem to have any good option for this.
> I tried interp1, and it's better than nothing, but the
> highest order interpolator seems to be 4-tap ('spline').
> I could do a higher order filter myself, but feel that Matlab
> probably has the ideal functionality already, if I only
> knew how to invoke it.
interp
--
Randy Yates % "She tells me that she likes me very much,
Digital Signal Labs % but when I try to touch, she makes it
mailto://yates@ieee.org % all too clear."
http://www.digitalsignallabs.com % 'Yours Truly, 2095', *Time*, ELO
Article: 148810"Randy Yates" <yates@ieee.org> wrote in message news:m3wrrbfqf5.fsf@ieee.org... > "Pete Fraser" <pfraser@covad.net> writes: >> I'm simulating some filter hardware in Modelsim, and need >> a way to display the output with a virtual anti-alias filter. >> Is there a Matlab facility for this? > interp Thanks. That seems better than interp1, but still seems weird. I can't understand their description of alpha. The width of the filter function remains the same for different values of alpha, but the severity of windowing changes.The size of the filter kernel also seems to be restricted to about 20 or under (still better than four for interp1). The worst thing about it is the DC gain seems to vary with phase. interp(y, 10, 10, 1.0) gives me unity DC gain at the original sample sites, but a gain of 0.968 at a point in the middle. Am I missing something, or is Matlab just being dumb? Thanks PeteArticle: 148811
>"Randy Yates" <yates@ieee.org> wrote in message >news:m3wrrbfqf5.fsf@ieee.org... >> "Pete Fraser" <pfraser@covad.net> writes: >>> I'm simulating some filter hardware in Modelsim, and need >>> a way to display the output with a virtual anti-alias filter. >>> Is there a Matlab facility for this? > >> interp > >Thanks. That seems better than interp1, but still seems weird. >I can't understand their description of alpha. The width of the >filter function remains the same for different values of alpha, but the >severity of windowing changes.The size of the filter kernel also >seems to be restricted to about 20 or under (still better than >four for interp1). > >The worst thing about it is the DC gain seems to vary with phase. > >interp(y, 10, 10, 1.0) gives me unity DC gain at the original >sample sites, but a gain of 0.968 at a point in the middle. >Am I missing something, or is Matlab just being dumb? > >Thanks > >Pete > Try "resample" or "upfirdn". Resample calls upfirdn using internal filter. upfirdn allows using your own filter. Kadhiem --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148812
Hi All, My design is meant to work at two speed modes(full & half rate). Initially I used one clk source(560MHz) plus enable. However, I envisage changing the plan to divide the clk itself from origin(instead of enable) so that the design is simplified and becomes identical in both cases apart from clk speed. The problem is that I have to use an FPGA on-chip PLL, which expects an input clk of 560MHz but will receive either 560 MHz in full mode or 280MHz in division mode. The PLL seem to lock in both cases. Does anybody foresee PLL problems in this approach or what else can be done to keep PLL design as recommended by Altera. Knowing that I can't switch between two PLLs. Regards Kadheim --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148813
kadhiem_ayob wrote: > Does anybody foresee PLL problems in this approach or what else can be done > to keep PLL design as recommended by Altera. Knowing that I can't switch > between two PLLs. I don't know, if it helps for your problem, but you can switch between two PLLs, at least I've used this for a Cyclone chip, so should be possible with Stratix, too. Open Megawizard and choose altclkctrl in the I/O folder. You can input customize it for two clocks and there is a checkbox for glitch-free switchover. Works nice in one of my designs. Another idea would be to use altpll_reconfig, but I don't have experience with it. -- Frank Buss, http://www.frank-buss.de piano and more: http://www.youtube.com/user/frankbussArticle: 148814
Thanks Frank However, I only have one physical clk input which carries clk signal at either 560 or 280Mhz to same PLL. One option may be to use two PLLs set one at 560 and one at 280 inputs fed by same input then mux out the outputs but I know this approach is risky at both the PLL's input side and its output side. I prefer to have one PLL and enter ref clk as 560 then "cheat" the PLL and inject 280MHz in half mode. It locks and seems happy. But I am not sure if the design will be reliable and acceptable "legally". Regards Kadhiem --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148815
On Aug 28, 1:34=A0pm, "kadhiem_ayob" <kadhiem_ayob@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: > Thanks Frank > > However, I only have one physical clk input which carries clk signal at > either 560 or 280Mhz to same PLL. > > One option may be to use two PLLs set one at 560 and one at 280 inputs fe= d > by same input then mux out the outputs but I know this approach is risky = at > both the PLL's input side and its output side. > I prefer to have one PLL and enter ref clk as 560 then "cheat" the PLL an= d > inject 280MHz in half mode. It locks and seems happy. But I am not sure i= f > the design will be reliable and acceptable "legally". > > Regards > > Kadhiem =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Look at QuartusII fitter report under PLL usage tab or something similar. They report max and min lock frequency for the reference clock. If you see that you are far off then try to play with reference clock frequency and bandwidth settings in megawithard. If it still doesn't help then the only safe option is reconfiguring the PLL on the fly. That's of course will only work when you have some other "safe" clock for reconfiguration. But then again if you have the safe clock may be it's a good idea to use it and possibly its derivate throughout your FPGA design instead of 280/560 clock? I am assuming that 280/560 clock comes from external PLL and drives some ADC or DAC and you can't use Stratix PLL for that because its jitter sucks. However it's normally very good idea to use that DAC/ADC clock in FPGA only to drive ADC/DAC samples into/out of small FIFO and base the rest of design on the other "safe" internally generated clock.Article: 148816
Pete Fraser wrote:
> I'm simulating some filter hardware in Modelsim, and need
> a way to display the output with a virtual anti-alias filter.
>
> Is there a Matlab facility for this?
> plot doesn't seem to have any good option for this.
> I tried interp1, and it's better than nothing, but the
> highest order interpolator seems to be 4-tap ('spline').
> I could do a higher order filter myself, but feel that Matlab
> probably has the ideal functionality already, if I only
> knew how to invoke it.
>
> Any thoughts.
>
> Example:
>
> Generate a DC to Nyquist sweep
>>> t = 0:0.001:1;
>>> y = chirp(t, 0, 1, 500);
>>> plot(y)
> Looks crunchy as hell.
>
>>> ti = 0:0.0001:1;
>>> yi = interp1(t, y, ti, 'spline');
>>> plot(yi)
> Now looks much better, but still quite aliased towards
> Nyquist (as you'd expect from a 4-tap lpf).
>
> Thanks
>
> Pete
>
>
Pete,
I'm not clear on all that but if you change to this:
t = 0:0.001:1;
y = chirp(t, 0, 1, 50);
plot(y)
Then the plot looks fine if it meets your definition of "fine".
The only problem I see is the the higher frequencies are undersampled
(in a "plotting" sense) - and you did mention aliasing so I expect
that's what you meant.
Just to check:
The sample rate appears to be 1000Hz and the interval is 1msec of course.
The highest frequency is 500Hz so there would be 2 samples per cycle at
the highest frequency which meets the Nyquist criterion except at 500Hz.
But, for practical purposes, it doesn't reach 500Hz anyway.
That would all be OK except that the bandwidth is higher than 500Hz due
to the frequency modulation. So, I'm not entirely sure just what
"Nyquist" is here. One could figure it out easily enough but I'm lazy
so I did this:
fy=fft(y)
mfy=abs(fy)
plot(1:1001,mfy)
The result is pretty revealing and suggests that the waveform is quite
undersampled as there are very high values around fs/2.
x axis from 900 to 1000 you can see the "intermodulation" effects of
the sampling - which is what makes the original plot look weird.
I'm not sure that helps because I've not addressed the lpf questions.
Were you intending to LPF and then plot? You're still going to get the
intermodulation effects up around 500Hz. I tried it with a simple [1 1]
filter with a zero at 500Hz and it was still evident.
I hope this helps some....
Fred
Article: 148817
On Aug 28, 1:40=A0am, "Pete Fraser" <pfra...@covad.net> wrote:
> I'm simulating some filter hardware in Modelsim, and need
> a way to display the output with a virtual anti-alias filter.
>
> Is there a Matlab facility for this?
> plot doesn't seem to have any good option for this.
> I tried interp1, and it's better than nothing, but the
> highest order interpolator seems to be 4-tap ('spline').
> I could do a higher order filter myself, but feel that Matlab
> probably has the ideal functionality already, if I only
> knew how to invoke it.
>
> Any thoughts.
Last time I needed to do this, I remember having had modelsim doing
the whole thing there. I used to do this:
- define an output real signal in VHDL
- write a conversion function from two's complement to floating point
in VHDL, this would give you a real signal in modelsim
- as far as I remember, you can define an 'analog' signal to plot in
modelsim and it comes with an interpolation option
Hope this helps.
-Momo
Article: 148818
"Fred Marshall" <fmarshall_xremove_the_xs@xacm.org> wrote in message
news:queeo.81896$PY3.39434@en-nntp-05.dc1.easynews.com...
> I'm not clear on all that but if you change to this:
> t = 0:0.001:1;
> y = chirp(t, 0, 1, 50);
> plot(y)
>
> Then the plot looks fine if it meets your definition of "fine".
It does.
> The only problem I see is the the higher frequencies are undersampled (in
> a "plotting" sense) - and you did mention aliasing so I expect that's
> what you meant.
Correct. I can't just look at a waveform and tell
if my simulated filter hardware is behaving correctly.
> Just to check:
> The sample rate appears to be 1000Hz and the interval is 1msec of course.
> The highest frequency is 500Hz so there would be 2 samples per cycle at
> the highest frequency which meets the Nyquist criterion except at 500Hz.
Correct (although I don't care about units). It's just sample inputs
to Modelsim.
> But, for practical purposes, it doesn't reach 500Hz anyway.
Close enough.
> That would all be OK except that the bandwidth is higher than 500Hz due to
> the frequency modulation. So, I'm not entirely sure just what "Nyquist"
> is here. One could figure it out easily enough but I'm lazy so I did
> this:
>
> fy=fft(y)
> mfy=abs(fy)
> plot(1:1001,mfy)
>
> The result is pretty revealing and suggests that the waveform is quite
> undersampled as there are very high values around fs/2.
>
>
> x axis from 900 to 1000 you can see the "intermodulation" effects of the
> sampling - which is what makes the original plot look weird.
Could be. I was being sloppy and ignoring the FM aspect.
> I'm not sure that helps because I've not addressed the lpf questions. Were
> you intending to LPF and then plot? You're still going to get the
> intermodulation effects up around 500Hz. I tried it with a simple [1 1]
> filter with a zero at 500Hz and it was still evident.
I was intending to do a filtered upconversion, then plot.
I first hoped that plot would have an option for this, but no luck.
I then tried interp1, which does some of what I was looking for,
but is restricted to a 4-tap filter ('spline' method), and so is still
visually aliased.
I then tried interp, which allows higher order filters, but has some
very weird behaviour. The various polyphase coefficient sets have DC
gains that are not unity, so if you up-convert DC you get a weird scallop
effect. Either I or Mathworks is suffering from a serious absence of grasp.
Then I discovered resample and upfirdn (thanks Kadhiem).
They seem to do pretty much what I was hoping for.
> I hope this helps some....
Thanks Fred.
Pete
Article: 148819"kadhiem_ayob" <kadhiem_ayob@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote in message news:sv2dndPiufvWfuXRnZ2dnUVZ_jidnZ2d@giganews.com... > Try "resample" or "upfirdn". Resample calls upfirdn using internal filter. > upfirdn allows using your own filter. Thanks. That's pretty much what I was hoping for. PeteArticle: 148820
"Manny" <mloulah@hotmail.com> wrote in message news:7b13d9e3-7c30-4ca1-ab02-5d994c77b24c@i13g2000yqe.googlegroups.com... > - as far as I remember, you can define an 'analog' signal to plot in > modelsim and it comes with an interpolation option That's where this whole thing started. The Modelsim interpolation option is not good, and you can't really use it to evaluate analog waveforms that are above fs/4. Matlab's 'resample' followed by 'plot' does a much better job. Thanks PeteArticle: 148821
On Aug 29, 3:28=A0am, "Pete Fraser" <pfra...@covad.net> wrote: > That's where this whole thing started. > The Modelsim interpolation option is not good, and you can't > really use it to evaluate analog waveforms that are above fs/4. Never needed more than this as my signals are usually well oversampled. Alternatively, you can write your own custom interpolation function in VHDL. Since it's purely for simulation, it's as easy as writing in any procedural language. > Matlab's 'resample' followed by 'plot' does a much better job. Again not sure, but if your signal is bandpass, resample may be useless here, or not? -MomoArticle: 148822
On Aug 29, 6:06=A0am, Manny <mlou...@hotmail.com> wrote: > Again not sure, but if your signal is bandpass, resample may be > useless here, or not? That is, bandpass and *broadband*. -MomoArticle: 148823
resample works irrespective of signal bandwidth(0~.5Fs).it's only limitation is that it does not support very large vectors. Incidentally I also use it for fractional delay modelling e.g. for ADC clk edge variation; upsample by 100 for example then manually downsample from a chosen sample: y1 = resample(x,100,1); y2 = y1(26:100:end); % 0.26 fractional delay Kadhiem --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148824
Hello everyone, We are building a board in which we propose to design the FPGA interface to a DAC in the following manner. Please give feedback whether such an approach is feasible. Functionality: Among other things, the board contains three components: ADC, DAC and FPGA (XC3SD1800A, Spartan 3ADSP 1.8 million gates). The ADC & DAC are connected to the FPGA. The ADC, DAC and FPGA are all clocked at 250 MHz from an external clock source. To test whether ADC, DAC & FPGA are working fine, we propose to use the FPGA as a pipe from the ADC to the DAC. In this way, the output of the DAC should resemble the analog input. The question is this: Assuming the clock is routed on the PCB such that there is no phase delay between the ADC, DAC and the FPGA, can the data output by the FPGA be delayed by say half a clock cycle in order to satisfy the setup & hold consideration of the DAC. The trouble is we cannot use a DCM to phase-delay the clock inside the FPGA because the jitter- performance of the DCM is very poor compared to the input clock. Instead, can we use timing contraints to achieve the phase delay ? Thanks, Sharath
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