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>Best thing to do is contact through the general email boardsales AT >enterpoint DOT co DOT uk. Either myself or one of my team can answer >questions there. > >John Adair >Enterpoint Ltd. Thank you, just sent a e-mail. My name is Luis Filipe Rossi for reference. Cya --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148776
Stef <stef33d@yahooI-N-V-A-L-I-D.com.invalid> wrote: >In comp.arch.fpga, >Morten Leikvoll <mleikvol@yahoo.nospam> wrote: >> "Fredxx" <fredxx@spam.com> wrote in message >> news:i4jh01$ukp$1@news.eternal-september.org... >>> This is for a niche market, though any market has competitors who can play >>> informer to the authorities. >> >> I would not worry (I used to worry too). The authorities has a lot more >> important work to do than chasing low qty products that has a tiny bit more >> radiation than the papers allow. > >They may not actively chase for such products, but when a complaint is >made (by, for example, that competitor) they will have to follow that up. >And although it may not happen very often, I have seen it happen, twice. > >And how do you know you're only 'a tiny bit' over the limits without >actually measuring your device? Take a simple oscillator chip and >connect it to the 'wrong' trace, emissions will go through the roof. > >There is no requirement to actually do measurements, you just have to be >under the limits. How you make sure you are, is up to you. If you can >calculate and simulate everything, that may be enough proof you honestly >believe that your device is under the limits. I have not seen that happen, >just measuring is usually simpler. > >And even good measurements are not a complete guarantee your device is >always under the limits. These measurements are just scans through the >required frequency range. And if your device produces short burst, they >may be missed in those scans. But at least you have evidence that you >did all you could to make sure your device is under the limits. The tests are well specified. The measured values are averages, not peak values. It often helps to use a spread-spectrum oscillator so the peak is smeared out over a wider band. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 148777
Hi folks, my team here at Xilinx just published a new issue of Xcell Journal: http://www.xilinx.com/publications/xcellonline/index.htm. This issue has some great tutorial and how-to articles. Check out Austin Lesea's tutorial on timing constraints on page 46. The issue also includes features on the new 7 Series and Virtex-5QV rad-hard FPGA. Also, if you would like to contribute to Xcell, just shoot me an email at xcell(at)xilinx.com Cheers, Mike SantariniArticle: 148778
On 18 Aug, 17:11, "Fredxx" <fre...@spam.com> wrote: > I have a small electronic unit which needs some CE compliance testing. > > Cost is a major issue and was wondering if anyone here can offer advice on > an affordable solution. Where I used to work they hire the testing facility for half a day, and do their own initial testing. They then fix any problems and the product usually passes the formal tests without any problems.Article: 148779
Have a look at our Craignell1 http://www.enterpoint.co.uk/component_replace= ments/craignell.html and Craignell2 http://www.enterpoint.co.uk/component_replacements/craignell= 2.html modules. We have various processor IPs running in these. Otherwise lots more choice in our range so if these are not what you want have a brouse. John Adair Enterpoint Ltd. On 17 Aug, 16:08, stevem1 <steve.martind...@gmail.com> wrote: > I have a custom 8051 RTL core that I want to put into a CPLD > on a development board. > > I also need an external Flash/EEProm memory on the same > CPLD development board to run 8051 code from. > > Are there any CPLD EVM/development boards that come with > an 8 bit with Flash/EEProm ? > > If not I, I will have to attach a socket(for the EEProm), to an > existing > CPLD board. > > =A0 thanks, > =A0 =A0 =A0-steveArticle: 148780
In comp.arch.fpga, Nico Coesel <nico@puntnl.niks> wrote: > Stef <stef33d@yahooI-N-V-A-L-I-D.com.invalid> wrote: >> >>And even good measurements are not a complete guarantee your device is >>always under the limits. These measurements are just scans through the >>required frequency range. And if your device produces short burst, they >>may be missed in those scans. But at least you have evidence that you >>did all you could to make sure your device is under the limits. > > The tests are well specified. The measured values are averages, not > peak values. It often helps to use a spread-spectrum oscillator so the > peak is smeared out over a wider band. No, not averages, but quasi-peak. But that measurement is a scan of the required frequency range, a measurement receiver can not monitor the entire band simultaniously. So if your device emits bursts of, lets say, 0.1 seconds every few seconds, there is a possibility they will be missed in the measurement. And next time you measure that same device, it may just pop up as an unpleasant surprise. The (well known) place where we do most of our measurements actually does a very quick (under half an hour) peak scan and after that just measures the ten or so highest peaks with the required quasi-peak detector. Doing the entire scan with quasi-peak would take hours. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) Peace is much more precious than a piece of land... let there be no more wars. -- Mohammed Anwar Sadat, 1918-1981Article: 148781
Hi, I am really looking for some help in how to write code for my FPGA board for implementing a TCP Client using lwIP API using the commands like netconn_connect() and so on. I found some documentation on how to build a TCP server but I could not find any help for TCP client. Any help regarding on how to build a client would be great. If any body has an idea regarding one of teh three topics which i have mentioned below, then that would be helping me a lot: 1)I am looking for some basic explanation like what are the steps i need to consider to write a client code from scratch. 2)or a sample code which shows the basic implementation of TCP client using lwIP API 3)or what changes should I need to make in the server program so that it can run as a client Kind Regards, Mahee --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148782
On 2010-08-19, Symon <symon_brewer@hotmail.com> wrote: > I have no idea if this is appropriate to your situation, but you might > avoid a lot of the CE compliance issues by using a wall-wart or somesuch > which is already CE marked. Then all the mains powered stuff is > pre-certified by someone else. Get one with a ferrite thingy near the DC > jack! For Safety, Yes - EMC, not necessarily. I just had a case where a product with a wall-wart was above the allowed conducted emissions on the mains, with the cause being in the product, not the wall-wart. Adding common-mode filtering fixed that, so a ferrite in the DC cable might have been sufficient. cu MichaelArticle: 148783
The easiest way I found for that, is to use the socket API.
The CONNECT code looks similar to this:
struct sockaddr_in sServer;
sServer.sin_len = sizeof(struct sockaddr_in);
sServer.sin_family = AF_INET;
sServer.sin_port = MY_PORT_NUMBER;
inet_aton("123.45.123.45", &(sServer.sin_addr));
memset(&(sServer.sin_zero), 0, sizeof(sServer.sin_zero));
int nSocket = lwip_socket(AF_INET, SOCK_STREAM, IPPROTO_TCP);
if (nSocket < 0) {
printf("lwip_socket() returned -%d\r\n", -nSocket);
return;
}
printf("Connecting to server\r\n");
int nErr = lwip_connect(nSocket, (struct sockaddr*)(&sServer),
sizeof(sServer));
if (nErr < 0) {
printf("lwip_connect() returned -%d, errno=%d\r\n", -nErr,
lwip_get_err(nSocket));
return;
}
After that, you can use lwip_send() and lwip_recv() for data
transmission.
Best regards
Article: 148784Hi all, I am working on text Huffman Encoder and Decoder to be implemented on FPGA. and here are things which are not clear for me. 1.Will the binary tree be constructed by software and then the coded data be taken and VHDL coded OR can I construct the Binary tree using VHDL? and I need some hint. kude --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148785
I am using the DCM of the Virtex 4VSX35 to make the 100MHz pulse from the 50MHz but results are not satisfactory instead of having (1010) from the resultant pulse i am getting (1xx0) can anybody tell me how to get my desired result. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148786
The article on Metastability and its mitigation looks a good primer for those who are not already aware of this important topic. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148787
On 24/08/2010 13:39, kude wrote: > Hi all, > I am working on text Huffman Encoder and Decoder to be implemented on > FPGA. > and here are things which are not clear for me. > 1.Will the binary tree be constructed by software and then the coded data > be taken and VHDL coded OR can I construct the Binary tree using VHDL? and > I need some hint. > That's up to you. If you construct the tree in software and generate the VHDL from a fixed tree, the hardware will be a lot easier. But then you have a fixed tree - it will only be efficient for encoding data that matches that tree.Article: 148788
hi all, I've been helping out a small amateur team who, for reasons that don't concern us here, need to get hold of a few ancient QuickLogic FPGA devices. They have already been cheated by at least two obsolete-part merchants who supplied devices that have already been programmed - not terribly useful, given that these are fuse-programmable parts. Welcome to the charming and honorable world of obsolete parts supply! Does anyone have some unused QL12x16B, or the equivalent Cypress CY7C383A, devices that they could part with? Any speed grade is OK, but the parts MUST be 68-pin PLCCs and (obviously) MUST be virgin un-programmed devices. Happy to pay reasonable shipping costs and a modest honorarium, but we're not interested in paying shark prices for suspect parts. Even two or three devices would be welcome; six or eight would be magical. Before anyone asks: yes, we DO know that we can do this with more modern devices, but as so often there are many other constraints that make this unreasonably troublesome. Feel free to respond here, or by email to jonathan at oxfordbromley dot plus dot com. Thanks in advance --- Jonathan BromleyArticle: 148789
Hi everyone, I'm currently using a design with a 5 /4 interpolation Filter used to convert a signal sampled @ 80 MHz to 100 MHz. The Interpolation filter is designed using FIR compiler 3.2 (ISE 10) and implemented on a Virtex 5 FPGA. The problem is present in simulation too. For this purpose we have used a 33-tap filter. The filter works well however there is an implementation difference between Matlab and the Xilinx core. I used a step response to characterize both systems and I obtain slightly different results. There is a slight phase delay between the Matlab implementation (with upfirdn function) and the interpolation FIR filter compiled with FIR Compiler 3.2. I have run some tests to understand better the problem and it seems to be related with the decimation process. Let me explain : Assuming X : original signal sampled @ 80 MHz X_up : signal stuffed with 4 zeros for every sample @ 400 MHz (only used for explanation purposes) Y : X_up filtered by our 33-tap FIR filter @ 400 MHz Z : Decimated version of Y Signal @ 100 MHz X = X0, X1, X2, X3,... Xn, ... Xm,... The complete resampling process would look like this X_up = X0,0,0,0,X1,0,0,0,0,X2,0,0,0,0,X3,0,0,0,0,X4,0,0,0,0,....,Xn, 0,0,0,0,.... Then X_up is filtered by the FIR filter to obtain the "Y signal". Y = Y0, Y1, Y2, Y3, Y4,, Y5, Y6, Y7, Y8 .... @ 400 MHz By decimating by 4, we take only 1 sample out of 4. However it seems that Matlab and Xilinx do not take the same sample In Matlab, with the upfirdn function, I obtain the following results Z_matlab = Y0, Y4, Y8, Y12, ... @ 100 MHz Z_xilinx = Y1, Y5, Y9, Y13,... @ 100 MHz. Basically, the Xilinx output signal is shifted by one sample @ 400 MHz, or one quarter of a sample @ 100 MHz. Am I the only one that got this problem? Is there a way to control the decimation process by selecting which sample out of N is selected? This is an important issue since the decimation process influences the phase of the signal. I am also aware that with the polyphase implementation, the implementation does not compute all samples in the Y sequence @ 400 MHz, I only added these intermediate signals to be clearer. Thanks Benjamin CouillardArticle: 148790
Very old hat... http://www.xilinx.com/support/documentation/application_notes/xapp616.pdf --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148791
>On 24/08/2010 13:39, kude wrote: >> Hi all, >> I am working on text Huffman Encoder and Decoder to be implemented on >> FPGA. >> and here are things which are not clear for me. >> 1.Will the binary tree be constructed by software and then the coded data >> be taken and VHDL coded OR can I construct the Binary tree using VHDL? and >> I need some hint. >> > >That's up to you. If you construct the tree in software and generate >the VHDL from a fixed tree, the hardware will be a lot easier. But then >you have a fixed tree - it will only be efficient for encoding data that >matches that tree. > @David Brown,ok but what if I want to construct the tree using the VHDL,where shall I start? And what logic units will I need ? thanks --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148792
On 08/24/2010 09:03 AM, kude wrote: >> On 24/08/2010 13:39, kude wrote: >>> Hi all, >>> I am working on text Huffman Encoder and Decoder to be implemented on >>> FPGA. >>> and here are things which are not clear for me. >>> 1.Will the binary tree be constructed by software and then the coded > data >>> be taken and VHDL coded OR can I construct the Binary tree using VHDL? > and >>> I need some hint. >>> >> >> That's up to you. If you construct the tree in software and generate >> the VHDL from a fixed tree, the hardware will be a lot easier. But then >> you have a fixed tree - it will only be efficient for encoding data that >> matches that tree. >> > > @David Brown,ok but what if I want to construct the tree using the > VHDL,where shall I start? http://www.altavista.com/web/results?fr=altavista&itag=ody&q=Huffman+Encoding&kgs=0&kls=0 > And what logic units will I need ? Who knows? Finish your project and you can tell us. If you're lucky there's a book out there on implementing data compression in logic; I suspect, however, that what there is are a lot of very specific, narrowly focused materials on specific methods (i.e. "Implementing Video Compression in Digital Hardware"). And that's if you're lucky -- if you're not lucky then there are 10 companies out there that have each learned how to do it, and no one wants to tell anyone else how it's done. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 148793
kude <tadmas09@n_o_s_p_a_m.gmail.com> wrote: > I am working on text Huffman Encoder and Decoder to be > implemented on FPGA. I recommend looking at the literature on systolic arrays. I am not so sure, but I believe that works well for many compression algorithms. Remember that you are building hardware, and the size must be specified before synthesis. You can't do dynamic allocation as in many programming languages. -- glenArticle: 148794
Hi, After seeing a number of customers struggling with this issue, I have written a detailed ApNote showing how to implement a multiple configuration system for Altera FPGAs. The example is a Cyclone III using Active Serial mode / EPCS (on a DE0 board), but it is easily translatable to any other Altera FPGA/board. It is not complex, but getting everything right from the documentation is not absolutely obvious. The ApNote and the design files are available at the top of the list at: http://www.alse-fr.com/apnotes.php Anyone spotting a discrepancy, please let me know. Hope this helps, Bert.Article: 148795
On 24 Aug, 16:20, Benjamin Couillard <benjamin.couill...@gmail.com> wrote: > Hi everyone, > > I'm currently using a design with a 5 /4 interpolation Filter used to > convert a signal sampled @ 80 MHz to 100 MHz. The Interpolation filter > is designed using FIR compiler 3.2 (ISE 10) and implemented on a > Virtex 5 FPGA. The problem is present in simulation too. > > For this purpose we have used a 33-tap filter. The filter works well > however there is an implementation difference between Matlab and the > Xilinx core. I used a step response to characterize both systems and I > obtain slightly different results. There is a slight phase delay > between the Matlab implementation (with upfirdn function) and the > interpolation FIR filter compiled with FIR Compiler 3.2. > > I have run some tests to understand better the problem and it seems to > be related with the decimation process. Let me explain : > > Assuming > > X : original signal sampled @ 80 MHz > > X_up : signal stuffed with 4 zeros for every sample @ 400 MHz (only > used for explanation purposes) > > Y : X_up filtered by our 33-tap FIR filter @ 400 MHz > > Z : Decimated version of Y Signal @ 100 MHz > > X = X0, X1, X2, X3,... Xn, ... Xm,... > > The complete resampling process would look like this > > X_up = X0,0,0,0,X1,0,0,0,0,X2,0,0,0,0,X3,0,0,0,0,X4,0,0,0,0,....,Xn, > 0,0,0,0,.... > > Then X_up is filtered by the FIR filter to obtain the "Y signal". > > Y = Y0, Y1, Y2, Y3, Y4,, Y5, Y6, Y7, Y8 .... @ 400 MHz > > By decimating by 4, we take only 1 sample out of 4. However it seems > that Matlab and Xilinx do not take the same sample > > In Matlab, with the upfirdn function, I obtain the following results > > Z_matlab = Y0, Y4, Y8, Y12, ... @ 100 MHz > > Z_xilinx = Y1, Y5, Y9, Y13,... @ 100 MHz. > > Basically, the Xilinx output signal is shifted by one sample @ 400 > MHz, or one quarter of a sample @ 100 MHz. Am I the only one that got > this problem? Is there a way to control the decimation process by > selecting which sample out of N is selected? This is an important > issue since the decimation process influences the phase of the signal. > > I am also aware that with the polyphase implementation, the > implementation does not compute all samples in the Y sequence @ 400 > MHz, I only added these intermediate signals to be clearer. > > Thanks > > Benjamin Couillard You have my sympathy, it's not easy dealing with undocumented or "optimized" features. Getting the correct output phase from polyphase filters are usually not covered in text books. Let's assume the filter consists of five banks of coefficients, controlled by an modulo-5 commutator, which is incremented in steps of 4. Each time the commutator rolls over we clock in a new input sample. To explain what you see we must assume the commutator starts with the value 1 (and not 0 as it should). So we have Five polyphases: H0, H1, H2, H3, H4 H0 = h[0], h[5] ... H1 = h[1], h[6] ... H2 = h[2], h[7] ... etc Normally h[0]*x[0] is the first output from a filter. If I understand correctly your first output is h[1]*x[0] = y[1] You need: x[n], n: 0012344567889 H_ix: 0432104321043 ; starting in H0: y[0], y[4], y[8] etc You have: x[n], n: 0112345567899 H_ix: 1043210432104 ; starting in H1: y[1], y[5], y[9] etc Fix/suggestion: insert 1 zero sample, "*", and skip its output y[*]. x[n], n: *001234456788 H_ix: 1043210432104 ; starting in H1: y[*], y[0], y[4], etc The dummy sample will align/sync the commutator to the y[0]-sequence. Best rgdsArticle: 148796
> After seeing a number of customers struggling with this issue, I have written a detailed ApNote > showing how to implement a multiple configuration system for Altera FPGAs. Thanks for this Bert, I have to get remote-update / multiple configuration operating on a Startan III board immenently so this is very useful. One thing, when I skimmed your post I presumed you were talking about configuring multiple devices from one flash chip, not multiple images for one device. Nial.Article: 148797
> Anyone spotting a discrepancy, please let me know. Bert, there's only one page in the PDF (numbering shows 1 of 9) ! Nial.Article: 148798
> Bert, there's only one page in the PDF (numbering shows 1 of 9) ! ...and as he's just pointed out by email there's a link to the whole thing at the bottom. Nial.Article: 148799
Dans son message précédent, Bert_Paris a écrit : > for Altera FPGAs. I don't assume it's going to be useful for Xilinx (or Actel or Lattice) users, since most of the work is about undesrtanding how to use the *Altera* Megafunction named "altremote_update"... Bert
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