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On Sep 27, 2:39=A0pm, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > Nico Coesel <n...@puntnl.niks> wrote: > > "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote: > > Sorry, but this sounds like a load of crap to me. The S3E is a > > perfectly useful chip. Although the pin configuration is more limited > > that the standard S3 parts. You seem obsessed with flash. FYI none of > > the designs I ever worked on used flash to store the FPGA > > configuration. Flash isn't a big deal for everyone. > > But the 2.5 Volt-only JTAG is a PITA... Bingo! Another thing is that S3E appears to be available in more packages than S3A so you might be able to find a better fit for a particular design. -aArticle: 143251
On Sep 28, 6:45=A0pm, rickman <gnu...@gmail.com> wrote: > On Sep 28, 8:23=A0am, "Antti.Luk...@googlemail.com" > > > > <antti.luk...@googlemail.com> wrote: > > > Do people ever use archived news and get angry about unrelated quote = meaning > > > unrelated search hits? > > > > > Why a two layer board? =A0I would expect any decent design to use a= t > > > > least four layers just so it can have a ground/power plane for nois= e > > > > reduction. =A0Especially when you don't know what someone will be d= oing > > > > with it, best is to provide a bit of overkill. =A0I'm not intereste= d in > > > > saving every last penny on a development board like this. > > > > With programmable pin helping the layouter to get a planar layout, th= e > > > bottom layer can be made quite a continous groundplane. > > > > .. > > > > Bye > > > -- > > > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu= -darmstadt.de > > > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- > > > please complain to the GOOGLE (and saying that use something > > else isnt an option always, sorry... I use what is the easiest way) > > when replying using google news its not easy to delete the rubish > > as it not even seen on screen > > > well, i see the thread is reached status where people start to > > complain > > about quoting issues, :( > > If you are using Google Groups, I hope you are clicking the spam and > reporting it. =A0Google seems to continue to make this easier. =A0The las= t > time I noticed, you had to open the "opions" and click "report the > message", then type at least "spam" into the edit box. =A0Now I see that > there is a link at the bottom of the post where you can just click > once. =A0It even confirms that the report has been accepted! > > How much easier can it get? > > Rick I do report all spam messages, if you wanted to know that AnttiArticle: 143252
if Xilinx RTL view shows 2 input logic gate (OR2B1) with BOTH input connected to same input signal, ist that what? problem with synthesis? OR2B1 with both input connected is same as ALWAYS 1 but the signal that comes to the OR2B1 is required in the logic behing the OR2B1 from the RTL view i see that one required signal is going to be optimized away during implementation stage. maybe it goes some other path and RTL is still correct, still a 2 input gate in RTL wired so that it has constant 1 at output seems a potential problem? AnttiArticle: 143253
Hi, Xilinx EDK 9.2i. A custom ip generates interrupts to Microblaze system. Another custom ip generates periodic timer interrupts. Interrupt controller misses no interrupt from the timer, but fails to capture about 10 percent of the interrupts from other custom ip. I placed a counter at the point where the interrupt signal is sent to processor to make sure that it actualy happens. Counter perfectly scores but I am not able to receive 10% of the interrupts in processor side. I am beginning to think that xps interrupt controller has a bug. But then how come it captures all timer interrupts? I checked if the interrupt signal goes back to low after it is raised, and has no problem there. It is fairly slow compared to processor plb bus clock too. I also switched priorities of two interrupts with no effect. Has anyone seen such a "funny" behavior with xps interrupt controller? Thanks for reading this.Article: 143254
> Cool. Can it execute from SPI FLASH memory 1/2/4 bits wide ? The load/store interface expects 32-bit words, so it would require some modification to deal with an interface of any other width. I certainly haven't tested it with an SPI interface of any kind. > So you are saying this is in the 10-20mips region ? I wish. The processor's CPI on the benchmark suite is 73.94, putting the MIPS value between 1.77 and 2.32 based on the clock frequencies I gave you. > How does the power consumption compare, with a NIOS clock-reduced/ > gated to give the same appx MIPs ? I'll have to get back to you on that, since I haven't done any power testing on it yet.Article: 143255
On Sep 29, 3:40=A0am, rickman <gnu...@gmail.com> wrote: > Yes, that is true, but not my point. =A0A single ground plane does > nothing to reduce noise on the power rails. =A0The capacitor that is > formed by parallel planes spaced 10 mil in a PWB is the best power > supply decoupling device you can provide. =A0Even on a very small board, > these planes provide significant noise elimination, both in terms of > minimizing the effect on the chips and also in terms of reducing > EMI. > > I realize that many designs just don't have a need for this, but my > point was that a general purpose development/eval board needs to > consider a wide range of designs including ones that push the speed of > the device and have a number of outputs switching at high edge rates. > Capacitors alone will not normally address the problem adequately in > these cases. I'd generally agree - a demoboard such as this, should not be a 'minefield for the unwary', but the design itself should be paste-able into someone's project. (unless it is some highly specific FPGA subset, that only uses half a dozen IOs, but that's a different type of demoboard... ) A better place to drive the PCB cost down, is simply to reduce the area. -jgArticle: 143256
Antti wrote:
> if Xilinx RTL view shows 2 input logic gate (OR2B1)
> with BOTH input connected to same input signal, ist that what?
> problem with synthesis?
Unlikely.
I expect that the logic is correct.
The RTL view is just the starting point.
A full synthesis will do many reductions.
-- Mike Treseler
Article: 143257Mike NG: I was only vaguely aware of the adruino toolchain being open and its ease of use, having such a large following and many are hobbyists. Much work needs to be done on this front, but is not a show stopper. I did a quick search for VHDL compilers and found some open license programs, not sure how they work? OpenCores.org maybe a source for looking into. It does seem that the ability of Xilinx toolset is useful and not altogether useless in this particular endeavor. I like the way it has been utilized in other projects as calls to particular programming to put together a bin or bit or xsvf or other files of need within a dos type command window and utilizing batch files to do it all. I think this would be an easy transition for a Linux, or unix user. The board house that put these together is overseasales@qdcircuits.net. Nico, I think the suggestion by you and others is valid and requires some time and energy to make the JTAG chain within the USB communication a reality, FT2232R. Antti, Still harping on the antiquated chip thing, dang. I mentioned that this revolution of the design was for ease of build I had some S3E's and wanted to use them in some design, I did they are consumed. The thing about it is I can see that much of the support circuitry is up and running putting an S6, with multiboot, in here would be possible and would come up the first time I built it, support circuitry, programming, power, and communication, is working. In fact trying to get some less than 10 chips of the newly offered S6 with giga transceivers. I really appreciate the CPLD and will try and get it into the jtag chain with the FT2232. I like the bus like ability of driving I/O into or out of any pin on the FPGA, build a mux. So much of the I/O is hung on the CPLD, this is akin to the muxes building many peripheries buses with only the available I/O's on small MCUs. Sending out a programmed CPLD for a project is also possible, therefore a programmable out of the box board solution. Like the CPLD. Just add power and it is doing the processing I have programmed in it. Nothing is set in stone, in fact it is all ones and zeros, the ability to change anything is possible and likely. Uwe Bonnes, I am not sure of the difficulty of the 2.5V vref on the jtag, but would sure like to hear about the details. I am utilizing a ltc3455 four voltage output switching regulator which requires astonishingly little support circuitry for a 1.2V, 1.8V, 2.5V and 3.3V at the usb rating of ~ 2.5W. JG You asked the question of cheap communication for both programmming and runtime information at an acceptable bandwidth not to mention the power over usb. FTDI has been successful in this design and will be looking at the FT2232 for all its communication protocols, jtag being one of the most useful in this design. Another affordable option is Ethernet and power over ethernet, which I have a design, but requires about twice the funds to run prototype testing. Ethernet is a grand solution with so much hanging on the internet, oh the possibilities. All, I thank you for your rich comments and ideas all have been more than my expectations. I will be looking at many of them for another run at at a better solution to my problem, because nothing is set in stone and a change only requires some time, some thought, and some more of my bad calculations. As for the discussion on the four layer board its ability in many ways is worth the effort and cost. The complexity of the design of the four layer board is hardly passed onto any subsequent users, parts are still soldered onto the top or bottom not on on the inner layers. Antti, you are still correct nobody still is interested in this board so I think for now I will make it whisper BT for some marketing and fun. Sincerely, Cy Drollinger Electronic Realization L.L.C. cy@montana.net PH: 406-586-5502 www.elec-real.comArticle: 143258
On Sep 29, 10:35=A0am, nobody <cydrollin...@gmail.com> wrote: > JG > > You asked the question of cheap communication for both programmming > and runtime information at an acceptable bandwidth not to mention the > power over usb. FTDI has been successful in this design and will be > looking at the FT2232 for all its communication protocols, jtag being > one of the most useful in this design. Just to clarify, I was talking of their new FT2232H, which has high speed USB. There was a thread some weeks ago on cae, about the sustainable data rate (no breaks/fixed tick-rate) on a 2232H, and I'm not sure what the final answer was. 2232H has larger buffers, and higher peak speeds, so the sustainable number has to be higher ? -jgArticle: 143259
On Sep 29, 1:26=A0am, Mike Treseler <mtrese...@gmail.com> wrote: > Antti wrote: > > if Xilinx RTL view shows 2 input logic gate (OR2B1) > > with BOTH input connected to same input signal, ist that what? > > problem with synthesis? > > Unlikely. > I expect that the logic is correct. > The RTL view is just the starting point. > A full synthesis will do many reductions. > > =A0 =A0 =A0 -- Mike Treseler yes sure it was just confusing as the signal "optimized to 1" is needed in the logic and i was not able to find where the optimized signal was actually used the problem is found, and it well it close to that place but not releted to the weird looking gate in rtl view AnttiArticle: 143260
On Sep 29, 1:57=A0am, -jg <jim.granvi...@gmail.com> wrote: > On Sep 29, 10:35=A0am, nobody <cydrollin...@gmail.com> wrote: > > > JG > > > You asked the question of cheap communication for both programmming > > and runtime information at an acceptable bandwidth not to mention the > > power over usb. FTDI has been successful in this design and will be > > looking at the FT2232 for all its communication protocols, jtag being > > one of the most useful in this design. > > Just to clarify, I was talking of their new FT2232H, which has > high speed USB. > There was a thread some weeks ago on cae, about the sustainable > data rate (no breaks/fixed tick-rate) on a 2232H, and I'm not sure > what the final answer was. 2232H has larger buffers, and higher peak > speeds, so the sustainable number has to be higher ? > > -jg FTDI has claimed so 20MByte this is more then 2 times less than with cypress FX2 AnttiArticle: 143261
On Sep 28, 10:00=A0am, Andy Peters <goo...@latke.net> wrote: > Another thing is that S3E appears to be available in more packages > than S3A so you might be able to find a better fit for a particular > design. That's my principle objection to the S3A family. I buy my parts from Digi-Key, and the only non-BGA packages for S3A are the 50K devices. I have fairly limited assembly resources so BGA / QFN parts aren't possible, but I want larger devices. What to do? EricArticle: 143262
On Sep 28, 6:13=A0am, Dek <daniele.deq...@gmail.com> wrote: > On 28 Set, 11:27, Martin Thompson <martin.j.thomp...@trw.com> wrote: > > > > > Dek <daniele.deq...@gmail.com> writes: > > > Hi all, > > > > I'm new to this group and I'd like to ask you some help with my > > > design. Actually I'm testing a double median filter implemented in a > > > Virtex5 FPGA. To chek it in different situation I tought to use an > > > ChipScope Pro ILA core to store a set of data (32 x 10 x 1024 bit) an= d > > > use them as stimuli for my device, finally storing the output (32 x 1 > > > x 1024bit) in another ILA core. The data I'd like to use for this tes= t > > > are stored in .txt files. The point is: > > > > 1) Is it possible to pass data from a .txt file to a ILA core? > > > 2) If so, can you suggest me how to do that? > > > When you say you're testing using ILA - have you tested on a simulator > > first? =A0You'll be vastly more productive there while developing the c= ode, > > as compiles are much quicker and you can probe all the signals you want= . > > > If you *have* done this and want to test it in the real hardware as > > well, then you might be able to wire up a VIO interface and control it > > from a TCL script to send data into your core (slowly) and use the ILA > > to capture the output. > > > But, unless you think something is actually wrong with the synthesis, m= y > > experience is that testing hardware in that way is not very valuable. > > > Cheers, > > Martin > > > -- > > martin.j.thomp...@trw.com > > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp:/= /www.conekt.net/electronics.html > > Thanks all for the reply; > > I had simulated the code using Modelsim, now I'll try to repeat the > simulation with ISE. I will also read the data2mem manual, but I'm > wondering if the Jtag cable is fast enough to pass data to be > simuleted at clock speed. If not I will always need to store data > temporary into BRAM, also if I use Matlab (Anyway this possibility is > very interesting, do you have any reference about useing Matlab > +SysGen?). > > Thanks again If you've never used SysGen before, I would start with materials on www.xilinx.com. A few pointers: SysGen main page (http://www.xilinx.com/tools/sysgen.htm) Free Recorded Lecture: System Generator Getting Started Training (http://www.xilinx.com/support/training/rel/system-generator.htm) Cheers, Jim http://myfpgablog.blogspot.com/Article: 143263
>On 23 Set, 13:20, "sreedevi1988" <sreedevi1...@gmail.com> wrote: >> Hello, >> >> I am trying to implement a fir filter in vhdl.. i want to put the output >> sequence into a text file, so that I can use the same text file in MATLAB >> and check the frequency response.. The problem I am facing is;;when I try >> to simulate thro Modelsim, it gives the following errors... >> >> # ** Warning: fir_low.vhd(57): (vcom-1194) FILE declaration was written >> using VHDL 1987 syntax. >> # ** Error: fir_low.vhd(89): No feasible entries for subprogram "write". >> # ** Error: fir_low.vhd(90): No feasible entries for subprogram >> "writeline". >> # ** Error: fir_low.vhd(94): VHDL Compiler exiting >> # ** Error: C:/Modeltech_xe_starter/win32xoem/vcom failed. >> >> Pls help me out in this regard. >> >> Thank you, >> Sreedevi > >If you didn't solve the problem yet, try to post the post the piece of >code > >Bye > >Dek > Hello --------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 15:10:27 09/09/2009 -- Design Name: -- Module Name: fir_plsssssss - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; library std; use IEEE.std_logic_textio.all; use std.textio.all; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use ieee.STD_LOGIC_UNSIGNED.ALL; use ieee.math_real.all; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fir_low is port(clk: in std_logic ); end fir_low; architecture Behavioral of fir_low is constant n: integer := 24; type real is range -2147483647.0 TO 2147483647.0; type b is array(0 to n) of real; type x is array(0 to n) of real; --type LINE is access string; --type TEXT is file of string; constant m: integer := 486; type y is array(0 to m) of real; --signal inpu,c:b := (0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0); signal coeff:b := (0.0013 , 0.0026, 0.0, -0.0072,-0.0072 , 0.0112, 0.0272, 0.0, -0.0581, -0.0538, 0.0875, 0.2971, 0.3988, 0.2971, 0.0875, -0.0538, -0.0581, 0.0, 0.0272, 0.0112, -0.0072, -0.0072, 0.0, 0.0026, 0.0013); signal final : y; signal outinp:y :=(12.3353,19.8419,26.8143,32.4206,35.9764,37.0465,35.5109,31.5833,25.7799,18.8417,11.6238,4.9678,0.4210,4.0732,5.8150,5.7791,4.3658,2.1608,0.1763,2.0330,2.9548,2.7273,1.4145,0.6521,2.9326, 4.7762,5.5401,4.7104,2.0039,2.5662,8.6736,15.7133,22.8840,29.3042,34.1449,36.7563,36.7692,34.1533,29.2243,22.5971,15.0929,7.6163,1.0201,4.0190,7.0943,8.1182,7.3191,5.1865,2.3760,0.4125,2.5595,3.6353,3.4742,2.2014,0.2088,1.9164,3.4995,3.9021,2.6432,0.5044,5.4577,11.8184,18.9190,25.9152,31.9090,36.0837,37.8286,36.8353,33.1481,27.1624,19.5700,11.2608,3.1955,3.7304,8.8107,11.6218,12.0717,10.3985,7.1190,2.9382,1.3662,5.0657,7.5886,8.5989,8.0340,6.0976,3.2096,0.0751,3.1665,5.5399,6.8204,6.8395,5.6530,3.5220,0.8592,1.8484,4.1256,5.5903,6.0162,5.3657,3.7901,1.5965,0.8099,3.0000,4.5956,5.3339,5.1095,3.9887,2.1930,0.0560, 2.0374,3.7198,4.7049,4.8359,4.1093,2.6726,0.7947,1.1842,2.9129,4.0920,4.5246,4.1490,3.0472,1.4269,0.4163,2.1533,3.4795,4.1680,4.1082,3.3229,1.9627,0.2767,1.4324,2.8625,3.7652,3.9890,3.5042,2.4064,0.8980,0.7491,2.2419,3.3190,3.7953, 3.5944,2.7601,1.4475,0.1057,1.6223,2.8348,3.5322,3.5971,3.0248,1.9234,0.4930,1.0102,2.3197,3.2059,3.5163,3.2016,2.3231,1.0414,0.4132,1.7821,2.8238,3.3570,3.2916,2.6441,1.5336,0.1602,1.2311,2.3941,3.1248,3.2971,2.8844,1.9637,0.7016,0.6765,1.9260,2.8266,3.2210,3.0427,2.3265,1.2024,0.1284,1.4291,2.4698,3.0675,3.1188,2.6174,1.6547,0.4034,0.9137,2.0629,2.8417,3.1137,2.8328,2.0510,0.9088,0.3901,1.6153,2.5498,3.0292,2.9702,2.3848,1.3785,0.1308,1.1365,2.1990,2.8688,3.0283,2.6505,1.8036,0.6387,0.6371,1.7974,2.6369,3.0072,2.8436,2.1758,1.1230,0.1276,1.3541,2.3391,2.9081,2.9607,2.4879,1.5740,0.3812,0.8787,1.9822,2.7338,3.0000,2.7338,1.9822,0.8787,0.3812,1.5740,2.4879,2.9607,2.9081,2.3391,1.3541,0.1276,1.1230,2.1758,2.8436,3.0072,2.6369,1.7974,0.6371,0.6387,1.8036,2.6505,3.0283,2.8688,2.1990,1.1365,0.1308, 1.3785,2.3848,2.9702,3.0292,2.5498,1.6153,0.3901,0.9088,2.0510,2.8328,3.1137,2.8417,2.0629,0.9137,0.4034,1.6547,2.6174,3.1188,3.0675,2.4698,1.4291,0.1284,1.2024,2.3265,3.0427,3.2210,2.8266,1.9260,0.6765,0.7016,1.9637,2.8844,3.2971,3.1248,2.3941,1.2311,0.1602,1.5336,2.6441,3.2916,3.3570,2.8238,1.7821,0.4132,1.0414,2.3231,3.2016,3.5163,3.2059,2.3197,1.0102,0.4930,1.9234,3.0248,3.5971,3.5322,2.8348,1.6223,0.1057,1.4475,2.7601,3.5944,3.7953,3.3190,2.2419,0.7491,0.8980,2.4064,3.5042,3.9890,3.7652,2.8625,1.4324,0.2767,1.9627,3.3229,4.1082,4.1680,3.4795,2.1533,0.4163,1.4269,3.0472,4.1490,4.5246,4.0920,2.9129,1.1842,0.7947,2.6726,4.1093,4.8359,4.7049,3.7198,2.0374,0.0560,2.1930,3.9887,5.1095,5.3339,4.5956,3.0000,0.8099,1.5965,3.7901,5.3657,6.0162,5.5903,4.1256,1.8484,0.8592,3.5220,5.6530,6.8395,6.8204,5.5399,3.1665,0.0751,3.2096,6.0976,8.0340,8.5989,7.5886,5.0657,1.3662,2.9382,7.1190,10.3985,12.0717,11.6218,8.8107,3.7304,3.1955,11.2608,19.5700,27.1624,33.1481,36.8353,37.8286,36.0837,31.9090,25.9152,18.9190,11.8184,5.4577,0.5044,2.6432,3.9021,3.4995,1.9164,0.2088,2.2014,3.4742,3.6353,2.5595,0.4125,2.3760,5.1865,7.3191,8.1182,7.0943,4.0190,1.0201,7.6163,15.0929,22.5971,29.2243,34.1533,36.7692,36.7563,34.1449,29.3042,22.8840,15.7133,8.6736,2.5662,2.0039,4.7104,5.5401,4.7762,2.9326,0.6521,1.4145,2.7273,2.9548,2.0330,0.1763,2.1608,4.3658,5.7791,5.8150,4.0732,0.4210,4.9678,11.6238,18.8417,25.7799,31.5833,35.5109,37.0465,35.9764,32.4206,26.8143,19.8419,12.3353,5.1523,0.9452,5.3937,7.8981,8.4559,7.3370,5.0222,2.1117,0.7780,3.1146,4.5285,4.8600,4.1667,2.6940,0.8137,1.0549,2.5280,3.3288, 3.3348,2.5940,1.3066,0.2208,1.6416,2.6409); signal i,j : integer := 0; begin process (clk,i) file outfile:text is out "G:\work1.txt"; variable inp:x:= (3.0000,2.6409,1.6416,0.2208,1.3066,2.5940,3.3348,3.3288,2.5280,1.0549,0.8137,2.6940,4.1667,4.8600,4.5285,3.1146,0.7780,2.1117,5.0222,7.3370,8.4559,7.8981,5.3937,0.9452,5.1523); variable temp: real := 0.0; variable temp1: real := inp(0); variable y:real := 0.0; VARIABLE out_l : line; variable inpu,c:b := (0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0); variable outinp_slv_var : std_logic_vector(15 downto 0); variable outinp_int : integer := 0; variable int :integer := 0; begin if(rising_edge(clk)) then y := 0.0; for i in 0 to n loop inpu(i) := inp(i); end loop; for i in 0 to (n-1) loop temp := inp(i+1); inp(i+1) := temp1; temp1 := temp; end loop; if (j <m) then inp(0) := outinp(j); j <= j+1; end if; for s in 0 to n loop c(s) := (coeff(s)*inpu(s)); end loop; for t in 0 to n loop y := (y + c(t)); end loop; final(i) <= y; if (i<m) then i <= i+1; end if; outinp_int := integer(y* 10000.0); outinp_slv_var := conv_std_logic_vector(outinp_int,16); --WRITE(out_l,y); write (out_l, outinp_slv_var); write( outfile , out_l); end if; end process; end Behavioral; Hello This is the code I wrote.. Pls neglect so many numbers (input and co-efficient values)The doubts I ve is: a) Do i ve to declare what a line and text is? I mean type LINE is access string; type TEXT is file of string; b) Here, I've tried to convert a real number into a std logic vector n write into a text...Can't I directly put in a number like 2.3456 into a text file? Anyway, neither of them is working.. Pls help me!!! --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143264
On Sep 29, 3:05=A0am, emeb <ebromba...@gmail.com> wrote: > On Sep 28, 10:00=A0am, Andy Peters <goo...@latke.net> wrote: > > > Another thing is that S3E appears to be available in more packages > > than S3A so you might be able to find a better fit for a particular > > design. > > That's my principle objection to the S3A family. I buy my parts from > Digi-Key, and the only non-BGA packages for S3A are the 50K devices. I > have fairly limited assembly resources so BGA / QFN parts aren't > possible, but I want larger devices. What to do? > > Eric Altera has MUCH larger selection of non-BGA packages so you can use the latest devices and HUGE ones if you need, all in TQFP packages I totally agree that S3A is BAD as of package selection but Xilinx is doing many things bad/wrong/too late S3 - good as of LARGE parts XC3S5000 !!! S3E - not as good any more, large parts dropped, but larger part in nonBGA as in S3A S3A - good configuration options (multiboot) bad package options S3AN - even worse package options S3ADSP - large and better than S3A, but only 2 devices S6 - better in some terms, but again limited package options so there is never a best, its compromise so or so S3A has multiboot, and need one power supply less than S3E but you are pretty much limited to S3A(N) 50 if talking non BGA while S3E gives 500 part in TQFP100 yes, actually if thinking S3E or S3A then winner is: Cyclone III :) Cy@ dont give up ;) there is rule of thumb: it takes 6+ month from initial product launch til you may hope some interest (sales) your 6 months isnt past yet S3E multiboot can be implemented using 0.49$ MCU adding and expensive CPLD (bad $/feature ratio) to the board give no benefits to the user, it makes the PCB and documentation more expensive, yes you always have to consider documentation as cost item, you spend time (or you pay$$ for someone todo it) AnttiArticle: 143265
..using Altera Stratix3 and TI's XIO1011B PHY. Altera/PLDA's core is too expensive to use with a yearly fee. Axcon.dk have a nicer price, but I want to look for even better. A one off cost with available source code is preferred.Article: 143266
"Morten Leikvoll" <mleikvol@yahoo.nospam> writes: > ..using Altera Stratix3 and TI's XIO1011B PHY. > > Altera/PLDA's core is too expensive to use with a yearly fee. > Axcon.dk have a nicer price, but I want to look for even better. > > A one off cost with available source code is preferred. Last time I worked with PCIe we rolled our own implementation. However, we used a verification library from nSys. If you have more design resources than cash this is a possible way to go. BTW, the Arria II GX and Stratix IV GX contains PCIe hardmacros, wouldn't that be a better choice? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 143267
Hello all, I was wondering about the current status of IP protection for Xilinx targets, and in general. * I guess ISE version 11 is going to provide solutions based on Flexlm (with _timed_ licenses, floating or non floating, single family or multi-family, with or without bitstream generation, with or without simulation netlist generation, etc). But is this available now ? What about Webpack users ? (even v11) ? * What was/is available pre-11 ? - I know there is a solution for Synplify users - What for XST users ? Some users seem reluctant to switch to v11. I didn't check if Synplicity encryption was avaimable for Actel users, so if anyone knows the answer... AFAIK, Altera seems the most advanced vendor regarding IP protection but I guess all the other vendors should have solutions. Thanks in advance, BertArticle: 143268
"Petter Gustad" <newsmailcomp6@gustad.com> wrote in message news:87zl8e2mf8.fsf@pangea.home.gustad.com... > "Morten Leikvoll" <mleikvol@yahoo.nospam> writes: > >> ..using Altera Stratix3 and TI's XIO1011B PHY. >> >> Altera/PLDA's core is too expensive to use with a yearly fee. >> Axcon.dk have a nicer price, but I want to look for even better. >> >> A one off cost with available source code is preferred. > > Last time I worked with PCIe we rolled our own implementation. > However, we used a verification library from nSys. If you have more > design resources than cash this is a possible way to go. > > BTW, the Arria II GX and Stratix IV GX contains PCIe hardmacros, > wouldn't that be a better choice? > > Petter Thanks for the quick reply. The Arrira and Stratix IV are options but will require some redo of the pcb (the Statix3 was drawn in long time ago, but our Altera's dealer forgot to mention licensing cost for this core) Unfortunately we got neither excess of design resources nor cash (hey, credit crunch still hasn't disappeared ;)Article: 143269
On Sep 29, 11:27=A0am, "Antti.Luk...@googlemail.com"
<antti.luk...@googlemail.com> wrote:
> On Sep 29, 1:57=A0am, -jg <jim.granvi...@gmail.com> wrote:
>
>
>
> > On Sep 29, 10:35=A0am, nobody <cydrollin...@gmail.com> wrote:
>
> > > JG
>
> > > You asked the question of cheap communication for both programmming
> > > and runtime information at an acceptable bandwidth not to mention the
> > > power over usb. FTDI has been successful in this design and will be
> > > looking at the FT2232 for all its communication protocols, jtag being
> > > one of the most useful in this design.
>
> > Just to clarify, I was talking of their new FT2232H, which has
> > high speed USB.
> > There was a thread some weeks ago on cae, about the sustainable
> > data rate (no breaks/fixed tick-rate) on a 2232H, and I'm not sure
> > what the final answer was. 2232H has larger buffers, and higher peak
> > speeds, so the sustainable number has to be higher ?
>
> > -jg
>
> FTDI has claimed so 20MByte
Has anyone confirmed this is a sustainable ('gapless') rate ?
> this is more then 2 times less than with cypress FX2
The price is also quite a bit lower for FT2232H, and it is sure to
replace a FT232R rather easier.
The speed jump from FT232R to FT2232H, is larger than the smaller
extra gain of the FX2.
20MByte (if supported thru windows) is a good logic analyser, or
Counter sampling rate.
FX2 prices seem to be climbing, and something like a UC3A3 has
a LOT more bang for less $$ (but admittedly is newer, so has less
infrastructure right now.. )
UC3A3 really needs a lower pin count member, for this sort of
FPGA+USB_Instruments application.
-jg
Article: 143270Hello, in quest for the HDL source files for the Spartan 6 SP601 Demo board and application, all I find is http://forums.xilinx.com/xlnx/board/message?board.id=Spartan&thread.id=3844 > BTW, the design files are 'Coming Soon'.... Some zip files are available at http://www.xilinx.com/products/boards/sp601/reference_designs.htm but they contain very few .v files. This seems not enough to rebuild (and later adapt) the Ethernet/DSP application delivered with the board. Even not to bebuild the build-in self test... Any news about those HDL files? Thanks -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 143271
> Looking for interest in an Open Source Hardware USB programmable FPGA, > XC3S250E. I have been having some difficulty getting the right people > exposed to this project. If you have any interest in this project > would like to hear from you. It is headed into an Open Source Hardware > agreement therefore their is no proprietary information about the > design. Resources available here http://www.fpgaz.com/usbp/index.html and here http://www.myhdl.org/doku.php/users:cfelton:projects:usbpArticle: 143272
On Sep 28, 8:05=A0pm, emeb <ebromba...@gmail.com> wrote: > On Sep 28, 10:00=A0am, Andy Peters <goo...@latke.net> wrote: > > > Another thing is that S3E appears to be available in more packages > > than S3A so you might be able to find a better fit for a particular > > design. > > That's my principle objection to the S3A family. I buy my parts from > Digi-Key, and the only non-BGA packages for S3A are the 50K devices. I > have fairly limited assembly resources so BGA / QFN parts aren't > possible, but I want larger devices. What to do? This is one of my complaints about FPGA vendors. Of course, they are responding to the market and the profit figure. But my designs typically use small, cramped boards and BGAs are typically not an improvement over the right size leaded package. Yes, the BGA looks smaller on the data sheet, but they typically require a board with more layers and they use real estate on *both* sides of the board unless you want to use some pretty exotic technology such as blind vias. I did a calculation yesterday and found that one of the two low pin count leadless packages for the S6 parts uses less real estate than a 100 TQFP by going to a 0.5 mm ball pitch. The other one is "smaller" but after counting the other side of the board as being used, actually is 30% larger with a 0.8 mm ball pitch. And that doesn't consider that these parts are all moe expensive because of the higher I/O count making higher testing costs. I'm just not a fan of BGA and CS technology for my designs. RickArticle: 143273
On Sep 29, 9:41=A0am, rickman <gnu...@gmail.com> wrote: > On Sep 28, 8:05=A0pm, emeb <ebromba...@gmail.com> wrote: > > > On Sep 28, 10:00=A0am, Andy Peters <goo...@latke.net> wrote: > > > > Another thing is that S3E appears to be available in more packages > > > than S3A so you might be able to find a better fit for a particular > > > design. > > > That's my principle objection to the S3A family. I buy my parts from > > Digi-Key, and the only non-BGA packages for S3A are the 50K devices. I > > have fairly limited assembly resources so BGA / QFN parts aren't > > possible, but I want larger devices. What to do? > > This is one of my complaints about FPGA vendors. =A0Of course, they are > responding to the market and the profit figure. =A0But my designs > typically use small, cramped boards and BGAs are typically not an > improvement over the right size leaded package. =A0Yes, the BGA looks > smaller on the data sheet, but they typically require a board with > more layers and they use real estate on *both* sides of the board > unless you want to use some pretty exotic technology such as blind > vias. =A0I did a calculation yesterday and found that one of the two low > pin count leadless packages for the S6 parts uses less real estate > than a 100 TQFP by going to a 0.5 mm ball pitch. =A0The other one is > "smaller" but after counting the other side of the board as being > used, actually is 30% larger with a 0.8 mm ball pitch. I agree, I am usually looking for small footprint high logic resource parts. It is odd, the vendors might have missed some opportunities here. I come across more and more designers with these needs. Most designers simply opt out and force a small footprint uC to work (or barely work). At one point I was excited about the Actel QFNs but they have these non-standard dual row/column QFNs. And when I do use a high pin-count BGA majority of the pins are unused.Article: 143274
On Sep 25, 9:19=A0am, Poojan Wagh <poojanw...@gmail.com> wrote: > I'd like to set up automated unit test scripts. (I'm using Riviera Pro > 2009.06.) Does anyone know a good way of doing this? > > For example, I've written assertion-based unit tests for most of my > modules. I'd like something to run each test and summarize the > results. I know I could probably do so with a csh/bash script. > However, I was looking for something more canned if it exists. I don't know about Riviera but if you use MyHDL you get all the benefits of the Python Universe. Unit test and batteries included.
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