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hariz wrote:
> i am just a new user of modelsim and debussy, can anyone help me transfer
> my code to modelsim and debussy from quartus?
>
> i have a code in verilog using quartus..but due to long simulation time i
> can't view all the output..so i switched to modelsim..however, i cant view
> the memory contents in modelsim..
>
> how can i double check the contents of my memory in modelsim?
>
>
I add the memory array variable or signal to the waveforms.
If I leave the mouse arrow over the array waveform,
a table of values pops up for each clock tick.
Or just have the testbench write some values
and read them back.
-- Mike Treseler
Article: 143126I have an (obsolete) Altera Logic Programmer Card (PLP6) that I cannot get to work. I installed MaxPlus2 v 10.23 and the PLP6 driver on a WinXP box. When I attempt to setup the card in the MaxPlus2, it tells me that it cannot find the card. Do you have any information about this card? I can find nothing online. Do you have a datasheet? There are 5 red LEDs on the card. Do you know what they mean? Thank you.Article: 143127
Nicolas Matringe wrote:
> I copied the working code at the end of this message. If I define
> variable v_bcnt as unsigned(5 downto 0) then the design stops working.
> I haven't dug into the problem but SPI communication doesn't work
> anymore.
consider using a natural range instead of unsigned.
Synthesis won't waste any bits if you declare the range.
> I know I should probably submit a testcase but I don't have much time
> at the moment. Any help around this problem is welcome.
I would write a testbench instead.
Probably something to do with unsigned rollover.
Good luck.
-- Mike Treseler
Article: 143128Looking for interest in an Open Source Hardware USB programmable FPGA, XC3S250E. I have been having some difficulty getting the right people exposed to this project. If you have any interest in this project would like to hear from you. It is headed into an Open Source Hardware agreement therefore their is no proprietary information about the design. Here is an image of the board. http://www.mediafire.com/imageview.php?quickkey=yhjjddznzmx&thumb=5 Cy Drollinger Electronic Realization L.L.C. 313 W. Mendenhall #5 Bozeman, MT 59715 PH: 406-586-5502 Email: cy@montana.netArticle: 143129
On Sep 22, 7:27=A0am, KJ <kkjenni...@sbcglobal.net> wrote: > On Sep 22, 7:18=A0am, Antti <antti.luk...@googlemail.com> wrote: > > > =A0 signal next =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0: integer range -1 to 2; > > I missed this line in my first post. =A0So for starters, 'next' would > have to be 3 bits based on the defined range. =A0As I mentioned in the > previous post, depending on what the logic actually is, some of the > bits could be optomized away during synthesis. =A0If there is a two bit > (or one bit) implementation, synthesis tools will most likely find > it. =A0Reduction of simple boolean logic as in this case is their strong > suit. > > Kevin Jennings Most synthesis tools implement symmetrical signed ranges, so -1 to 2 takes the same number of bits as required for -3 to 2, which is 3 bits. Most synthesis tools will implement "integer range 6 to 7" as three bits too (same as for 0 to 7). Most synthesis tools will not alter the coding to use fewer bits. Synthesis might be able to optimize decoding the value based on the range specification (i.e. values -2 and -3, while representable in three bits, are not, by definition, possible), such that decoding, e.g. 2, only requires looking at two of the bits, etc. AndyArticle: 143130
On Sep 22, 7:34=A0pm, Andy <jonesa...@comcast.net> wrote: > On Sep 22, 7:27=A0am, KJ <kkjenni...@sbcglobal.net> wrote: > > Most synthesis tools will implement "integer range 6 to 7" as three > bits too (same as for 0 to 7). > > Most synthesis tools will not alter the coding to use fewer bits. > That's only one of the first steps in the synthesis process though. Synthesis tools will then look at the boolean logic that gets created and optomize that. As I mentioned previously, the OP's example where the only assignment was to a value of -1 (because he intentionally commented out the rest for clarity) would cause 'next' to get reduced to a constant which would then get absorbed into whatever logic that depends on 'next' so 'next' would be implemented in 0 bits. Another example would be if the only use of some integer that is defined to be in the range of 0 to 7 is of the form "if my_integer >=3D 4 then..." would result in only one bit being implemented...this would also be true if the range was define to be 4 to 7 or -529 to 683. The bottom line is one can't really answer the question of how many bits it will take to implement some integer without knowing the context of how that integer gets used (i.e. what is the logic that uses that integer). Knowing the defined range for the integer tells you the upper bound on how many bits it might take, not the actual number. Kevin JenningsArticle: 143131
On Sep 22, 8:27=A0pm, KJ <kkjenni...@sbcglobal.net> wrote: Disregard this part.. > this would if the range was ... or -529 to 683. >Article: 143132
hariz wrote: > i am just a new user of modelsim and debussy, can anyone help me transfer > my code to modelsim and debussy from quartus? Where do you need debussy with Modelsim. Most of the debussy features are already in normal Modelsim gui. > how can i double check the contents of my memory in modelsim? There are many ways, one is to use in the workspace pane Memory tab and find the memory array there. Or in the objects window right click the memory array and select "View memory contents". If you need to modify the contents etc. that can be done via the memory viewer or via tcl commands in scripts. Remember to make sure that you have enough visibility (-novopt or +acc in vopt flow). --KimArticle: 143133
Mike Treseler wrote: > I add the memory array variable or signal to the waveforms. > If I leave the mouse arrow over the array waveform, > a table of values pops up for each clock tick. If the memory is done in VHDL signals/variables this slows down the simulation considerably. On the other hand if the memory is done in verilog the simulation does not slow down. Only verilog has optimizations in this area. Just small tip if simulation performance is needed ;) --KimArticle: 143134
On Sep 22, 10:19=A0pm, nobody <cydrollin...@gmail.com> wrote: > Looking for interest in an Open Source Hardware USB programmable FPGA, > XC3S250E. I have been having some difficulty getting the right people > exposed to this project. If you have any interest in this project > would like to hear from you. It is headed into an Open Source Hardware > agreement therefore their is no proprietary information about the > design. > > Here is an image of the board.http://www.mediafire.com/imageview.php?quic= kkey=3Dyhjjddznzmx&thumb=3D5 > > Cy Drollinger > Electronic Realization L.L.C. > 313 W. Mendenhall #5 > Bozeman, MT 59715 > PH: 406-586-5502 > Email: c...@montana.net Dear Cy who are the right people? customers buying the hardware from you? an OEM fab that manufacturers the board for you cheaply? developers who spend their time to support your board so you can use those open source projects to sell more boards and make more money? somebody who can give you good advice? the PCB is far too expensive to make for "open source" guys, so nobody will build this board, unless you manufacture and sell it cheaply, so whatever you call open source hardware, it is just an commercial products with schematic made public, but the schematics of most FPGA development hardware is openly public anyway, so where is you point? you really have to say what type of contacts you are looking for! AnttiArticle: 143135
Hi for the very unlikely case that some one from Estonia hasnt found http://www.vtl.ee/kokkutulek09/ the page for registration for this year meeting, i post it here too of course if someone from finland/sweden wants to come, welcome too but the workshops are in estonian language ;) there will be a small mini-exhibition, i try to drag most of my FPGA stuff there i will be writing a short story afterwards in october brain too http://groups.google.com/group/antti-brain/files?hl=en AnttiArticle: 143136
HI, I have to develope FIR filter, the IP core for FIR filter is alredy there with Xilinix ISE suite. I added the IP core by specifiying the Coefficeint file, but i need to know where i should instantiate this FIR ?. after that how should i synthesize and impement my design if any one worked on this kind of cores please help me out.Article: 143137
On Sep 22, 8:33=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > Nicolas Matringe wrote: > > I copied the working code at the end of this message. If I define > > variable v_bcnt as unsigned(5 downto 0) then the design stops working. > > I haven't dug into the problem but SPI communication doesn't work > > anymore. > > consider using a natural range instead of unsigned. > Synthesis won't waste any bits if you declare the range. I will give this a try. However I have another problem with the same code and variable v_cntr (type natural). If I change its range (and change the constants assigned to it accordingly) the design also stops working NicolasArticle: 143138
Hello, I am trying to implement a fir filter in vhdl.. i want to put the output sequence into a text file, so that I can use the same text file in MATLAB and check the frequency response.. The problem I am facing is;;when I try to simulate thro Modelsim, it gives the following errors... # ** Warning: fir_low.vhd(57): (vcom-1194) FILE declaration was written using VHDL 1987 syntax. # ** Error: fir_low.vhd(89): No feasible entries for subprogram "write". # ** Error: fir_low.vhd(90): No feasible entries for subprogram "writeline". # ** Error: fir_low.vhd(94): VHDL Compiler exiting # ** Error: C:/Modeltech_xe_starter/win32xoem/vcom failed. Pls help me out in this regard. Thank you, SreedeviArticle: 143139
On Sep 23, 4:38=A0am, "nic_o_...@msn.com" <nic_o_...@msn.com> wrote: > On Sep 22, 8:33=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > > > Nicolas Matringe wrote: > > > I copied the working code at the end of this message. If I define > > > variable v_bcnt as unsigned(5 downto 0) then the design stops working= . > > > I haven't dug into the problem but SPI communication doesn't work > > > anymore. > > > consider using a natural range instead of unsigned. > > Synthesis won't waste any bits if you declare the range. > > I will give this a try. > However I have another problem with the same code and variable v_cntr > (type natural). If I change its range (and change the constants > assigned to it accordingly) the design also stops working > > Nicolas Simulation and debug will likely get you to the root cause faster...'specially since the only description you give of the unexpected behaviour is "the design also stops working". KJArticle: 143140
I see what you are getting at, and you are correct, to a point. Yes, if it turns out that none of the bits is ever used, then none of the bits will get implemented (we have no idea where/if "next" gets used). However if it is used, the coding, or those bits that are left of it, in all the synthesis tools I have seen, will be from the original three bit encoding. For example, I have yet to see a synthesis tool that would recode range -1 to 2 as range 0 to 3, which would allow ALL valid values to be encoded with only two bits. > Another example would be if the only use of some integer that is > defined to be in the range of 0 to 7 is of the form "if my_integer >= > 4 then..." would result in only one bit being implemented...this would > also be true if the range was define to be 4 to 7 ... Actually, decoding "my_integer >= 4" from a value with a valid range of 4 to 7 could take zero bits (constant TRUE). Synthesis sometimes (I haven't nailed down exactly under what conditions) looks at what gets stored in an object as well as what is read from it to make optimizations. I have seen this occur with a counter that counted from 0 to 5 and rolled over, unconditionally. It happened to be a natural range 0 to 5. I don't know whether Symplify took the range as a hint, or performed a reachability analysis on the counter, but it only looked at two of the bits to decode some of the values. AndyArticle: 143141
On Sep 23, 9:07=A0am, Andy <jonesa...@comcast.net> wrote: > I see what you are getting at, and you are correct, to a point. Yes, > if it turns out that none of the bits is ever used, then none of the > bits will get implemented (we have no idea where/if "next" gets used). > > However if it is used, the coding, or those bits that are left of it, > in all the synthesis tools I have seen, will be from the original > three bit encoding. For example, I have yet to see a synthesis tool > that would recode range -1 to 2 as range 0 to 3, which would allow ALL > valid values to be encoded with only two bits. > [snip] > > Andy It turns out that even with simple binary encoding, the values -1 to 2 (or any set of four contiguous integer values) can always be decoded using only bits 1 and 0 as these are different for each value. In the case of -1 to 2 they are 11 00 01 10, and so even though bit 2 also changes it is not necessary to use bit 2 for decoding IF the optimising agent is smart enough to detect that bit 2 can be described as a function of bits 1 and 0 and is therefore redundant. Regards, GaborArticle: 143142
Sreedevi, Here is a link to a test bench vhdl file: mix_n_uart_test.vhd that was used to do just what you are attempting. http://www.mediafire.com/file/y3vnd3jihyy/mix_n_uart_test.vhd Cy Drollinger E.R. L.L.C.Article: 143143
I'm porting linux 2.6 kernel to a ML 410 board using Xilinx's kernel tree. Particularly, I would like to use Xilinx's icap driver (as in driver/char/xilinx_hwicap. I do not have problems in using it to write a partial bitstream to ICAP; but I have a problem when performing read back. I'm trying to read from a device from a user application using: int* frame = (int*) malloc( 83 * sizeof(int)); FILE *ICAP; ICAP = fopen("/dev/icap0", "r+b"); fwrite(word, sizeof(*word), 18, ICAP); fread(frame, sizeof(int), 83, ICAP); The device is opened OK. And the 18 words written to icap is the same as those in hwicap v1_01_a driver's xhwicap_device_read_frame.c: 1. Dummy 2. Sync 3. Noop 4. Noop 5. CMD 6. RCRC 7. Noop 8. Noop 9. CMD 10. RCFG 11. Noop 12. Noop 13. Noop 14. W FAR 15. frame addr 16. FRDO 83 words 17. Noop 18. Noop The problem is, in icap read function, static int buffer_icap_device_read(struct hwicap_drvdata *drvdata,u32 offset, u32 count) "count" is not the same value as I requested with fread. Instead of 0x53 (words), it gets 0x1000 (bytes). This value seems to causes a device read failure (it is not associated with frame boundary, and it is not the same value as previous command written to icap requests)- the icap status register after read is 0, not the normal value 0x7ffc; and data copied to user buffer is not the desired frame data. Actually, I am able to work around with this problem by forcing count to 83 in hwicap_read. This is OK since I mostly only needs to read one frame. By doing so, icap status register is the correct value of 0x7ffc after read. And in user space, *frame get the desired frame data. How can I fix the driver function so that hwicap_read gets the same "count" as fread passes to it? Or did I make any mistake? best regards Wenwei ZhaArticle: 143144
Antti, I enjoy your responses they are to the bone, but valid. The right people are engineers who wish to pick this project up for their benefit, yes antti as well as mine. The engineer would be some one willing to pay a bit extra for one of four boards available with all the design file associated with the boards. These files are the meat of the work and would allow an engineer to make changes from the current form to one more suitable to their needs, if necessary. Open Source license also allows anyone willing to manufacture this product for sale and profit of their own, royalty free. Development and testing is a huge cost and has been paid for in this project. Yes, antti schematics are available for many of the development boards but firmware and how things are implemented are not. Digilent for example produced a project that only required a usb to miniB connection to the board to program utilizing Xilinx's impact program, how did they do that? They will not tell me, I understand, but it was worth asking. If the 4 layer printed circuit board was manufactured for $6 is that to expensive? My point: is placing all of this projects work in an open source license to be easily duplicated at a reasonable cost one board under $50.00 for someone in need of well behaved electronic signals, maybe an engineer, a student, a hobbyist, and the like. Antti, you are so preceptive, Yes, I would like to be able to accept notes of appreciation for this body of work, because someone finds it helpful. Being able to discuss this body of work and let it go out to those who would find it useful makes me smile. Open Source Hardware licensing just prevents anyone from strangling the work and making it theirs, plagiarism. This body of work is not quite original but is not a rip off, or a copy of another work. Yes, their are similar projects out there and I have asked for help on this project from those similar project, but understandably I got go away, I did. I have spent my resource on this project and I need more to continue on or even try something different. Thanks for asking Antti, Cy DrollingerArticle: 143145
nobody <cydrollinger@gmail.com> wrote:
>Looking for interest in an Open Source Hardware USB programmable FPGA,
>XC3S250E. I have been having some difficulty getting the right people
>exposed to this project. If you have any interest in this project
>would like to hear from you. It is headed into an Open Source Hardware
>agreement therefore their is no proprietary information about the
>design.
>
>Here is an image of the board.
>http://www.mediafire.com/imageview.php?quickkey=yhjjddznzmx&thumb=5
What is the purpose of the board? What needs to be done?
I see an FTDI chip. Can it be programmed through OpenOCD / serial port
JTAG?
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 143146On Sep 23, 6:58=A0pm, nobody <cydrollin...@gmail.com> wrote: > Antti, > > I enjoy your responses they are to the bone, but valid. The right > people are engineers who wish to pick this project up for their > benefit, yes antti as well as mine. The engineer would be some one > willing to pay a bit extra for one of four boards available with all > the design file associated with the boards. These files are the meat > of the work and would allow an engineer to make changes from the > current form to one more suitable to their needs, if necessary. Open > Source license also allows anyone willing to manufacture this product > for sale and profit of their own, royalty free. Development and > testing is a huge cost and has been paid for in this project. Yes, > antti schematics are available for many of the development boards but > firmware and how things are implemented are not. Digilent for example > produced a project that only required a usb to miniB connection to the > board to program utilizing Xilinx's impact program, how did they do > that? They will not tell me, I understand, but it was worth asking. > > If the 4 layer printed circuit board was manufactured for $6 is that > to expensive? > > My point: is placing all of this projects work in an open source > license to be easily duplicated at a reasonable cost one board under > $50.00 for someone in need of well behaved electronic signals, maybe > an engineer, a student, a hobbyist, and the like. Antti, you are so > preceptive, Yes, I would like to be able to accept notes of > appreciation for this body of work, because someone finds it helpful. > Being able to discuss this body of work and let it go out to those who > would find it useful makes me smile. Open Source Hardware licensing > just prevents anyone from strangling the work and making it theirs, > plagiarism. This body of work is not quite original but is not a rip > off, or a copy of another work. Yes, their are similar projects out > there and I have asked for help on this project from those similar > project, but understandably I got go away, I did. > I have spent my resource on this project and I need more to continue > on or even try something different. > > Thanks for asking Antti, > > Cy Drollinger Cy you havent done your homework ;) 1) Xilinx USB cable can be put on customer board (yours) the schematic is FREELY available, FX2+CPLD, support:impact/chipscope/xmd 2) Digilent USB cable can put on customer board (yours) the schematic is FREELY available, FX2 only, support: chipscope/xmd 3) Anttis option: a] FT232RL and S3E, CBUS used for CLK and JTAG, i can provide ALL TOOLS needed for this b] FT245RL + S3AN (uses multiboot) a and b allow full programmability over usb, at lower cost then your, and lower than digilent or xilinx usb embedded all solutions are EASY and READY for anyone to benefit, and lower cost then yours 6$ one off 4 layer PCB? you have good fab, if so! but, you use hard to get and hard to use connectors, making also add on boards expensive, so that reduces the interest another level your work is 1:1 same as "console FPGA" or have i failed to see something? i see nothing what your board does better (both designs are WAY TOO OLD, and WAY too expensive...) AnttiArticle: 143147
On Sep 23, 7:17=A0pm, n...@puntnl.niks (Nico Coesel) wrote: > nobody <cydrollin...@gmail.com> wrote: > >Looking for interest in an Open Source Hardware USB programmable FPGA, > >XC3S250E. I have been having some difficulty getting the right people > >exposed to this project. If you have any interest in this project > >would like to hear from you. It is headed into an Open Source Hardware > >agreement therefore their is no proprietary information about the > >design. > > >Here is an image of the board. > >http://www.mediafire.com/imageview.php?quickkey=3Dyhjjddznzmx&thumb=3D5 > > What is the purpose of the board? What needs to be done? > > I see an FTDI chip. Can it be programmed through OpenOCD / serial port > JTAG? > > -- > Failure does not prove something is impossible, failure simply > indicates you are not using the right tools... > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"If it doesn't fit, use a bigg= er hammer!" > -------------------------------------------------------------- NO you need a JTAG cable to program the CPLD then you can download the FPGA much same idea as the ondemand thing there is no "bootstrap" option that would allow the board to be flashd with empty CPLD and flash soldered =3D=3D=3D BAD design AnttiArticle: 143148
On Sep 23, 11:58=A0am, nobody <cydrollin...@gmail.com> wrote: > Antti, > > I enjoy your responses they are to the bone, but valid. The right > people are engineers who wish to pick this project up for their > benefit, yes antti as well as mine. The engineer would be some one > willing to pay a bit extra for one of four boards available with all > the design file associated with the boards. These files are the meat > of the work and would allow an engineer to make changes from the > current form to one more suitable to their needs, if necessary. Open > Source license also allows anyone willing to manufacture this product > for sale and profit of their own, royalty free. Development and > testing is a huge cost and has been paid for in this project. Yes, > antti schematics are available for many of the development boards but > firmware and how things are implemented are not. Digilent for example > produced a project that only required a usb to miniB connection to the > board to program utilizing Xilinx's impact program, how did they do > that? They will not tell me, I understand, but it was worth asking. Yes, there are vendors who do not make all of their design files available for FPGA development boards. But for the most part, the FPGA makers provide development boards and make all of their design files available. I think they do this to reduce the amount of support required. If you have all of the design files, you don't need to ask so many questions, you can just look it up yourself. So in that sense, there are a number of open source FPGA development boards. Just not with the freedom to make your own copies although I can't imagine an FPGA vendor would object since you would be putting their parts on it! > If the 4 layer printed circuit board was manufactured for $6 is that > to expensive? No one can have a board manufactured for $6. You might be able to get 100 for $600 or possibly even 10 for $60, but not 1 for $6. That is one of the problems with open source hardware. It is "hard" and often difficult to make on your own. But that does not need to be a problem. The most successful open source hardware (OSH) project I have seen is the Beagle Board which can only be made in pretty advanced factories. It uses a Package on Package mounting technique for the processor memory as the OMAP CPU used is intended for use in PDAs and cell phone like applications. So clearly, the fact that you might have to sell some part or even all of the board would not doom the project as Antti might think. (Not trying to put words in your mouth Antti, just making a point). In fact, I am thinking about an open source GPS receiver project which would require not only the electronic hardware, but also a mechanical design be done. Now *that* can be a problem for open source I think. > My point: is placing all of this projects work in an open source > license to be easily duplicated at a reasonable cost one board under > $50.00 for someone in need of well behaved electronic signals, maybe > an engineer, a student, a hobbyist, and the like. Antti, you are so > preceptive, Yes, I would like to be able to accept notes of > appreciation for this body of work, because someone finds it helpful. > Being able to discuss this body of work and let it go out to those who > would find it useful makes me smile. Open Source Hardware licensing > just prevents anyone from strangling the work and making it theirs, > plagiarism. This body of work is not quite original but is not a rip > off, or a copy of another work. Yes, their are similar projects out > there and I have asked for help on this project from those similar > project, but understandably I got go away, I did. > I have spent my resource on this project and I need more to continue > on or even try something different. Have you defined your goals for this project? If you are going to succeed, you need to know what you are trying to do, *clearly*. Others can give feedback on the goals and you can modify them to include as many others as possible. Then you will get as much support as possible. RickArticle: 143149
I was looking up the shift operator in VHDL since I seldom use it and saw that there is both a shift left logical and a shift left arithmetic. The logic shift left shifts in zeros and the arithmetic shift left shifts in the value of the lsb. I remember from school how a shift right can be logical or arithmetic in order to implement signed and unsigned arithmetic. But when shifting left, I have always used a single shift operator, the logical shift. If an arithmetic left shift is used, it gives a valid result for some values, assuming that the "valid" result is the same as multiplying by 2**n. But the arithmetic left shift does not fit that model for other values. On the other hand, the logical left shift *always* returns a value that is the 2**n multiple of the input value, assuming there are no range issues such as overflowing into the sign bit. So I don't understand the utility of the arithmetic left shift operator and I especially don't see the reason for calling it "arithmetic". Can anyone shed some light on this? Rick
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