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On Sep 26, 8:39=A0pm, rickman <gnu...@gmail.com> wrote: > On Sep 23, 12:57=A0pm, "Antti.Luk...@googlemail.com" > > > > <antti.luk...@googlemail.com> wrote: > > On Sep 23, 7:38=A0pm, rickman <gnu...@gmail.com> wrote: > > > > On Sep 23, 11:58=A0am, nobody <cydrollin...@gmail.com> wrote: > > > > > Antti, > > > > > I enjoy your responses they are to the bone, but valid. The right > > > > people are engineers who wish to pick this project up for their > > > > benefit, yes antti as well as mine. The engineer would be some one > > > > willing to pay a bit extra for one of four boards available with al= l > > > > the design file associated with the boards. These files are the mea= t > > > > of the work and would allow an engineer to make changes from the > > > > current form to one more suitable to their needs, if necessary. Ope= n > > > > Source license also allows anyone willing to manufacture this produ= ct > > > > for sale and profit of their own, royalty free. Development and > > > > testing is a huge cost and has been paid for in this project. Yes, > > > > antti schematics are available for many of the development boards b= ut > > > > firmware and how things are implemented are not. Digilent for examp= le > > > > produced a project that only required a usb to miniB connection to = the > > > > board to program utilizing Xilinx's impact program, how did they do > > > > that? They will not tell me, I understand, but it was worth asking. > > > > Yes, there are vendors who do not make all of their design files > > > available for FPGA development boards. =A0But for the most part, the > > > FPGA makers provide development boards and make all of their design > > > files available. =A0I think they do this to reduce the amount of supp= ort > > > required. =A0If you have all of the design files, you don't need to a= sk > > > so many questions, you can just look it up yourself. =A0So in that > > > sense, there are a number of open source FPGA development boards. > > > Just not with the freedom to make your own copies although I can't > > > imagine an FPGA vendor would object since you would be putting their > > > parts on it! > > > > > If the 4 layer printed circuit board was manufactured for $6 is tha= t > > > > to expensive? > > > > No one can have a board manufactured for $6. =A0You might be able to = get > > > 100 for $600 or possibly even 10 for $60, but not 1 for $6. =A0That i= s > > > one of the problems with open source hardware. =A0It is "hard" and of= ten > > > difficult to make on your own. =A0But that does not need to be a > > > problem. =A0The most successful open source hardware (OSH) project I > > > have seen is the Beagle Board which can only be made in pretty > > > advanced factories. =A0It uses a Package on Package mounting techniqu= e > > > for the processor memory as the OMAP CPU used is intended for use in > > > PDAs and cell phone like applications. =A0So clearly, the fact that y= ou > > > might have to sell some part or even all of the board would not doom > > > the project as Antti might think. =A0(Not trying to put words in your > > > mouth Antti, just making a point). > > > > In fact, I am thinking about an open source GPS receiver project whic= h > > > would require not only the electronic hardware, but also a mechanical > > > design be done. =A0Now *that* can be a problem for open source I > > > think. > > > > > My point: is placing all of this projects work in an open source > > > > license to be easily duplicated at a reasonable cost one board unde= r > > > > $50.00 for someone in need of well behaved electronic signals, mayb= e > > > > an engineer, a student, a hobbyist, and the like. Antti, you are so > > > > preceptive, Yes, I would like to be able to accept notes of > > > > appreciation for this body of work, because someone finds it helpfu= l. > > > > Being able to discuss this body of work and let it go out to those = who > > > > would find it useful makes me smile. Open Source Hardware licensing > > > > just prevents anyone from strangling the work and making it theirs, > > > > plagiarism. This body of work is not quite original but is not a ri= p > > > > off, or a copy of another work. Yes, their are similar projects out > > > > there and I have asked for help on this project from those similar > > > > project, but understandably I got go away, I did. > > > > I have spent my resource on this project and I need more to continu= e > > > > on or even try something different. > > > > Have you defined your goals for this project? =A0If you are going to > > > succeed, you need to know what you are trying to do, *clearly*. > > > Others can give feedback on the goals and you can modify them to > > > include as many others as possible. =A0Then you will get as much supp= ort > > > as possible. > > > > Rick > > > Rick, > > > beagle is: > > 1) backed up by TI > > 2) uses (used) newest components > > > Cy's design: > > 1) uses OBSOLETED and NFND components > > > see the difference? > > > Cy: doing something different is an option > > > And as before i am failing to see what you expect to find? > > > I can only sayd that no "open source" developer will be > > ordering and assembling those boards for personal use > > and no company is interested to produce them either > > > so if somebody makes the boards its only you, and then > > you have boards with 2 generation too old FPGA that > > nobody is interested in, and that you can not sell even > > for break even > > > Antti > > I'm not sure what your point is. =A0I am sure there are any number of > differences between nobody's project and the beagleboard. =A0So? > > Why do you think the XC3S250E is an obsolete chip? =A0Heck, every chip > will be off the cutting edge in six months. =A0Personally, I prefer to > use parts that are not brand new designs, especially with Xilinx. > They have a reputation for making their products widely available only > a long time after initial shipments to favored customers. =A0Do you have > any of the new parts? > > As to the beagleboard being "backed up" by TI, that really doesn't > make much of a difference. =A0I have not seen any indication that the > people making them are financially supported by TI. =A0The fact that the > board can only be made by rather advanced technology assemblers means > you pretty much *have* to buy these boards rather than making your > own. =A0I will say that at $150 there is not much incentive to build > your own, even if you want 100's. =A0A much smaller board that I am > building and selling in qty 100's, with cheaper parts costs me $100 to > build. =A0I expect the beagleboard costs close to the selling price, so > maybe TI *is* supporting the project in some way. > > My only problem with the beagleboard is that the power consumption is > too high, and that it has no FPGA ;^) =A0I would like something along > these lines with an ARM9 processor and memory capable of running > Linux, all designed for lowest power so it can run from batteries. > Like a PDA I guess, but more than 6 hours of run time, more like 20 > hours with a PDA sized display. > > I wish this was not the FPGA forum. =A0I don't feel I should carry on > with this discussion here. =A0There are some display technologies I > would like to discuss. =A0Maybe I'll go over to c.a.e and post there... > > Rick Rick, when did you last look for information for S3E based boards made by Xilinx at Xilinx website? if you have done it recently, go and do some search. This should answer the issue why S3e should not be used any more. It's not that bad chip, but S3A is available at digikey already for some time now, so there is no reason not to use S3A S3A S3AN S3ADSP S6 are all newer than S3E, and i have strong belive that Xilinx really wants everyone to use S3A and newer chips for any new designs. Correct me if i am wrong about this. I also feel there is no reason to use something as old as S3E for new designs (unless there are special reasons todo so) Cy's designs uses 1 FT245 2 CPLD 3 S3E 4 Oscillator 5 spi flash need 4 layer PCB and requires external JTAG to bootstrap Anttis design would use 1 FT232R (also used for CLOCK!) 2 S3E or S3A 3 spi flash and would bootstrap with empty components, and could be done with 2 layer PCB see the difference? if you make a design for open source it doesnt mean you should not make it as good as you can, this is what i think, and what i have tried to say as well. AnttiArticle: 143226
On Sep 27, 6:55=A0pm, n...@puntnl.niks (Nico Coesel) wrote: > "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote: > >On Sep 23, 10:47=3DA0pm, "Antti.Luk...@googlemail.com" > ><antti.luk...@googlemail.com> wrote: > >> On Sep 23, 10:41=3DA0pm, nobody <cydrollin...@gmail.com> wrote: > > >> > Antti, > > >> > You have it all figured dont ya, Nobody, nothing, no company, no > >> > interest. Well, seems as if two others have joined in to express som= e > >> > interest. > > >> > =3DA0I agree the mating components, 4 connectors, used on the board = for > >> > stacking the boards are expensive and therefore need to rethink > >> Antti > >> PS I am not as negative just trying to help you, > >> and yes i have pretty much figured out > > >i must correct myself > > >s3e: no failsafe multiboot in SPI flash without external circuitry > > Whats the problem with that? The only limitation of this board is that > you need an external JTAG interface to program it. It would be nicer > to have JTAG thru the FTDI chip. That way you'll always have a > fallback. > > -- > Failure does not prove something is impossible, failure simply > indicates you are not using the right tools... > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"If it doesn't fit, use a bigg= er hammer!" > -------------------------------------------------------------- missing multiboot was one major issue with S3E in my opinion other FPGA had multiboot already, Xilinx was just leaping behind they fixed it in S3A and V5 only multiboot is a VERY important feature, no wonder pretty much all FPGA vendors support it in their latest families. Ah, when we talk about open-source user programmable USB FPGA things, I already have one on my desk, well it isnt opened yet to public, but it soon will be, it does use FT245 and FPGA with multiboot feature, first image is programmed with FTDI communication and some default FPGA applicatation that is responsible for SPI flash update, and user application auto start, leaving 3 FPGA configurations for the user AnttiArticle: 143227
"Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com> wrote:
>On Sep 26, 8:39=A0pm, rickman <gnu...@gmail.com> wrote:
>> On Sep 23, 12:57=A0pm, "Antti.Luk...@googlemail.com"
>>
>>
>>
>> <antti.luk...@googlemail.com> wrote:
>> > On Sep 23, 7:38=A0pm, rickman <gnu...@gmail.com> wrote:
>>
>> > > On Sep 23, 11:58=A0am, nobody <cydrollin...@gmail.com> wrote:
>>
>> > > > Antti,
>>
>> > > > I enjoy your responses they are to the bone, but valid. The right
>> > > > people are engineers who wish to pick this project up for their
>> > > > benefit, yes antti as well as mine. The engineer would be some one
>> > > files available. =A0I think they do this to reduce the amount of supp=
>ort
>> > > required. =A0If you have all of the design files, you don't need to a=
>sk
>e
>> > > > on or even try something different.
>>
>> > > Have you defined your goals for this project? =A0If you are going to
>> > > succeed, you need to know what you are trying to do, *clearly*.
>> > > Others can give feedback on the goals and you can modify them to
>> > > include as many others as possible. =A0Then you will get as much supp=
>ort
>> > > as possible.
>>
>> > > Rick
>>
>> Linux, all designed for lowest power so it can run from batteries.
>> with this discussion here. =A0There are some display technologies I
>> would like to discuss. =A0Maybe I'll go over to c.a.e and post there...
>>
>> Rick
>
>Rick,
>when did you last look for information for S3E based boards made by
>Xilinx at Xilinx website?
>if you have done it recently, go and do some search. This should
>answer the issue why
>S3e should not be used any more. It's not that bad chip, but S3A is
>available at digikey
>already for some time now, so there is no reason not to use S3A
>S3A
>S3AN
>S3ADSP
>S6
>are all newer than S3E, and i have strong belive that Xilinx really
>wants everyone
Sorry, but this sounds like a load of crap to me. The S3E is a
perfectly useful chip. Although the pin configuration is more limited
that the standard S3 parts. You seem obsessed with flash. FYI none of
the designs I ever worked on used flash to store the FPGA
configuration. Flash isn't a big deal for everyone.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 143228Nico Coesel <nico@puntnl.niks> wrote: > "Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com> wrote: > Sorry, but this sounds like a load of crap to me. The S3E is a > perfectly useful chip. Although the pin configuration is more limited > that the standard S3 parts. You seem obsessed with flash. FYI none of > the designs I ever worked on used flash to store the FPGA > configuration. Flash isn't a big deal for everyone. But the 2.5 Volt-only JTAG is a PITA... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 143229
On Sep 28, 4:42=A0am, "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> > > Anttis design would use > 1 FT232R (also used for CLOCK!) Why not FT2232H here, to "make it as good as you can," ? > 2 S3E or S3A > 3 spi flash I assume this includes SPI Flash with 2b/4b modes, again "make it as good as you can," ? ( or maybe even 2 SPI flash devices...) -jgArticle: 143230
-jg <jim.granville@gmail.com> wrote: > On Sep 28, 4:42 am, "Antti.Luk...@googlemail.com" > <antti.luk...@googlemail.com> > > > Anttis design would use > > 1 FT232R (also used for CLOCK!) > Why not FT2232H here, to "make it as good as you can," ? The FT2232H costs more buck and needs more infrastructure. But I perfer it too... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 143231
On Sep 28, 9:48=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu-
darmstadt.de> wrote:
> -jg <jim.granvi...@gmail.com> wrote:
> > Why not FT2232H here, to "make it as good as you can," ?
>
> The FT2232H costs more buck and needs more infrastructure. But I perfer i=
t
> too...
I like the potential for a reasonable rate continual sample, for
things like PC Frequency counter, Logic analyzer ets, as it's always
good to have a 'free instrument' or two, in any development kit, and
especially so for teaching.
{ We've been getting quite good results from SoundCards, on the 'free
instrument' front, (but with obvious bandwidth ceilings) }
-jg
Article: 143232On Sep 27, 12:42=A0pm, "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote: > On Sep 26, 8:39=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > On Sep 23, 12:57=A0pm, "Antti.Luk...@googlemail.com" > > > <antti.luk...@googlemail.com> wrote: > > > On Sep 23, 7:38=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > On Sep 23, 11:58=A0am, nobody <cydrollin...@gmail.com> wrote: > > > > > > Antti, > > > > > > I enjoy your responses they are to the bone, but valid. The right > > > > > people are engineers who wish to pick this project up for their > > > > > benefit, yes antti as well as mine. The engineer would be some on= e > > > > > willing to pay a bit extra for one of four boards available with = all > > > > > the design file associated with the boards. These files are the m= eat > > > > > of the work and would allow an engineer to make changes from the > > > > > current form to one more suitable to their needs, if necessary. O= pen > > > > > Source license also allows anyone willing to manufacture this pro= duct > > > > > for sale and profit of their own, royalty free. Development and > > > > > testing is a huge cost and has been paid for in this project. Yes= , > > > > > antti schematics are available for many of the development boards= but > > > > > firmware and how things are implemented are not. Digilent for exa= mple > > > > > produced a project that only required a usb to miniB connection t= o the > > > > > board to program utilizing Xilinx's impact program, how did they = do > > > > > that? They will not tell me, I understand, but it was worth askin= g. > > > > > Yes, there are vendors who do not make all of their design files > > > > available for FPGA development boards. =A0But for the most part, th= e > > > > FPGA makers provide development boards and make all of their design > > > > files available. =A0I think they do this to reduce the amount of su= pport > > > > required. =A0If you have all of the design files, you don't need to= ask > > > > so many questions, you can just look it up yourself. =A0So in that > > > > sense, there are a number of open source FPGA development boards. > > > > Just not with the freedom to make your own copies although I can't > > > > imagine an FPGA vendor would object since you would be putting thei= r > > > > parts on it! > > > > > > If the 4 layer printed circuit board was manufactured for $6 is t= hat > > > > > to expensive? > > > > > No one can have a board manufactured for $6. =A0You might be able t= o get > > > > 100 for $600 or possibly even 10 for $60, but not 1 for $6. =A0That= is > > > > one of the problems with open source hardware. =A0It is "hard" and = often > > > > difficult to make on your own. =A0But that does not need to be a > > > > problem. =A0The most successful open source hardware (OSH) project = I > > > > have seen is the Beagle Board which can only be made in pretty > > > > advanced factories. =A0It uses a Package on Package mounting techni= que > > > > for the processor memory as the OMAP CPU used is intended for use i= n > > > > PDAs and cell phone like applications. =A0So clearly, the fact that= you > > > > might have to sell some part or even all of the board would not doo= m > > > > the project as Antti might think. =A0(Not trying to put words in yo= ur > > > > mouth Antti, just making a point). > > > > > In fact, I am thinking about an open source GPS receiver project wh= ich > > > > would require not only the electronic hardware, but also a mechanic= al > > > > design be done. =A0Now *that* can be a problem for open source I > > > > think. > > > > > > My point: is placing all of this projects work in an open source > > > > > license to be easily duplicated at a reasonable cost one board un= der > > > > > $50.00 for someone in need of well behaved electronic signals, ma= ybe > > > > > an engineer, a student, a hobbyist, and the like. Antti, you are = so > > > > > preceptive, Yes, I would like to be able to accept notes of > > > > > appreciation for this body of work, because someone finds it help= ful. > > > > > Being able to discuss this body of work and let it go out to thos= e who > > > > > would find it useful makes me smile. Open Source Hardware licensi= ng > > > > > just prevents anyone from strangling the work and making it their= s, > > > > > plagiarism. This body of work is not quite original but is not a = rip > > > > > off, or a copy of another work. Yes, their are similar projects o= ut > > > > > there and I have asked for help on this project from those simila= r > > > > > project, but understandably I got go away, I did. > > > > > I have spent my resource on this project and I need more to conti= nue > > > > > on or even try something different. > > > > > Have you defined your goals for this project? =A0If you are going t= o > > > > succeed, you need to know what you are trying to do, *clearly*. > > > > Others can give feedback on the goals and you can modify them to > > > > include as many others as possible. =A0Then you will get as much su= pport > > > > as possible. > > > > > Rick > > > > Rick, > > > > beagle is: > > > 1) backed up by TI > > > 2) uses (used) newest components > > > > Cy's design: > > > 1) uses OBSOLETED and NFND components > > > > see the difference? > > > > Cy: doing something different is an option > > > > And as before i am failing to see what you expect to find? > > > > I can only sayd that no "open source" developer will be > > > ordering and assembling those boards for personal use > > > and no company is interested to produce them either > > > > so if somebody makes the boards its only you, and then > > > you have boards with 2 generation too old FPGA that > > > nobody is interested in, and that you can not sell even > > > for break even > > > > Antti > > > I'm not sure what your point is. =A0I am sure there are any number of > > differences between nobody's project and the beagleboard. =A0So? > > > Why do you think the XC3S250E is an obsolete chip? =A0Heck, every chip > > will be off the cutting edge in six months. =A0Personally, I prefer to > > use parts that are not brand new designs, especially with Xilinx. > > They have a reputation for making their products widely available only > > a long time after initial shipments to favored customers. =A0Do you hav= e > > any of the new parts? > > > As to the beagleboard being "backed up" by TI, that really doesn't > > make much of a difference. =A0I have not seen any indication that the > > people making them are financially supported by TI. =A0The fact that th= e > > board can only be made by rather advanced technology assemblers means > > you pretty much *have* to buy these boards rather than making your > > own. =A0I will say that at $150 there is not much incentive to build > > your own, even if you want 100's. =A0A much smaller board that I am > > building and selling in qty 100's, with cheaper parts costs me $100 to > > build. =A0I expect the beagleboard costs close to the selling price, so > > maybe TI *is* supporting the project in some way. > > > My only problem with the beagleboard is that the power consumption is > > too high, and that it has no FPGA ;^) =A0I would like something along > > these lines with an ARM9 processor and memory capable of running > > Linux, all designed for lowest power so it can run from batteries. > > Like a PDA I guess, but more than 6 hours of run time, more like 20 > > hours with a PDA sized display. > > > I wish this was not the FPGA forum. =A0I don't feel I should carry on > > with this discussion here. =A0There are some display technologies I > > would like to discuss. =A0Maybe I'll go over to c.a.e and post there... > > > Rick > > Rick, > when did you last look for information for S3E based boards made by > Xilinx at Xilinx website? > if you have done it recently, go and do some search. This should > answer the issue why > S3e should not be used any more. It's not that bad chip, but S3A is > available at digikey > already for some time now, so there is no reason not to use S3A > S3A > S3AN > S3ADSP > S6 > are all newer than S3E, and i have strong belive that Xilinx really > wants everyone > to use S3A and newer chips for any new designs. Correct me if i am > wrong > about this. I also feel there is no reason to use something as old as > S3E for > new designs (unless there are special reasons todo so) > > Cy's designs uses > > 1 FT245 > 2 CPLD > 3 S3E > 4 Oscillator > 5 spi flash > > need 4 layer PCB and requires external JTAG to bootstrap > > Anttis design would use > 1 FT232R (also used for CLOCK!) > 2 S3E or S3A > 3 spi flash > > and would bootstrap with empty components, and could > be done with 2 layer PCB Why a two layer board? I would expect any decent design to use at least four layers just so it can have a ground/power plane for noise reduction. Especially when you don't know what someone will be doing with it, best is to provide a bit of overkill. I'm not interested in saving every last penny on a development board like this. I will say that Uwe has a point about the 2.5 volt configuration signals of the S3. When the S3 came out they had a number of issues with the I/Os and only a few of them were fixed in the S3. The rest were fixed in the S3E and S3A. But there are often reasons for using older tech chips. My last design used a Lattice XP instead of the XP2 because the XP2 is not available in the 100 pin TQFP package. It costs more to use a higher pin count package and is harder to layout a BGA or CS package as well as requiring more layers and higher cost board. In another design I did some years back, I had to use an old tech chip to get 5 volt tolerance. I had to hunt around quite a bit to find an eval board for it too! I do agree that your ideas are better, I just don't think it is a pointless board that no one else would be interested in. I'm not saying that it is anything great, but I don't think it is complete crap either. RickArticle: 143233
On Sep 27, 11:51=A0pm, n...@puntnl.niks (Nico Coesel) wrote: > "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote: > >On Sep 26, 8:39=3DA0pm, rickman <gnu...@gmail.com> wrote: > >> On Sep 23, 12:57=3DA0pm, "Antti.Luk...@googlemail.com" > > >> <antti.luk...@googlemail.com> wrote: > >> > On Sep 23, 7:38=3DA0pm, rickman <gnu...@gmail.com> wrote: > > >> > > On Sep 23, 11:58=3DA0am, nobody <cydrollin...@gmail.com> wrote: > > >> > > > Antti, > > >> > > > I enjoy your responses they are to the bone, but valid. The righ= t > >> > > > people are engineers who wish to pick this project up for their > >> > > > benefit, yes antti as well as mine. The engineer would be some o= ne > >> > > files available. =3DA0I think they do this to reduce the amount of= supp=3D > >ort > >> > > required. =3DA0If you have all of the design files, you don't need= to a=3D > >sk > >e > >> > > > on or even try something different. > > >> > > Have you defined your goals for this project? =3DA0If you are goin= g to > >> > > succeed, you need to know what you are trying to do, *clearly*. > >> > > Others can give feedback on the goals and you can modify them to > >> > > include as many others as possible. =3DA0Then you will get as much= supp=3D > >ort > >> > > as possible. > > >> > > Rick > > >> Linux, all designed for lowest power so it can run from batteries. > >> with this discussion here. =3DA0There are some display technologies I > >> would like to discuss. =3DA0Maybe I'll go over to c.a.e and post there= ... > > >> Rick > > >Rick, > >when did you last look for information for S3E based boards made by > >Xilinx at Xilinx website? > >if you have done it recently, go and do some search. This should > >answer the issue why > >S3e should not be used any more. It's not that bad chip, but S3A is > >available at digikey > >already for some time now, so there is no reason not to use S3A > >S3A > >S3AN > >S3ADSP > >S6 > >are all newer than S3E, and i have strong belive that Xilinx really > >wants everyone > > Sorry, but this sounds like a load of crap to me. The S3E is a > perfectly useful chip. Although the pin configuration is more limited > that the standard S3 parts. You seem obsessed with flash. FYI none of > the designs I ever worked on used flash to store the FPGA > configuration. Flash isn't a big deal for everyone. > > -- > Failure does not prove something is impossible, failure simply > indicates you are not using the right tools... > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"If it doesn't fit, use a bigg= er hammer!" > -------------------------------------------------------------- I very seldom call others people comments "load of crap" sure S3e is useful chip, and i have said there could be valid reasons to use it also (if you did read my postings) as of S3AN <> S3A, it doesnt have to be S3AN, S3A is pretty much useable too (or S3ADSP even better), so if you Nico do not like Flash you could use S3A right? "none of the designs you worked did ever use flash to store FPGA configuration" - Nico is it really so? You never used a desgin with Parallel Flash conf? never a design with Serial flash conf? xilinx platform flash is flash too, ever used? did you only use OTP in ALL your designs? maybe.. AnttiArticle: 143234
On Sep 28, 12:48=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > -jg <jim.granvi...@gmail.com> wrote: > > On Sep 28, 4:42=A0am, "Antti.Luk...@googlemail.com" > > <antti.luk...@googlemail.com> > > > > Anttis design would use > > > 1 FT232R (also used for CLOCK!) > > Why not FT2232H here, to "make it as good as you can," ? > > The FT2232H costs more buck and needs more infrastructure. But I perfer i= t > too... > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar= mstadt.de > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- Right Uwe, it does cost a lot of more infrastructure, and is more expensive as chip as well, so thats the reason, for lowest cost it would be FT232R, for perfromance it would be FT2232H or CY7C68013 AnttiArticle: 143235
On Sep 28, 3:39=A0am, rickman <gnu...@gmail.com> wrote: > On Sep 27, 12:42=A0pm, "Antti.Luk...@googlemail.com" > > > > <antti.luk...@googlemail.com> wrote: > > On Sep 26, 8:39=A0pm, rickman <gnu...@gmail.com> wrote: > > > > On Sep 23, 12:57=A0pm, "Antti.Luk...@googlemail.com" > > > > <antti.luk...@googlemail.com> wrote: > > > > On Sep 23, 7:38=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > > On Sep 23, 11:58=A0am, nobody <cydrollin...@gmail.com> wrote: > > > > > > > Antti, > > > > > > > I enjoy your responses they are to the bone, but valid. The rig= ht > > > > > > people are engineers who wish to pick this project up for their > > > > > > benefit, yes antti as well as mine. The engineer would be some = one > > > > > > willing to pay a bit extra for one of four boards available wit= h all > > > > > > the design file associated with the boards. These files are the= meat > > > > > > of the work and would allow an engineer to make changes from th= e > > > > > > current form to one more suitable to their needs, if necessary.= Open > > > > > > Source license also allows anyone willing to manufacture this p= roduct > > > > > > for sale and profit of their own, royalty free. Development and > > > > > > testing is a huge cost and has been paid for in this project. Y= es, > > > > > > antti schematics are available for many of the development boar= ds but > > > > > > firmware and how things are implemented are not. Digilent for e= xample > > > > > > produced a project that only required a usb to miniB connection= to the > > > > > > board to program utilizing Xilinx's impact program, how did the= y do > > > > > > that? They will not tell me, I understand, but it was worth ask= ing. > > > > > > Yes, there are vendors who do not make all of their design files > > > > > available for FPGA development boards. =A0But for the most part, = the > > > > > FPGA makers provide development boards and make all of their desi= gn > > > > > files available. =A0I think they do this to reduce the amount of = support > > > > > required. =A0If you have all of the design files, you don't need = to ask > > > > > so many questions, you can just look it up yourself. =A0So in tha= t > > > > > sense, there are a number of open source FPGA development boards. > > > > > Just not with the freedom to make your own copies although I can'= t > > > > > imagine an FPGA vendor would object since you would be putting th= eir > > > > > parts on it! > > > > > > > If the 4 layer printed circuit board was manufactured for $6 is= that > > > > > > to expensive? > > > > > > No one can have a board manufactured for $6. =A0You might be able= to get > > > > > 100 for $600 or possibly even 10 for $60, but not 1 for $6. =A0Th= at is > > > > > one of the problems with open source hardware. =A0It is "hard" an= d often > > > > > difficult to make on your own. =A0But that does not need to be a > > > > > problem. =A0The most successful open source hardware (OSH) projec= t I > > > > > have seen is the Beagle Board which can only be made in pretty > > > > > advanced factories. =A0It uses a Package on Package mounting tech= nique > > > > > for the processor memory as the OMAP CPU used is intended for use= in > > > > > PDAs and cell phone like applications. =A0So clearly, the fact th= at you > > > > > might have to sell some part or even all of the board would not d= oom > > > > > the project as Antti might think. =A0(Not trying to put words in = your > > > > > mouth Antti, just making a point). > > > > > > In fact, I am thinking about an open source GPS receiver project = which > > > > > would require not only the electronic hardware, but also a mechan= ical > > > > > design be done. =A0Now *that* can be a problem for open source I > > > > > think. > > > > > > > My point: is placing all of this projects work in an open sourc= e > > > > > > license to be easily duplicated at a reasonable cost one board = under > > > > > > $50.00 for someone in need of well behaved electronic signals, = maybe > > > > > > an engineer, a student, a hobbyist, and the like. Antti, you ar= e so > > > > > > preceptive, Yes, I would like to be able to accept notes of > > > > > > appreciation for this body of work, because someone finds it he= lpful. > > > > > > Being able to discuss this body of work and let it go out to th= ose who > > > > > > would find it useful makes me smile. Open Source Hardware licen= sing > > > > > > just prevents anyone from strangling the work and making it the= irs, > > > > > > plagiarism. This body of work is not quite original but is not = a rip > > > > > > off, or a copy of another work. Yes, their are similar projects= out > > > > > > there and I have asked for help on this project from those simi= lar > > > > > > project, but understandably I got go away, I did. > > > > > > I have spent my resource on this project and I need more to con= tinue > > > > > > on or even try something different. > > > > > > Have you defined your goals for this project? =A0If you are going= to > > > > > succeed, you need to know what you are trying to do, *clearly*. > > > > > Others can give feedback on the goals and you can modify them to > > > > > include as many others as possible. =A0Then you will get as much = support > > > > > as possible. > > > > > > Rick > > > > > Rick, > > > > > beagle is: > > > > 1) backed up by TI > > > > 2) uses (used) newest components > > > > > Cy's design: > > > > 1) uses OBSOLETED and NFND components > > > > > see the difference? > > > > > Cy: doing something different is an option > > > > > And as before i am failing to see what you expect to find? > > > > > I can only sayd that no "open source" developer will be > > > > ordering and assembling those boards for personal use > > > > and no company is interested to produce them either > > > > > so if somebody makes the boards its only you, and then > > > > you have boards with 2 generation too old FPGA that > > > > nobody is interested in, and that you can not sell even > > > > for break even > > > > > Antti > > > > I'm not sure what your point is. =A0I am sure there are any number of > > > differences between nobody's project and the beagleboard. =A0So? > > > > Why do you think the XC3S250E is an obsolete chip? =A0Heck, every chi= p > > > will be off the cutting edge in six months. =A0Personally, I prefer t= o > > > use parts that are not brand new designs, especially with Xilinx. > > > They have a reputation for making their products widely available onl= y > > > a long time after initial shipments to favored customers. =A0Do you h= ave > > > any of the new parts? > > > > As to the beagleboard being "backed up" by TI, that really doesn't > > > make much of a difference. =A0I have not seen any indication that the > > > people making them are financially supported by TI. =A0The fact that = the > > > board can only be made by rather advanced technology assemblers means > > > you pretty much *have* to buy these boards rather than making your > > > own. =A0I will say that at $150 there is not much incentive to build > > > your own, even if you want 100's. =A0A much smaller board that I am > > > building and selling in qty 100's, with cheaper parts costs me $100 t= o > > > build. =A0I expect the beagleboard costs close to the selling price, = so > > > maybe TI *is* supporting the project in some way. > > > > My only problem with the beagleboard is that the power consumption is > > > too high, and that it has no FPGA ;^) =A0I would like something along > > > these lines with an ARM9 processor and memory capable of running > > > Linux, all designed for lowest power so it can run from batteries. > > > Like a PDA I guess, but more than 6 hours of run time, more like 20 > > > hours with a PDA sized display. > > > > I wish this was not the FPGA forum. =A0I don't feel I should carry on > > > with this discussion here. =A0There are some display technologies I > > > would like to discuss. =A0Maybe I'll go over to c.a.e and post there.= .. > > > > Rick > > > Rick, > > when did you last look for information for S3E based boards made by > > Xilinx at Xilinx website? > > if you have done it recently, go and do some search. This should > > answer the issue why > > S3e should not be used any more. It's not that bad chip, but S3A is > > available at digikey > > already for some time now, so there is no reason not to use S3A > > S3A > > S3AN > > S3ADSP > > S6 > > are all newer than S3E, and i have strong belive that Xilinx really > > wants everyone > > to use S3A and newer chips for any new designs. Correct me if i am > > wrong > > about this. I also feel there is no reason to use something as old as > > S3E for > > new designs (unless there are special reasons todo so) > > > Cy's designs uses > > > 1 FT245 > > 2 CPLD > > 3 S3E > > 4 Oscillator > > 5 spi flash > > > need 4 layer PCB and requires external JTAG to bootstrap > > > Anttis design would use > > 1 FT232R (also used for CLOCK!) > > 2 S3E or S3A > > 3 spi flash > > > and would bootstrap with empty components, and could > > be done with 2 layer PCB > > Why a two layer board? =A0I would expect any decent design to use at > least four layers just so it can have a ground/power plane for noise > reduction. =A0Especially when you don't know what someone will be doing > with it, best is to provide a bit of overkill. =A0I'm not interested in > saving every last penny on a development board like this. > > I will say that Uwe has a point about the 2.5 volt configuration > signals of the S3. =A0When the S3 came out they had a number of issues > with the I/Os and only a few of them were fixed in the S3. =A0The rest > were fixed in the S3E and S3A. > > But there are often reasons for using older tech chips. =A0My last > design used a Lattice XP instead of the XP2 because the XP2 is not > available in the 100 pin TQFP package. =A0It costs more to use a higher > pin count package and is harder to layout a BGA or CS package as well > as requiring more layers and higher cost board. =A0In another design I > did some years back, I had to use an old tech chip to get 5 volt > tolerance. =A0I had to hunt around quite a bit to find an eval board for > it too! > > I do agree that your ideas are better, I just don't think it is a > pointless board that no one else would be interested in. =A0I'm not > saying that it is anything great, but I don't think it is complete > crap either. > > Rick Rick I did not say its "complete crap" as you say look here, an USB-FPGA design with 100% open design schematic based on S3E http://www.oho-elektronik.de/index.php?c=3D1&s=3Dindex as with Cy's its not perfect (the TUSB3410 is NFND) but i do not call it crap the GODIL can be used as USB connected FPGA gadgets without any need for USB drivers mess, it can be easily achived by using source code and DLL/drivers from the code archive from Elektor (12/2004 file name 040334-11.zip) provided are sources for Delphi demo, tested to work, i implemented USB EEPROM programmer by adding only 5 lines of code also useable with VB, provided is Word example for that as of XP vs XP2, yeah i have some XP2 samples, but have used XP so far, the selection of packages is important AnttiArticle: 143236
On Sep 28, 1:52=A0am, -jg <jim.granvi...@gmail.com> wrote:
> On Sep 28, 9:48=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu-
>
> darmstadt.de> wrote:
> > -jg <jim.granvi...@gmail.com> wrote:
> > > Why not FT2232H here, to "make it as good as you can," ?
>
> > The FT2232H costs more buck and needs more infrastructure. But I perfer=
it
> > too...
>
> =A0 I like the potential for a reasonable rate continual sample, for
> things like PC Frequency counter, Logic analyzer ets, as it's always
> good to have a 'free instrument' =A0or two, in any development kit, and
> especially so for teaching.
> =A0{ We've been getting quite good results from SoundCards, on the 'free
> instrument' front, (but with obvious bandwidth ceilings) }
>
> -jg
Jim,
for those who are looking for dirt cheap usb locic and protocol
analyzer FX2 chips provide a easy solution
i first found this in some german forums, but later trapped onto this
http://www.6-lab.com/index.php/projectlist/logicu
logic-U-Plus is GENERIC FX2 board that can be configured
to emulate either Locic from
www.saleae.com
or
USBee AX Pro from
www.usbee.com
well, I have relation to those folks, and not promoting
any such use, but well, such "solutions" are available
and far more easy to use then making own logic
analyzer based on FT2232H
Antti
Article: 143237
On Sep 28, 9:28=A0am, "Antti.Luk...@googlemail.com"
<antti.luk...@googlemail.com> wrote:
> On Sep 28, 1:52=A0am, -jg <jim.granvi...@gmail.com> wrote:
>
>
>
> > On Sep 28, 9:48=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu-
>
> > darmstadt.de> wrote:
> > > -jg <jim.granvi...@gmail.com> wrote:
> > > > Why not FT2232H here, to "make it as good as you can," ?
>
> > > The FT2232H costs more buck and needs more infrastructure. But I perf=
er it
> > > too...
>
> > =A0 I like the potential for a reasonable rate continual sample, for
> > things like PC Frequency counter, Logic analyzer ets, as it's always
> > good to have a 'free instrument' =A0or two, in any development kit, and
> > especially so for teaching.
> > =A0{ We've been getting quite good results from SoundCards, on the 'fre=
e
> > instrument' front, (but with obvious bandwidth ceilings) }
>
> > -jg
>
> Jim,
>
> for those who are looking for dirt cheap usb locic and protocol
> analyzer FX2 chips provide a easy solution
>
> i first found this in some german forums, but later trapped onto thishttp=
://www.6-lab.com/index.php/projectlist/logicu
>
> logic-U-Plus is GENERIC FX2 board that can be configured
> to emulate either Locic fromwww.saleae.com
> or
> USBee AX Pro fromwww.usbee.com
>
> well, I have relation to those folks, and not promoting
> any such use, but well, such "solutions" are available
> and far more easy to use then making own logic
> analyzer based on FT2232H
>
> Antti
OOOOOOOOOOOOOPS
CORRECTION: I have NO relation to any of those folks,
monday morning, before cofee ;)
the software from saleae/usbee is licensed for free use
only with the hardware purchased from the official
resellers, any other use is not allowed.
I'd better take a break before posting any more
Antti
PS there is place for anything and everyone
if i say something could be done better, it
doesnt mean things done otherwise are
bad to the bones, or that i could them better
myself, anything that is done, completed
and useable is something good already
no matter the techncal solutions are
Article: 143238
On Sep 28, 6:28=A0pm, "Antti.Luk...@googlemail.com"
<antti.luk...@googlemail.com> wrote:
> On Sep 28, 1:52=A0am, -jg <jim.granvi...@gmail.com> wrote:
>
> > On Sep 28, 9:48=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu-
>
> > darmstadt.de> wrote:
> > > -jg <jim.granvi...@gmail.com> wrote:
> > > > Why not FT2232H here, to "make it as good as you can," ?
>
> > > The FT2232H costs more buck and needs more infrastructure. But I perf=
er it
> > > too...
>
> > =A0 I like the potential for a reasonable rate continual sample, for
> > things like PC Frequency counter, Logic analyzer ets, as it's always
> > good to have a 'free instrument' =A0or two, in any development kit, and
> > especially so for teaching.
> > =A0{ We've been getting quite good results from SoundCards, on the 'fre=
e
> > instrument' front, (but with obvious bandwidth ceilings) }
>
> > -jg
>
> Jim,
>
> for those who are looking for dirt cheap usb locic and protocol
> analyzer FX2 chips provide a easy solution
>
> i first found this in some german forums, but later trapped onto thishttp=
://www.6-lab.com/index.php/projectlist/logicu
>
> logic-U-Plus is GENERIC FX2 board that can be configured
> to emulate either Locic fromwww.saleae.com
> or
> USBee AX Pro fromwww.usbee.com
Those are not cheap, nor are they chips - and cannot pgm the FPGA
out of the box... - as this thread is about FPGA boards, my comments
were in that context.
ie what can do the PGM pathway _and_ give other runtime information,
almost for free.
In such single unit products, the incremental chip price variation is
not
material.
- Digikey shows the saving to be a princely $1 ;)
So, give the user a choice of much faster download times, and the
potential? for a free Logic/Frequency HW pathway, all for $1 more,
and
what would they choose ?
Article: 143239Dek <daniele.dequal@gmail.com> writes: > Hi all, > > I'm new to this group and I'd like to ask you some help with my > design. Actually I'm testing a double median filter implemented in a > Virtex5 FPGA. To chek it in different situation I tought to use an > ChipScope Pro ILA core to store a set of data (32 x 10 x 1024 bit) and > use them as stimuli for my device, finally storing the output (32 x 1 > x 1024bit) in another ILA core. The data I'd like to use for this test > are stored in .txt files. The point is: > > 1) Is it possible to pass data from a .txt file to a ILA core? > 2) If so, can you suggest me how to do that? When you say you're testing using ILA - have you tested on a simulator first? You'll be vastly more productive there while developing the code, as compiles are much quicker and you can probe all the signals you want. If you *have* done this and want to test it in the real hardware as well, then you might be able to wire up a VIO interface and control it from a TCL script to send data into your core (slowly) and use the ILA to capture the output. But, unless you think something is actually wrong with the synthesis, my experience is that testing hardware in that way is not very valuable. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 143240
On 28 Set, 11:27, Martin Thompson <martin.j.thomp...@trw.com> wrote: > Dek <daniele.deq...@gmail.com> writes: > > Hi all, > > > I'm new to this group and I'd like to ask you some help with my > > design. Actually I'm testing a double median filter implemented in a > > Virtex5 FPGA. To chek it in different situation I tought to use an > > ChipScope Pro ILA core to store a set of data (32 x 10 x 1024 bit) and > > use them as stimuli for my device, finally storing the output (32 x 1 > > x 1024bit) in another ILA core. The data I'd like to use for this test > > are stored in .txt files. The point is: > > > 1) Is it possible to pass data from a .txt file to a ILA core? > > 2) If so, can you suggest me how to do that? > > When you say you're testing using ILA - have you tested on a simulator > first? =A0You'll be vastly more productive there while developing the cod= e, > as compiles are much quicker and you can probe all the signals you want. > > If you *have* done this and want to test it in the real hardware as > well, then you might be able to wire up a VIO interface and control it > from a TCL script to send data into your core (slowly) and use the ILA > to capture the output. > > But, unless you think something is actually wrong with the synthesis, my > experience is that testing hardware in that way is not very valuable. > > Cheers, > Martin > > -- > martin.j.thomp...@trw.com > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://w= ww.conekt.net/electronics.html Thanks all for the reply; I had simulated the code using Modelsim, now I'll try to repeat the simulation with ISE. I will also read the data2mem manual, but I'm wondering if the Jtag cable is fast enough to pass data to be simuleted at clock speed. If not I will always need to store data temporary into BRAM, also if I use Matlab (Anyway this possibility is very interesting, do you have any reference about useing Matlab +SysGen?). Thanks againArticle: 143241
Hi everyone, First of all im a noob in VHDL, i only know the basic. But I have a project that its really hard for me. I hope that you guys could help me, im going to explain the project: We have to use a keyboard to input any data on a spartan 3E and show that info on the LCD display, then send that info to another spartan 3E, we should see the received data on the LCD display too. Then we have to input any data on the second spartan and send it back to the first one, all the info need to be display on boths LCD. The communication between the two Spartans should be wireless but if you think that is too hard then i think that we can use a wired communication. I have read that we have to use something abouts sockets and microblaze but im not sure at all. Thank You for your time!!Article: 143242
rickman <gnuarm@gmail.com> wrote: > On Sep 27, 12:42 pm, "Antti.Luk...@googlemail.com" > <antti.luk...@googlemail.com> wrote: > > On Sep 26, 8:39 pm, rickman <gnu...@gmail.com> wrote: > > > > > > I enjoy your responses they are to the bone, but valid. The right <zillions of line of senseless quote delete> Do people ever use archived news and get angry about unrelated quote meaning unrelated search hits? > Why a two layer board? I would expect any decent design to use at > least four layers just so it can have a ground/power plane for noise > reduction. Especially when you don't know what someone will be doing > with it, best is to provide a bit of overkill. I'm not interested in > saving every last penny on a development board like this. With programmable pin helping the layouter to get a planar layout, the bottom layer can be made quite a continous groundplane. .. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 143243
Hi, I am having the following sparkfun board which has XC3S500E + AT45DB161D on it. http://www.sparkfun.com/commerce/product_info.php?products_id=8458 The FPGA is working (a LED blink bit file works as expected). But when i generate a MCS file (as per xapp974.pdf) to program the config flash, i get various errors. 1) Indirect SPI (with Impact 9.2.4i with USB cable) Impact does not show the SPI flash as attached device when i add the bit file with "Enable programming of the attached SPI device attached to this FPGA" radio button. when i again assign the bit file, it says "Device selected does not support BPI/SPI..." Does ISE9.2.4i support Indirect SPI for XC3s500e ? 2) Direct SPI (with a header soldered to the Flash chip) Gives error -> Impact 2595 "device validation terminated" 3) Downloaded and tweaked the S3ESK Picoblaze Serial port programmer from Xilinx website. This is meant for M25P16 flash on the EDK board. so in spite of serial port saying "OK" after dumping the mcs file, all the locations were blank (0xFF). I guess its the different command set that is causing problem. 4) The "load_prom.sh" in the attached Python script at sparkfun gives an error of "xilprg" command not found. i could not find any xilprg (only cblsrv at sourceforge) i guess it supports ony parallel -3 cable. I am using ISE 9.2.4i with USB prog cable (using libusb-driver) on Suse11. Anything wrong with my setup ? or is the SPI prom usage being discouraged by Xilinx ? ThanksArticle: 143244
> Do people ever use archived news and get angry about unrelated quote mean= ing > unrelated search hits? > > > Why a two layer board? =A0I would expect any decent design to use at > > least four layers just so it can have a ground/power plane for noise > > reduction. =A0Especially when you don't know what someone will be doing > > with it, best is to provide a bit of overkill. =A0I'm not interested in > > saving every last penny on a development board like this. > > With programmable pin helping the layouter to get a planar layout, the > bottom layer can be made quite a continous groundplane. > > .. > > Bye > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar= mstadt.de > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- please complain to the GOOGLE (and saying that use something else isnt an option always, sorry... I use what is the easiest way) when replying using google news its not easy to delete the rubish as it not even seen on screen well, i see the thread is reached status where people start to complain about quoting issues, :( AnttiArticle: 143245
> > logic-U-Plus is GENERIC FX2 board that can be configured > > to emulate either Locic fromwww.saleae.com > > or > > USBee AX Pro fromwww.usbee.com > > Those are not cheap, nor are they chips - and cannot pgm the FPGA > out of the box... - as this thread is about FPGA boards, my comments > were in that context. > > ie what can do the PGM pathway _and_ give other runtime information, > almost for free. > In such single unit products, the incremental chip price variation is > not > material. > =A0- Digikey shows the saving to be a princely $1 ;) > > =A0So, give the user a choice of much faster download times, and the > potential? for a free Logic/Frequency HW pathway, all for $1 more, > and > what would they choose ? Jim, 1) FT2232H prices have gone down a great deal, I wasnt even aware well, if Cy would 1) remove the CPLD from the design this would be GOOD 2) replace FT245 with FT2232H this would be GOOD also but [2] is optional :) AnttiArticle: 143246
Actually, I'm now comparing the partial bitstream files ... However, 4 LUT out of 8 within one CLB are in the same frame, so there are 16 (bits per LUT) * 4 * 16 (CLBs per frame) means 1024 bits (out of 1312 bits) in a frame are dedicated to LUT truth table. On Sep 24, 11:53=A0am, austin <aus...@xilinx.com> wrote: > im, > > Why? ( I am curious) > > One easy way to find things is to use FPGA_editor to create two > identical designs, with different logic equations in the LUT of > interest. =A0Use "diff" (or equivalent) to find the difference in the > two bitstreams. > > AustinArticle: 143247
On Sep 28, 12:16=A0am, "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote: > On Sep 27, 11:51=A0pm, n...@puntnl.niks (Nico Coesel) wrote: > > > > > "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote: > > >On Sep 26, 8:39=3DA0pm, rickman <gnu...@gmail.com> wrote: > > >> On Sep 23, 12:57=3DA0pm, "Antti.Luk...@googlemail.com" > > > >> <antti.luk...@googlemail.com> wrote: > > >> > On Sep 23, 7:38=3DA0pm, rickman <gnu...@gmail.com> wrote: > > > >> > > On Sep 23, 11:58=3DA0am, nobody <cydrollin...@gmail.com> wrote: > > > >> > > > Antti, > > > >> > > > I enjoy your responses they are to the bone, but valid. The ri= ght > > >> > > > people are engineers who wish to pick this project up for thei= r > > >> > > > benefit, yes antti as well as mine. The engineer would be some= one > > >> > > files available. =3DA0I think they do this to reduce the amount = of supp=3D > > >ort > > >> > > required. =3DA0If you have all of the design files, you don't ne= ed to a=3D > > >sk > > >e > > >> > > > on or even try something different. > > > >> > > Have you defined your goals for this project? =3DA0If you are go= ing to > > >> > > succeed, you need to know what you are trying to do, *clearly*. > > >> > > Others can give feedback on the goals and you can modify them to > > >> > > include as many others as possible. =3DA0Then you will get as mu= ch supp=3D > > >ort > > >> > > as possible. > > > >> > > Rick > > > >> Linux, all designed for lowest power so it can run from batteries. > > >> with this discussion here. =3DA0There are some display technologies = I > > >> would like to discuss. =3DA0Maybe I'll go over to c.a.e and post the= re... > > > >> Rick > > > >Rick, > > >when did you last look for information for S3E based boards made by > > >Xilinx at Xilinx website? > > >if you have done it recently, go and do some search. This should > > >answer the issue why > > >S3e should not be used any more. It's not that bad chip, but S3A is > > >available at digikey > > >already for some time now, so there is no reason not to use S3A > > >S3A > > >S3AN > > >S3ADSP > > >S6 > > >are all newer than S3E, and i have strong belive that Xilinx really > > >wants everyone > > > Sorry, but this sounds like a load of crap to me. The S3E is a > > perfectly useful chip. Although the pin configuration is more limited > > that the standard S3 parts. You seem obsessed with flash. FYI none of > > the designs I ever worked on used flash to store the FPGA > > configuration. Flash isn't a big deal for everyone. > > > -- > > Failure does not prove something is impossible, failure simply > > indicates you are not using the right tools... > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"If it doesn't fit, use a bi= gger hammer!" > > -------------------------------------------------------------- > > I very seldom call others people comments "load of crap" > sure S3e is useful chip, and i have said there could > be valid reasons to use it also (if you did read my postings) > as of S3AN <> S3A, it doesnt have to be S3AN, S3A > is pretty much useable too (or S3ADSP even better), > so if you Nico do not like Flash you could use S3A right? > > "none of the designs you worked did ever use flash to store > FPGA configuration" - Nico is it really so? You never > used a desgin with Parallel Flash conf? > never a design with Serial flash conf? > xilinx platform flash is flash too, ever used? > > did you only use OTP in ALL your designs? I think the point is that it is often that the design does not use the FPGA standalone. It is very common that the FPGA is programmed by an MCU or other process and does not require any separate memory of any kind for the FPGA. I find that most of my FPGA designs are just that way, but it is not uncommon for my work to need dedicated memory for configuring the FPGA as well. I think in larger systems this is often not the case however. RickArticle: 143248
On Sep 28, 7:58=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > rickman <gnu...@gmail.com> wrote: > > On Sep 27, 12:42=A0pm, "Antti.Luk...@googlemail.com" > > <antti.luk...@googlemail.com> wrote: > > > On Sep 26, 8:39=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > > > I enjoy your responses they are to the bone, but valid. The r= ight > > <zillions of line of senseless quote delete> > > Do people ever use archived news and get angry about unrelated quote mean= ing > unrelated search hits? > > > Why a two layer board? =A0I would expect any decent design to use at > > least four layers just so it can have a ground/power plane for noise > > reduction. =A0Especially when you don't know what someone will be doing > > with it, best is to provide a bit of overkill. =A0I'm not interested in > > saving every last penny on a development board like this. > > With programmable pin helping the layouter to get a planar layout, the > bottom layer can be made quite a continous groundplane. Yes, that is true, but not my point. A single ground plane does nothing to reduce noise on the power rails. The capacitor that is formed by parallel planes spaced 10 mil in a PWB is the best power supply decoupling device you can provide. Even on a very small board, these planes provide significant noise elimination, both in terms of minimizing the effect on the chips and also in terms of reducing EMI. I realize that many designs just don't have a need for this, but my point was that a general purpose development/eval board needs to consider a wide range of designs including ones that push the speed of the device and have a number of outputs switching at high edge rates. Capacitors alone will not normally address the problem adequately in these cases. RickArticle: 143249
On Sep 28, 8:23=A0am, "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote: > > Do people ever use archived news and get angry about unrelated quote me= aning > > unrelated search hits? > > > > Why a two layer board? =A0I would expect any decent design to use at > > > least four layers just so it can have a ground/power plane for noise > > > reduction. =A0Especially when you don't know what someone will be doi= ng > > > with it, best is to provide a bit of overkill. =A0I'm not interested = in > > > saving every last penny on a development board like this. > > > With programmable pin helping the layouter to get a planar layout, the > > bottom layer can be made quite a continous groundplane. > > > .. > > > Bye > > -- > > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-d= armstadt.de > > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- > > please complain to the GOOGLE (and saying that use something > else isnt an option always, sorry... I use what is the easiest way) > when replying using google news its not easy to delete the rubish > as it not even seen on screen > > well, i see the thread is reached status where people start to > complain > about quoting issues, :( If you are using Google Groups, I hope you are clicking the spam and reporting it. Google seems to continue to make this easier. The last time I noticed, you had to open the "opions" and click "report the message", then type at least "spam" into the edit box. Now I see that there is a link at the bottom of the post where you can just click once. It even confirms that the report has been accepted! How much easier can it get? Rick
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