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I guess it depends on where you look at it. From the section title and the contents I assumed that this was an IP- core with tri-state output. Three pins go to tri-state IOBUF. TTRI controls the enable pin of output buffer (which is supposed to be an output for the IP-core, in this case). Figure 3.1 in Page 64 of the psf_rm.pdf document says it. What am I missing?. Why would anyone need an enable pin input along with separate In and Out ports? a tri-state buffer should be controlled by the IP-core of the buffer (owner is IP-core). They might be describing an output port controlled by an external device, on the other hand. But the text does not say it so. On 27 Temmuz, 05:52, "MM" <mb...@yahoo.com> wrote: > Seems to be a description of a tri-state buffer. TTRI is just an enable p= in > of the buffer, so it should be an input. > > /Mikhail > > "monurlu" <monu...@gmail.com> wrote in message > > news:bb0754fa-0a90-4e5c-8a40-a36987b65c42@t13g2000yqt.googlegroups.com... > Hi, > In psf_rm.pdf document (Xilinx EDK 9.02), there are some examples in > section "Tri-state (InOut and Output) Signals". In the example under > the title "Tri-state (In/Out) With Single-Bit Enable With Freely Named > Ports" a mpd file is given as > BEGIN tri_state_single > =A0 OPTION IPTYPE=3DIP > =A0 PARAMETER C_WIDTH=3D9, DT=3Dinteger > =A0 PORT IPIO=3D=93=94, DIR=3DIO,VEC=3D[0:C_WIDTH-1],THREE_STATE=3DTRUE, = TRI_I=3DITRI, > =A0 TRI_O=3DOTRI, TRI_T=3DTTRI > =A0 PORT ITRI=3D=94=94, DIR=3DI, VEC=3D[0:C_WIDTH-1] > =A0 PORT OTRI=3D=94=94, DIR=3DO, VEC=3D[0:C_WIDTH-1] > =A0 PORT TTRI=3D=94=94, DIR=3DI > END > I noticed that PORT TTRI=3D"" DIR=3DI line has the direction marked as > Input. Is it supposed to be O? Very same is done in the example > following this one too. I couldn't find any example mpd file doing the > same thing and assumed that this is a typo. > Thanks for any help/directionArticle: 142151
http://www.fpga-faq.org/FPGA_Boards.shtmlArticle: 142152
Andy Peters <google@latke.net> writes: > I suppose I could go back to scripts and Makefiles, but EDK adds > another whole level of bullshit to the process and that makes it > difficult to use without the GUI. I've integrated XPS acceptably (not perfectly :) into my script-driven flow. As EDK is makefile controlled, I have: xbash -c "cd some_xps_dir && make -f system.make netlist program" at the start of my synth/PAR script. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 142153
On Jul 27, 12:08=A0am, Mark McDougall <ma...@vl.com.au> wrote: > Gee, that's quite efficient from a coding POV, and makes it much more > readable too! (Not) Efficient compared to what, integrating a non-standard pre-processor into all of my tool flows? And training everyone else that will ever touch/review/reuse any of my code how to use it and integrate it into their flows? Oh, yeah, I forgot; you only have one tool and nobody else to worry about. Obviously, a generate statement remains the easiest way to control an entire module. But if you need to implement variant functionality at much lower levels, gating things with constants/generics is simpler and easier. For instance, using constant/generic masks makes getting rid of unused bits and controlling writeability in control/status registers much easier to write/read/review/maintain. And if a control register bit that enables a variant function is gated off in the control register, guess what happens to the code that implements that function? If a state in a state machine is not reachable due to constant/generic inputs, a good synthesizer will optimize that state away. I suggest you learn more about the language and how to use what it already has before you go off and roll your own, unless you want to stay on your own. Otherwise, you are completely free to pre-process and ifdef all of the above away. AndyArticle: 142154
Just wondering if anyone has come across this: Simulating an Altera scfifo in ModelSim 6.4a for Quartus II 9.0 and if either the sclr or aclr inputs are asserted, the FIFO's output becomes X's forever more. I can work around it, but it's obviously not correctly simulating. Other than this odd behavior, the FIFO sims correctly. Any ideas? Thanks, PeteArticle: 142155
Nevermind ... problems with my write-validation logic ... -- Pete On Jul 27, 10:45=A0am, Peter Sommerfeld <psommerf...@gmail.com> wrote: > Just wondering if anyone has come across this: > > Simulating an Altera scfifo in ModelSim 6.4a for Quartus II 9.0 and if > either the sclr or aclr inputs are asserted, the FIFO's output becomes > X's forever more. > > I can work around it, but it's obviously not correctly simulating. > Other than this odd behavior, the FIFO sims correctly. > > Any ideas? > > Thanks, PeteArticle: 142156
On Fri, 24 Jul 2009 10:08:19 -0700, Andy Peters wrote: > On Jul 24, 1:17Â am, luudee <rudolf.usselm...@gmail.com> wrote: >> On Jul 23, 12:36Â am, Andy Peters <goo...@latke.net> wrote: >> >> > I installed the full-up Xilinx ISE 11.x tools on a spare machine so I >> > could give it a test-drive. (We have a site license.) >> >> ... >> >> > I opened a WebCase, which I suspect will be ignored like every other >> > WebCase. >> >> > -a >> >> Well, Andy, I hate to say that, but it is your own fault. Perhaps you >> are a new user ... > > No, actually, I've being doing this for a long time -- remember XACT? > >> Using anything but only the fundamental features of the tools is asking >> for trouble. Even when just using the fundamental tools like "map >> <option>" in a perl script you will see that they tend to rename and >> change the way some switches work from release to release. > > I realize that things change all the time, which is why I like to > minimize my dependency on the tools. But unfortunately, that's not > always possible. And this little archiving feature was one of Xilinx' > better ideas, which is probably why they shitcanned it. I have one word for you, cvs. I would never use a vendor specific source control system when there are so many first class open source choices available. I prefer good old cvs because it's transparent, i.e. it doesn't use any binary databases it just uses the regular file system and a few text base files. It's also completely reliable across platforms, all of my systems are Linux based while my partner uses cygwin on XP and we have no problem sharing files. You could also use svn or git, I don't like svn and I've never tried git but they are all free and packaged with the major distros so you can make your own choice.Article: 142157
Has anyone seen issues with loading _some_ .bit files from SPI flash on Lattice EC parts ? What I'm seeing with my board, on powerup, there's a burst of SCLK pulses about 400ms, just like you get when loading normally, but DONE never goes high. I wonder if maybe the CRC is wrong? I've tried SST and ST flash chips, and verified the chip content against the .bit file on a device programmer. The same .bit file will program & run fine over JTAG, just won't load from flash, and .bit files for other projects will load OK from the SPI flash on the same board. I've eliminated power supply startup issues, and tried on multiple boards. Signals & power to the SPI flash look clean so data corruption between the flash and the FPGA seems unlikely (it is being programmed and verified via the same FPGA pins by ISPVM) I've tried ISPLever 7.2 SP1 and SP2. If by chance anyone has a LFEC3 (TQ144) board to hand that they'd be willing to try loading the file into, that would be really useful to definitively prove whether it's the file or my board. - please email mike@whitewing.co.uk if so. I've submitted a tech support request to Lattice - not heard back yet.Article: 142158
> Andy wrote: > >> For example, if you gate all the interface signals to a module with a >> generic/constant, the synthesis tool will not implement one gate/flop >> of it (leave the clock and reset alone, they'll go away by themselves). Mark McDougall wrote: > Gee, that's quite efficient from a coding POV, and makes it much more > readable too! (Not) The only reason I read code is to reuse it or to change it. In either case, knowing all of the available options is a good thing. -- Mike TreselerArticle: 142159
if you installed ISE 11 using a symbolically linked directory (instead of a "real" directory) something could not work. xilinxupdate failed to me with message: > "XilinxUpdate is unable to determine the current install. This could be due to the following reasons: > 1. You have launched the 32-bit version of XilinxUpdate and you have both the 64-bit and 32-bit versions of the tools. > To correctly update your software, launch the 64-bit version of XilinxUpdate. > 2. You are running XilinxUpdate from an old installation at "<ISE_DESIGN_SUITE_VERSION_1>". > To update the latest installation at "<ISE_DESIGN_SUITE_VERSION_2>", run the XilinxUpdate from that directory." The problem in my case is: <ISE_DESIGN_SUITE_VERSION_1> and <ISE_DESIGN_SUITE_VERSION_2> were the <real directory> and the <symbolically linked directory> I used for the installation. The solution: 0) NOT reinstall all ISE... but... 1) remove the sybolic lynk 2) create an empty directory with the same name and where the symbolic link was... 3) mount the real directory in the empty directory using the --bind option: mount --bind <real directory> <new empty directory> SandroArticle: 142160
Sandro <sdroamt@netscape.net> wrote: > if you installed ISE 11 using a symbolically linked directory (instead > of a "real" directory) something could not work. > xilinxupdate failed to me with message: > > "XilinxUpdate is unable to determine the current install. This could be due to the following reasons: > > 1. You have launched the 32-bit version of XilinxUpdate and you have both the 64-bit and 32-bit versions of the tools. > > To correctly update your software, launch the 64-bit version of XilinxUpdate. > > 2. You are running XilinxUpdate from an old installation at "<ISE_DESIGN_SUITE_VERSION_1>". > > To update the latest installation at "<ISE_DESIGN_SUITE_VERSION_2>", run the XilinxUpdate from that directory." > The problem in my case is: <ISE_DESIGN_SUITE_VERSION_1> and > <ISE_DESIGN_SUITE_VERSION_2> were the <real directory> and the > <symbolically linked directory> I used for the installation. > The solution: > 0) NOT reinstall all ISE... but... > 1) remove the sybolic lynk > 2) create an empty directory with the same name and where the > symbolic link was... > 3) mount the real directory in the empty directory using the --bind > option: > mount --bind <real directory> <new empty directory> I stumbled about that too. After the experience with ISE 10.1 failing to see the free disk space by scanning the output of "df" for "available": > env LANG=C df : Filesystem 1K-blocks Used Available Use% Mounted on > df : Dateisystem 1K???Blöcke Benutzt Verfügbar Ben% Eingehängt auf and explainung things long and repeated and carefully in the webcase I opened, and seeing the flaw again in 10.1.02 and 10.1.03 after explaining again and again, I gave up and move the install directory from symbolic to non-symbolic. How many ISE programmer do you think understand about symbolic links? And even if they would understand, how many of the first-level webcase workers have ever heard about symbolic links and are able to forward your comments in a sensible way? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 142161
..there were actually -3- non-spam posts in a row! ;) -Dave PollumArticle: 142162
Hi, i'm using ise 9.2i for my design, and the PAR runs successfully meeting all my constraints with no timing errors, but the simulation reports multiple warnings of hold/setup violation, what is the problem?Article: 142163
Hi, I am trying to implement a bram using the "BRAM_SDP_MACRO" in Virtex5 fpga on ML561 board using ISE 10.1 I want to write an array of data into it and then read it back to verify that the data was written correctly. What are the different ways of doing this? To start with, I have written a verilog code and am also using the template I found in the "Virtex-5 Libraries Guide". Using a 4-bit counter I write data into to the bram and later use a slower clock to read the data back to be diplayed on the seven-segment display one after the other. But I dont see any thing other than all the segments glowing, no matter how many read-clocks pass. I think this means, my output data is stuck at all 0s and is not changing at all. Can anyone please help me solve this? Thank you. Shamanth.Article: 142164
On Jul 28, 2:29=A0am, Dave Pollum <vze24...@verizon.net> wrote: > ..there were actually -3- non-spam posts in a row! ;) > -Dave Pollum only 3? in GG I count last 13 in a row as non spam :) AnttiArticle: 142165
On Jul 28, 4:14=A0am, "shamanth" <shamant...@gmail.com> wrote: > Hi, > > I am trying to implement a bram using the "BRAM_SDP_MACRO" in Virtex5 fpg= a > on ML561 board using ISE 10.1 > > I want to write an array of data into it and then read it back to verify > that the data =A0was written correctly. What are the different ways of do= ing > this? > > To start with, I have written a verilog code and am also using the > template I found in the "Virtex-5 Libraries Guide". Using a 4-bit counter= I > write =A0data into to the bram and later use a slower clock to read the d= ata > back to be diplayed on the seven-segment display one after the other. But= I > dont see any thing other than all the segments glowing, no matter how man= y > read-clocks pass. I think this means, my output data is stuck at all 0s a= nd > is not changing at all. > > Can anyone please help me solve this? > > Thank you. > > Shamanth. Hi yes. our super duper STUDENT get-me started consultation fee is flat 100$, paypal, in advance. BTW, I am not so joking about this, there is at least one happy student already, well he had little more complicated issue, so he was also happy to pay extra 100$ for another help session. AnttiArticle: 142166
On Jul 27, 11:45=A0pm, Uwe Bonnes >
>...
> How many ISE programmer do you think understand about symbolic links?
I hope almost all programmer directly involved in the ISE unix/linux
porting... ;-)
> And even if they would understand, how many of the first-level webcase wo=
rkers
> have ever heard about symbolic links
maybe very few but is normal for a first-level "help-desk"
> and are able to forward your comments in a sensible way?
it depends on how smart are the "help-desk"-guys and on how much easy
is to "explain a tecnical stuff to a not much skilled person"
I didn't try to open a webcase because
1) I'm a webpack user and I suppose that
free users goes in the very low priority queue
(maybe is not true but I can understand that...)
2) I easily found the solution by myself and then
I hope Xilinx peoples who usually to read this group
could "chime" internally directly about a solution
to a problem that in the unix/linux environment
could be quite common.
Sandro
Article: 142167Hi Mike, at what frequency is your SPI running. You can configure this in the *.lpf file or of course in the Design Planner. The actual frequency used is process/batch dependent since it uses an internal PLL. I think Lattice have specified an inaccuracy of 30%. Does it still fail if you set the load frequency to the lowest value? Other ideas: ----------- I always put 10K pull-ups to 3.3V on the lines to and from the SPI flash. Have you tied any unused flash inputs? (e.g. WP/HOLD to 3.3V on Atmel parts) You can also read a status register over the JTAG port with the Lattice USB thingy and ispVM. Is anything 'interesting' set in this if you read it after flash load fails? I've forgotten the exact feature/function in ispVM. I'll have mine hooked up later today so I'll take a look and post back. Regards, CharlesArticle: 142168
On Sun, 26 Jul 2009 07:18:57 +0000, Jaerder Sousa wrote: > Good Morning. > I want to get started on fpga development, but I cant decide on what > board and gate count to get. > I'm inclined tho the Xilinx spartan boards ( diligent BASYS or the > Nexys2 ) boards. > And linux compatibility for me is a must, since I use linux on my home > pc. > I'm planing to start on simple designs, so i prefer an inexpensive > solution, but well documented. > > I have a background on electronics and i'm currently studying C.S. > > Best Regards > > Jaerder Sousa. Thank you for the advice. I've decided to go for a spartan 3 starter kit. Best Regards!Article: 142169
On Tue, 28 Jul 2009 10:50:48 +0200, Charles Gardiner <invalid@invalid.invalid> wrote: >Hi Mike, > >at what frequency is your SPI running. You can configure this in the >*.lpf file or of course in the Design Planner. The actual frequency used >is process/batch dependent since it uses an internal PLL. I think >Lattice have specified an inaccuracy of 30%. Does it still fail if you >set the load frequency to the lowest value? Default - 2.5MHz. I've tried setting it faster and do see the SPI rate increase once config starts, so it is seeing some of the datastream. >Other ideas: >----------- >I always put 10K pull-ups to 3.3V on the lines to and from the SPI >flash. Have you tied any unused flash inputs? (e.g. WP/HOLD to 3.3V on >Atmel parts) > >You can also read a status register over the JTAG port with the Lattice >USB thingy and ispVM. Is anything 'interesting' set in this if you read >it after flash load fails? I've forgotten the exact feature/function in >ispVM. I'll have mine hooked up later today so I'll take a look and post >back. > >Regards, >Charles I've now tried retargetting the project to a LFEC6 and loaded it on a Lattice devboard with the same result so AFAICS it looks like it's a software issue generating a bad CRC on the bit file.Article: 142170
On Jul 28, 10:21=A0am, Sandro <sdro...@netscape.net> wrote: > ... > I hope Xilinx peoples who usually to read this group > could "chime" internally directly about a solution > to a problem that in the unix/linux environment > could be quite common. > ... For Xilinx guys... Maybe a the AR#33059 to related problem: http://www.xilinx.com/support/answers/33059.htm could give a true workaround using my tip. (todate AR#33059 solution is not a solution simply a statement "you can have problems...") SandroArticle: 142171
Have you looked at http://www.latticesemi.com/lit/docs/technotes/tn1053.pdf Check your configuration pins CFG[0:2]. All grounded for SPI.... Also check your software preferences. There are a number of options here which may be set to wake the device after programming. These are set in ispLEVER design planner global software settings or can be set manually in the preference file.Article: 142172
On Jul 28, 2:15=A0am, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Jul 28, 2:29=A0am, Dave Pollum <vze24...@verizon.net> wrote: > > > ..there were actually -3- non-spam posts in a row! ;) > > -Dave Pollum > > only 3? > > in GG I count last 13 in a row as non spam :) > > Antti Well I did report ~ 20 SPAM posts to Google. It looks like that actually did some good! -Dave PollumArticle: 142173
I've read about daisy chaining fpgas with Platform flash, but is daisy chaining fpgas possible with SPI flash? The documents at Xilinx seems to give only examples of single fpga configuration with SPI flash.Article: 142174
On Sun, 26 Jul 2009 10:28:03 -0700, Muzaffer Kal wrote: > On 26 Jul 2009 16:23:16 GMT, General Schvantzkoph > <schvantzkoph@yahoo.com> wrote: > >>Has anyone benchmarked Core7 vs Core2 on NCverilog, Questa, Xilinx and >>Altera FPGA tools? > > I'd also be very interested in Core7 vs Phenom II performance too (45nm > AMD ie Phenom II 955 etc.) We just got a new i7 machine for FPGA builds. It tested at just over twice as fast as our high-end AMD box that was 2-3 years old. I will publish the results in this ng within a week or two, assuming I can ever get the licensing for ISE 11.2 running on it. (Thanks Xilinx, flexlm was a really good move.) Regards, Allan
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