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Assuming a 16.758 MHz sample rate, what's the best way to generate a 2.333333 MHz sine wave in an FPGA? I could use a look-up table, but since the least common multiple of both frequencies is very high, and I have only limited memory, this is surely not optimal. The sampled sinewave for a down-conversion application. Many thanks, Guy.Article: 144026
On Nov 8, 2:59=A0pm, Guy Eschemann <guy.eschem...@gmail.com> wrote: > Assuming a 16.758 MHz sample rate, what's the best way to generate a > 2.333333 MHz sine wave in an FPGA? I could use a look-up table, but > since the least common multiple of both frequencies is very high, and > I have only limited memory, this is surely not optimal. The sampled > sinewave for a down-conversion application. Standard answer for severely memory-limited application: use a phase accumulator and CORDIC to calculate sin/cos from the phase angle. Needs quite a lot of FPGA fabric resource, but a fully pipelined implementation is very convenient since it needs no dedicated memory at all (each pipeline stage uses one fixed value from an arctan lookup table, and this value will end up being hard-wired). Note that CORDIC gives you both cos and sin outputs with no extra effort, which is likely to be useful for your downconverter. If your target technology has some spare hardware multipliers, CORDIC may not be the optimal solution. But it's easy to implement and well-understood. If you have access to a clock that's some exact multiple of your 16.758MHz sample rate, then you can make the hardware more compact too. -- Jonathan BromleyArticle: 144027
Guy Eschemann wrote: > Assuming a 16.758 MHz sample rate, what's the best way to generate a > 2.333333 MHz sine wave in an FPGA? I could use a look-up table, but > since the least common multiple of both frequencies is very high, and > I have only limited memory, this is surely not optimal. The sampled > sinewave for a down-conversion application. > > Many thanks, > Guy. DDS and analog filter on the msb.Article: 144028
On Nov 8, 1:59=A0pm, Guy Eschemann <guy.eschem...@gmail.com> wrote:
> Assuming a 16.758 MHz sample rate, what's the best way to generate a
> 2.333333 MHz sine wave in an FPGA? I could use a look-up table, but
> since the least common multiple of both frequencies is very high, and
> I have only limited memory, this is surely not optimal. The sampled
> sinewave for a down-conversion application.
>
> Many thanks,
> Guy.
The size of lookup table you need will depend a lot on the spurious-
free dynamic range (SFDR) you need for your application. The usual
method for dealing with mismatched sample/signal rates is to use a
phase accumulator with excess precision, and use the MSBs to address
the LUT. You can also use the LSBs to perform some higher-order
correction if need be. The circuit you're describing is a classic DDS
(Direct Digital Synthesizer), and the frequencies you're talking about
shouldn't present too much of a challenge.
In a radio up/down-conversion application, the slight inaccuracy of a
lookup-table approach is probably acceptable, given the inherent noise
and uncertainty of the channel.
Cheers,
-Ben-
Article: 144029Hello, Is there a readily available IP that implements an interconnection of MicroBlaze processors, i.e. in a 2D-Mesh or Torus network? Alexey.Article: 144030
Jonathan Bromley <spam@oxfordbromley.plus.com> wrote: > On Nov 8, 2:59?pm, Guy Eschemann <guy.eschem...@gmail.com> wrote: >> Assuming a 16.758 MHz sample rate, what's the best way to generate a >> 2.333333 MHz sine wave in an FPGA? I could use a look-up table, but >> since the least common multiple of both frequencies is very high, and >> I have only limited memory, this is surely not optimal. The sampled >> sinewave for a down-conversion application. > Standard answer for severely memory-limited application: use a > phase accumulator and CORDIC to calculate sin/cos from the > phase angle. Needs quite a lot of FPGA fabric resource, but a > fully pipelined implementation is very convenient since it > needs no dedicated memory at all (each pipeline stage uses > one fixed value from an arctan lookup table, and this value > will end up being hard-wired). Note that CORDIC gives you > both cos and sin outputs with no extra effort, which is > likely to be useful for your downconverter. I agree with the phase accumulator. I would have thought of a look-up table for the sin/cos, though. If one big table is too big, then a smaller table and linear interpolation using either another table or a mutliplier. -- glenArticle: 144031
On Fri, 06 Nov 2009 07:54:47 -0800, Curt Johnson <curt.johnson@dicombox.net> wrote: |If it is any solace, the Mentor schematic capture and PCB routing tools |are much worse. In addition to continuous license issues, crashes, |version compatibility problems, and file corruption, they produce |unreliable output. I now have to manually check every trace on a 10 |layer PCB with multiple BGA packages ever since we discovered that the |tools can randomly delete nets from a fully routed board without warning. |============= Mentor was an expensive joke ten years ago and I am not so surprised that it has not changed. I am glad I am retired and don't have to use their tools. jamesArticle: 144032
On Nov 9, 2:59=A0am, Guy Eschemann <guy.eschem...@gmail.com> wrote: > Assuming a 16.758 MHz sample rate, what's the best way to generate a > 2.333333 MHz sine wave in an FPGA? I could use a look-up table, but > since the least common multiple of both frequencies is very high, and > I have only limited memory, this is surely not optimal. The sampled > sinewave for a down-conversion application. DDS is one way, but if you only want one frequency, you should also check the humble VCO. The assumed ratio is 7.182 ( uses 2.333333' ) You can get that with a VCO and 4.3KHz compare Freq, or you can get within 25ppm, with a 212126.58 compare Freq. (/79; *11), and that's only 11 flipflops.. -jgArticle: 144033
On Nov 9, 11:15=A0am, -jg <jim.granvi...@gmail.com> wrote: > On Nov 9, 2:59=A0am, Guy Eschemann <guy.eschem...@gmail.com> wrote: > > > Assuming a 16.758 MHz sample rate, what's the best way to generate a > > 2.333333 MHz sine wave in an FPGA? I could use a look-up table, but > > since the least common multiple of both frequencies is very high, and > > I have only limited memory, this is surely not optimal. The sampled > > sinewave for a down-conversion application. > > DDS is one way, but if you only want one =A0frequency, you should also > check the humble VCO. > The assumed ratio is 7.182 ( uses 2.333333' ) > You can get that with a VCO and 4.3KHz compare Freq, > or you can get within 25ppm, with a 212126.58 compare Freq. > (/79; *11), and that's only 11 flipflops.. > > -jg Expanding this a little, there is no reason you cannot do the converse in a FPGA, with a Digital Frequency Synthesizer - here, you would multiply 16.758 by 11, then divide by 79, and that 79 could index a sine-rom if needed. -jgArticle: 144034
On Nov 6, 1:32=A0pm, Curt Johnson <curt.john...@dicombox.net> wrote: > rickman wrote: > > The reason for using commercial tools is supposed to be the great > > support and the lack of serious bugs... =A0so if you don't like your > > expensive layout tools, why use them? =A0I used FreePCB on my last > > project and found it very suitable. =A0I am sure there are some things > > that you need to do manually that expensive tools might do > > automatically, but hand checking all the nets is not one of them. > > > Not trying to be smart, this is a serious question. > > > Rick > > Good question. Mostly inertia. > > If FreePCB will import our libraries and designs, I'll check it out in a > minute. > > Maintenance is an issue. We are in the medical racket. Product lifetimes > can be a dozen years or more. We are still shipping product with > XC3142's in them. When parts go obsolete, we often need to quick turn a > board to keep shipping product. That means either we keep the tools > around for the duration, or find something that can read the files. > > Most of my new designs are more or less 50% original and 50% cut and > pasted from previous designs. It saves a bit of time not having to > recreate parts and redraw schematics. > > I've used Pads, Tango, Calay, Cadroid, Orcad, and a few other packages > over the years. Some were better than others, but all of them had > problems of one sort or another. I've kind of got to the point where if > my PC doesn't catch fire after I install a new version, I consider it a > victory. > > Curt FreePCB is not the sun and moon of PCB layout. It won't import any other layouts or libraries I'm pretty sure. It is a pretty good tool. Do *any* layout tools import other layouts? There have been efforts over the years to establish a common format for schematic and layout tools and it has always met with failure because none of the tool vendors want to let a user switch easily. That alone is reason enough for me to want to never use a commercial tool again. RickArticle: 144035
On Nov 9, 4:51=A0pm, rickman <gnu...@gmail.com> wrote: > =A0Do *any* layout tools import other layouts? =A0 Yes, Mentor have Layout translators from Protel(Altium), Cadstar, OrCAD, and also Schematic Translators from the same. They work quite well, and are good for harvesting web resource, and things like reference designs. Last time I checked, Analog Devices and SiLabs used Mentor's PADS for their designs, but others may use OrCAD Schematic. DXF is also a useful interchange format, often overlooked. I remember creating a good decal for an Open-Frame relay, via the DXF file supplied. In fact, the DXF file had vital info that was missing off the drawing !! -jgArticle: 144036
On Nov 7, 6:53=A0pm, Karl Berry <kberr...@gmail.com> wrote: > I'm trying to look into the status of free software/open source > efforts relating to FPGA (because rms asked me to). Open-source efforts have not served us well in the FPGA and electronics design/verification community. There are a few beacons of usefulness (Icarus Verilog,...) but, for the most part, available open-source tools just don't provide the level of productivity and flexibility that real users need. There are, I think, many reasons why the match is not good. In the software development community, there is a big overlap between the skills of tool users and tool developers. In EDA-land, although the users are likely to be very software-savvy they are rather unlikely to be competent developers. Those users, however, are (rightfully and necessarily) very demanding of their tools; they have deadlines to meet, products to get out the door and businesses to run; 80%-finished tools are completely useless to them. So there is a big mismatch between the community's expectations of their tools, and its ability to develop them (or to engage with developers, or to engage with the open-source development process). A couple of specific examples: - ghdl I have no idea whether it's any use or not. The fact that there is no vigorously maintained binary distribution means that it's useless to me. The idea of building my tools from source code fills me with horror - I'm not competent to do that with the kind of reliability that's needed for tools that are critical to my daily work. But the community of potential ghdl users is not large enough to justify the considerable effort of maintaining a distribution that would give me the same level of convenience and confidence that I get with commercial tools. -gcc Yes, I know gcc is fantastic. I use it all the time. But as an FPGA user I would love to be able to port gcc to different, way-out embedded target architectures. I know it can be done. I know that gcc is about as flexible as it gets for creating new back-end targets. But it requires guru-level expertise even to start work on a port. I gather that lcc is easier to port, but I've now been scared off even trying. Once again there's a mismatch between the users' expectations and needs, and the skills that those users could bring to the tool development process. I don't really know what can be done about this. I think there's a risk of the open-source evangelists being flushed with their own success in other fields, and giving the impression of extreme smugness - "all you need to fix this problem is a good Eclipse plug-in"... yeah, right. There's certainly a risk of the EDA community being insufficiently articulate about the very complex requirements they have for their development tools, and therefore failing to communicate effectively with open-source developers. By contrast, commercial developers respond to revenue streams and therefore it becomes their responsibility, not the users', to establish lines of communication that reflect customer needs back into the development process. In the open source world, I suspect, this has worked primarily because the developers are also users themselves. It is a mistake to think that, because EDA tool users are very technical people with a good level of software expertise, they are also able to communicate effectively with tool developers; it is an equally gross error to assume that, because you're a smart software developer, you naturally understand all the needs of a particular user group. Much humility and flexibility will be needed from both sides if we are to make real progress. -- Jonathan BromleyArticle: 144037
On Nov 9, 8:51=A0pm, Jonathan Bromley <s...@oxfordbromley.plus.com> wrote: <snip many points> Besides those points, there are very important Time-Line issues : FPGA vendors start tool research BEFORE they start the silicon, and they are not about to tell anyone the details of their 2011 chips!. That makes FPGA tools very different from PCB design tools, where the target-issues have changed little and are obvious well in advance. Because the tools are so critically coupled to the silicon, that leaves only the silicon-agnostic areas, and there are some Open source developments in those areas. -jgArticle: 144038
Karl Berry wrote: > I'm trying to look into the status of free software/open source > efforts relating to FPGA (because rms asked me to). > > After searching in this group, wikipedia, etc., the one I've been able > to find is slipway/abits from Adam Megacz (Adam, are you still here?), > but from checking out the sources it seems development stalled a while > back, understandably enough since I gathered from the last post I saw > about it that the manufacturer didn't have much interest in the > hardware any more. > > Are there any other ongoing projects? Any info greatly appreciated. > Thanks in advance. > > Karl Berry (karl /at/ gnu /dot/ org) There are various open source packages for FPGA programming that let you use a high level language and generate Verilog and/or VHDL output, as well as being useful for simulation and checking the correctness of your design. The "big" one (a relative term) is MyHDL, which is Python based. <http://www.myhdl.org/> There are many others, often based on functional programming languages. Functional programming is in many ways a better fit for high level hardware design than procedural languages, but it's a niche area. And since FPGA development is also a niche area, there are very few people who are interested, competent, and have the time and energy to do open source development in these languages. Thus many have come and gone because they haven't been able to maintain a momentum of development. Examples here include confluence (a bit unpolished, but even the half-done development versions are usable).Article: 144039
"pcie-rat" <ro7@axcon.dk> wrote in message news:320bb306-e1b8-41f0-88b1-530e813009e1@m16g2000yqc.googlegroups.com... > Morten, > > Whatever solution you go with - my advice is this: > > * Get readable commented source code - or get a good option to buy it > at a decent cost. It pays in the end. I agree that is a plus. Spending time on support is not creating added value. I'd rather spend the time on correcting/improving the problems myself. > * When thinking about price, take your own cost into consideration. > One engineering day in the Nordic region cost about EUR 5-600 all > included (yes, more than just salary). So if you are trying to save > say EUR 4000 (which incidentally is about 50% of the solution we > have :-), you have about 7 days in total to do so. This needs to > include everything. And that is just breaking even. If your company > usually have you do something that is more valuable than the cost of > having you hanging around :-) Which I hope they do :-) They would want > you to generate more savings than the time you spend. So better budget > at most about 3-4 days to save the EUR 4000 :-) I don't fully agree with that although I can see it from your perspective (especially if the market is small). Competition is to the benefit of the buyer. It will be like saying it is ok to pay $100 for a bread, cause the process of doing all from scratch yourself is gonna cost much much more. For low quantity volumes and a price like that can kill the project. To continue my comparison, it would prevent any cafe's to open, cause the price of bread would not make it profitable. :)Article: 144040
On Sun, 8 Nov 2009 20:34:15 -0800 (PST), -jg <jim.granville@gmail.com> wrote: >On Nov 9, 4:51 pm, rickman <gnu...@gmail.com> wrote: >> Do *any* layout tools import other layouts? > > Yes, Mentor have Layout translators from Protel(Altium), Cadstar, >OrCAD, and also Schematic Translators from the same. > > They work quite well, and are good for harvesting web resource, >and things like reference designs. > > Last time I checked, Analog Devices and SiLabs used Mentor's >PADS for their designs, but others may use OrCAD Schematic. > >DXF is also a useful interchange format, often overlooked. But probably one of the least standard 'standards' out there, at least in terms of implementation... I find that an imported/exported DXF rarely resembles the original in all respects - even really basic stuff like the scale can be completely wrong!Article: 144041
Jonathan Bromley wrote: > On Nov 7, 6:53 pm, Karl Berry <kberr...@gmail.com> wrote: >> I'm trying to look into the status of free software/open source >> efforts relating to FPGA (because rms asked me to). > > Open-source efforts have not served us well in the > FPGA and electronics design/verification community. > There are a few beacons of usefulness (Icarus Verilog,...) > but, for the most part, available open-source tools just > don't provide the level of productivity and flexibility > that real users need. I agree with your analysis. In the short and medium term, I believe that a balanced approach like the one from www.sigasi.com is the most sensible. The product consist both of proprietary and open source code. Open source is used systematically whenever possible, for maximal cost-effectiveness and productivity. However, there is always a company behind it that does the integration and testing, and guarantees quality and support. In the longer term, things will depend on whether hardware design becomes a "mainstream" software development technology. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.comArticle: 144042
Alexey <trenkoff@gmail.com> writes: > Hello, > > Is there a readily available IP that implements an interconnection of > MicroBlaze processors, i.e. in a 2D-Mesh or Torus network? > Just hang a bunch of FSL buses off the FSLs of the Microblazes. Copy and paste in the MHS file is less hassle than the XPS GUI in my experience ;) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 144043
On Nov 8, 5:15=A0pm, -jg <jim.granvi...@gmail.com> wrote: > On Nov 9, 2:59=A0am, Guy Eschemann <guy.eschem...@gmail.com> wrote: > > > Assuming a 16.758 MHz sample rate, what's the best way to generate a > > 2.333333 MHz sine wave in an FPGA? I could use a look-up table, but > > since the least common multiple of both frequencies is very high, and > > I have only limited memory, this is surely not optimal. The sampled > > sinewave for a down-conversion application. > > DDS is one way, but if you only want one =A0frequency, you should also > check the humble VCO. > The assumed ratio is 7.182 ( uses 2.333333' ) > You can get that with a VCO and 4.3KHz compare Freq, > or you can get within 25ppm, with a 212126.58 compare Freq. > (/79; *11), and that's only 11 flipflops.. > > -jg When you say VCO, are you suggesting that the OP use a PLL to generate the a multiple of the 2.333... frequency and then use a much smaller sine table? That's not a bad idea actually. But that would put the samples in the new clock domain and I believe the OP needs the samples in the 16.758 MHz clock domain. I suppose a multirate filter could be used to convert the sample rate, but I expect that would be a lot more logic than the CORDEC approach. RickArticle: 144044
On Nov 8, 11:34=A0pm, -jg <jim.granvi...@gmail.com> wrote: > On Nov 9, 4:51=A0pm, rickman <gnu...@gmail.com> wrote: > > > =A0Do *any* layout tools import other layouts? =A0 > > =A0Yes, Mentor have Layout translators from Protel(Altium), Cadstar, > OrCAD, and also Schematic Translators from the same. > > =A0They work quite well, and are good for harvesting web resource, > and things like reference designs. > > =A0Last time I checked, Analog Devices and SiLabs used Mentor's > PADS for their designs, but others may use OrCAD Schematic. > > DXF is also a useful interchange format, often overlooked. > > =A0I remember creating a good decal for an Open-Frame relay, via > the DXF file supplied. > =A0In fact, the DXF file had vital info that was missing off the > drawing !! Curt was asking about drawings and libraries. Do the converters also convert user built libraries? A lot of people have significant libraries which represent a lot of work although, if the info is captured in a way that is easily read, I think most footprints are pretty easy to recreate. It is coming up with the dimensions that is the hard part I think. I know FreePCB makes it *very* easy to draw footprints, it is just figuring out how to design them that is the hard part. It would only be a weeks work to convert 100 footprints if you had the dimensions readily available. Schmatic symbols are a different thing because each schematic package has its own quirks about how they are made I think. FreePCB does not include schematics at all. Many people use TinyCAD for that, but since layout is not closely tied to schematic capture, it doesn't matter a lot what you use. RickArticle: 144045
On Nov 4, 11:40 am, austin <aus...@xilinx.com> wrote: > All, > > I was puzzled that they used a push of the 65nm technology node (to > 60nm). > > It is a huge investment for a FPGA device company to launch a new > family, and to launch one with "the old" technology node means that > the latest technology node is guaranteed to beat you on price, power, > and/or performance (since 90nm, we do not get to choose all three, we > are at best a two out of three for a new node). That is a vastly overstated argument without *any* supporting evidence. It has happened more than once that an FPGA vendor (I won't mention any names that include an X) has pushed ahead with a new process only to be burned by the problems it created. Maybe the new process will see better performance (are parts still getting much faster really?) or power (assuming the new process deals with the problems it creates in this area), but price is highly dependent on yield which is seldom good in a new process and only provides edible fruit as it ripens. All this is on top of the issue of meeting an announced schedule for availability of the parts. I remember at least two generations of parts from Xilinx that were "shipping" except that you couldn't get any for some six months. Altera tends to hold back a bit longer until they are sure they will meet schedule and won't have problems with the parts. > True, S6 is optimized for power (first time we have ever used a low > power process from a foundry), so bragging about performance is one > way to shout very loudly "we sure burn a lot more power!" > > When we asked customers what their number one need was for S6, it was > "lower the power!" > > I know that many like to use the latest Spartan node to replace the > previous Virtex node (lower their bill of materials costs), but > frankly, S6 was designed for a new markets, and not intended to > cannibalize Virtex 5 sockets. > > Anyway, it is always fun to watch how these things play out, > > Austin Yes, it makes for interesting reports even if not interesting parts. RickArticle: 144046
"Antti" <antti.lukats@googlemail.com> wrote in message news:95de46f5-319d-480d-bb38- > you can sometimes enable "early access" support, by changing some things > in the EDK, > or just be adding the new family to the MPD files Antti, Have you actually tried this approach of "porting" MB to V6? I wonder how much time I will have to spend and whether I will be able to estimate performance this way... Thanks, /MikhailArticle: 144047
malcolm wrote: > Err, but a random-deleted net is actually easy to find, as you usually > have more than one copy (as in, in the SCH, or even in a copy of the > PCB ) ? > > Which Mentor flows/versions are you using ? If I have plots from an earlier revision, I compare them with the new revision one page at a time on a light box. Every difference has to be traced to ensure that it is an intended change. On a 10 layer PCB with 4 BGAs, about a dozen smaller packages and a couple of hundred discretes, it takes me two or three days. Not difficult, but extremely tedious. Viewdraw & Pads. I'm using Viewdraw (or DxDesigner I think they call it now) version 2006.1. I havn't been able to get the 2007 release to read in any of our current projects. The random net deleting feature has been in place since before I started here in 1993; but before BGAs, we could always rework the boards. CurtArticle: 144048
hi all. i am using Spartan 3A DSP 1800A board which supports a UART/serial link. when using EDK i can directly use it to send the data from the FPGA to the PC using the xil_printf() command which i can finally view in hyperterminal.But now i want to send the data from FPGA to matlab instead of hyperterminal. I am using a microblaze processor. this sort of problem has been largely addressed for microcontrollers but not for the FPGA or the processors embedded in FPGA.could somebody suggest me some ideas,links,tutorials related to this problem. Any suggestions would be highly appreciated. PrashantArticle: 144049
On Nov 9, 6:11=A0pm, "MM" <mb...@yahoo.com> wrote: > "Antti" <antti.luk...@googlemail.com> wrote in message > > news:95de46f5-319d-480d-bb38- > > > you can sometimes enable "early access" support, by changing some thing= s > > in the EDK, > > or just be adding the new family to the MPD files > > Antti, > > Have you actually tried this approach of "porting" MB to V6? I wonder how > much time I will have to spend and whether I will be able to estimate > performance this way... > > Thanks, > /Mikhail not with V6, with some previous version yes Antti
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