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Hello, Thanks for reply. Reason for using JTAG is: I am already using this PIC18 to configure a Xilinx FPGA on JTAG. So the JTAG low level protocol is ready. I could decode Xilinx bit file. With Altera, what remanis is only extracting the actual configuration data from the rbf (or any other) file. For any other configuration scheme, I may have to carry out some hardware change too.. If you or anyone has some clue about rbf file format, that will be very much useful. JRunner software from Altera shows first 44 bytes is the header in rbf file. So does it meant that from 45th byte onwards, everything else is configuration data? Regards, >You might be better off using the PIC (or whatever mirco/processor) >implement the serial programming. This method is well documented and >very straightforward to implement. I'm not sure Altera publishes >anything allowing you to configure using JTAG, other than their >proprietary ByteBlaster, etc. > --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144701
On Dec 25, 7:37=A0am, "gopal_amlekar" <gopal_amle...@yahoo.com> wrote: > Hello, > > Thanks for reply. > > Reason for using JTAG is: I am already using this PIC18 to configure a > Xilinx FPGA on JTAG. So the JTAG low level protocol is ready. I could > decode Xilinx bit file. With Altera, what remanis is only extracting the > actual configuration data from the rbf (or any other) file. For any other > configuration scheme, I may have to carry out some hardware change too.. > > If you or anyone has some clue about rbf file format, that will be very > much useful. JRunner software from Altera shows first 44 bytes is the > header in rbf file. So does it meant that from 45th byte onwards, > everything else is configuration data? > > Regards, > > >You might be better off using the PIC (or whatever mirco/processor) > >implement the serial programming. =A0This method is well documented and > >very straightforward to implement. =A0I'm not sure Altera publishes > >anything allowing you to configure using JTAG, other than their > >proprietary ByteBlaster, etc. > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com RBF is raw binary so there is no in detail description of it, same as BIT file you take the file and use it as RAW data AnttiArticle: 144702
To simplify design of the DSP system I have decided to describe the ports connecting different blocks (to be synthesized in the same FPGA) as a record. It resulted in a code, in which two different processes (each in one of connected blocks) assign values to the different fields of the same record. Unfortunately my VHDL simulator (namely: GHDL) recognizes this situation as the conflict, and sets the whole record to 'U'. Have I really overlooked something in the VHDL rules? It seems, that it should not be considered a conflict, as each field is driven by a single process. -- TIA WZabArticle: 144703
I have found the following discussion: http://www.velocityreviews.com/forums/t487026-vhdl-port-inout-problem.html And according to the solution decribed there, I set ALL fields (elements) of the record in ALL processes. If the particular process does not drive the particular signal, I set it to "Z". This solution works, however I'm afraid that setting a signal to 'Z' in any place instead of ports of top entity may confuse the synthesis tools... Does any of you have any experiences with such a problem? -- TIA WZabArticle: 144704
I'm trying to build a register-file for an ALU which has 3 read ports
and 1 write port. There is a single clock design but I need to assume
that all ports are in use on every clock cycle, worst case.
I can envision implementing this using 3 Dual Port Memories each
with one read port and one write port as follows:
Sorry - ASCII ART (use fixed width font)
Address lines elided -
+-------+
+--->| RAM1 | -----> read1
| +-------+
| +-------+
write1 --+--->| RAM2 | -----> read2
| +-------+
| +-------+
+--->| RAM3 | -----> read3
+-------+
Is this the best way to do this?
If I *had* to add another write port to the memory - can you do that
using memories? I can't see it...
Thanks in advance.
Rob Doyle
Article: 144705Rob Doyle wrote: > Is this the best way to do this? AFAIK, IMHO, etc. yes > If I *had* to add another write port to the memory - can you do that > using memories? I can't see it... Good question indeed. There are some ways to fake a dual-write register set using single-write blocks but nothing I know can really do it. If you are designing a CPU, this can badly affect the ISA and/or performance. That's why "most RISC CPU" only have 2R1W instruction. One simple way to double the number of ports is by clocking the register set 2x faster, but I assume from your post that it's what you intend to do. That's a good bet if your pipeline/clock/timing can handle it, the memory blocks can often run faster than the logic on some FPGAs. Another method is to implement a register/buffer/write cache that gets written back to the main register set on the following cycle. The method assumes that the 2W instructions are not very common and it stalls the pipeline for one cycle in order to perform the write back, in case the following instruction does a write too. A special path must also forward the recently written value and bypass the read ports. Yet another method splits the register set into two parts, say the odd and even banks. The ISA will specify that the 2W instructions can not write to two registers of the same bank. The restriction can be loosened a bit with more banks (4 or 8) depending on the available resources. As far as I know, the venerable Alpha EV6 used powerful combinations of these methods, implementing the 32-register set with 2 huge banks that could handle 4 simultaneous instructions at once (with the help of register renaming and out-of-order execution). comp.arch readers will fill the gaps :-) > Thanks in advance. keep us informed of your advances, > Rob Doyle yg -- http://ygdes.com / http://yasep.orgArticle: 144706
As enticing as it is, I've found that using record types in synthesizable VHDL is just inviting problems. I certainly wouldn't do it if I needed separate processes to drive different elements of the record. Avoiding 'Z' except for actual tri-state hardware (e.g., IOB pins on FPGAs) is a good idea. The synthesizers can often deal with Z OK, but I prefer to keep my designs closer to what the hardware can actually implement, rather than counting on the cleverness of the synthesizer. (Obviously I still do count on the cleverness of the synthesizer; I just try not to do it more than necessary.) EricArticle: 144707
Hallo, Have you tried to create an interface process with two different input interfaces and one output interface, devoted to acquire data from the two writing processes and to merge them into the record you need? I didn't check if this can work, but it should. Ciao, MaurizioArticle: 144708
On Fri, 25 Dec 2009 21:38:48 -0700, Rob Doyle <radioengr@gmail.com> wrote: > >If I *had* to add another write port to the memory - can you do that >using memories? I can't see it... One thing you can do is to have two copies of your register file and keep a 'most-recently-written' state for each location. Then each read path has an additional 2-1 mux after it controlled by the same signal (and a comparator for the read address). This should give the datapath you want but whether the extra delay is acceptable depends on your requirements. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 144709
On Dec 13, 10:32=A0pm, Eric Smith <space...@gmail.com> wrote: > Thanks, Brian! =A0That's very helpful! > > Eric FWIW, in case you do need to find out the BRAM locations in the implementation for some other purpose, take a look at the message below on Xilinx forum: http://forums.xilinx.com/xlnx/board/message?board.id=3DVirtex&message.id=3D= 5177#M5177 Cheers, Jim http://myfpgablog.blogspot.com/Article: 144710
hi folks, I have a very elderly Nallatech Strathnuey board that I might try to get going if I have e few spare hours. It has two old-original Spartan XC2S150 devices, two Xilinx flash ROMS, a USB interface and a bunch of power regulators; it also can plug into a PCI slot (I probably won't try to use that) and various expansion connectors. A few weeks ago I ping'd Nallatech about it, but got no response (it's hard to blame them for ignoring a request about a ten-year-old board, but I was a bit disappointed to get no reply at all). So I wondered if anyone here has access to any relevant documentation and/or driver software... or, of course, the usual advice to stop futzing around with museum stuff and move on to something more sensible :-) thanks in advance, and happy 2010, -- Jonathan Bromley PS - what's the correct way to write the past tense of the verb "to ping"? Pingued? Pung? I started with "pinged" but that would probably be pronounced with a soft G...Article: 144711
I hadn't looked at their webste for a while but looks like they have basically dropped anything that was a old product prior to their takeover by Interconnect. I guess the new owners don't want the baggage of the past. I used to look at the Strathnuey because it was a competing product and even when it was a "current" board they made it hard to get information without a full sales engagement. John Adair Enterpoint Ltd. On 27 Dec, 10:12, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > hi folks, > > I have a very elderly Nallatech Strathnuey board that I might > try to get going if I have e few spare hours. =A0It has two > old-original Spartan XC2S150 devices, two Xilinx flash ROMS, > a USB interface and a bunch of power regulators; it also > can plug into a PCI slot (I probably won't try to use that) > and various expansion connectors. > > A few weeks ago I ping'd Nallatech about it, but got no > response (it's hard to blame them for ignoring a request > about a ten-year-old board, but I was a bit disappointed > to get no reply at all). =A0So I wondered if anyone here > has access to any relevant documentation and/or driver > software... =A0or, of course, the usual advice to stop > futzing around with museum stuff and move on to something > more sensible :-) > > thanks in advance, and happy 2010, > -- > Jonathan Bromley > > PS - what's the correct way to write the past tense of > the verb "to ping"? =A0Pingued? =A0Pung? =A0I started with > "pinged" but that would probably be pronounced with a > soft G...Article: 144712
HI ! i have a usb-JTAG CABLE FOR PROGRAMMING A FPGA , there is no mention of any vendor or company on the cable .... when i used it to program a XILINX SPARTAN 3 E FPGA ON A DIGILENT BOARD THROUGH "ADEPT(SOFTWARE I DOWNLOADED FROM DIGILENT.COM)" , the bit file was successfully downloaded to FPGA BOARD ....but now i have a XTREME DSP SPARTAN 3A STARTER PLATFORM and when i generate a bit file and goto iMPACT no cable is detected .... one can not say that the cable is from digilent because there is no mention of any sort on cable , 2ndly the cable has been used previously by some other person to program a XILINX SPARTAN 3 BORAD through iMPACT............... so what should i do .... kindly help my 295$ board is of no use to me now ............Article: 144713
>HI ! i have a usb-JTAG CABLE FOR PROGRAMMING A FPGA , there is no mention >of any vendor or company on the cable .... when i used it to program a >XILINX SPARTAN 3 E FPGA ON A DIGILENT BOARD THROUGH "ADEPT(SOFTWARE I >DOWNLOADED FROM DIGILENT.COM)" , the bit file was successfully downloaded >to FPGA BOARD ....but now i have a XTREME DSP SPARTAN 3A STARTER PLATFORM >and when i generate a bit file and goto iMPACT no cable is detected .... >one can not say that the cable is from digilent because there is no mention >of any sort on cable , 2ndly the cable has been used previously by some >other person to program a XILINX SPARTAN 3 BORAD through >iMPACT............... so what should i do .... kindly help my 295$ board >is of no use to me now ............ > > > The digilent cable used with their adept software is a custom design. It will not work with impact software unless it is reprogrammed. Can you still use the adept software with your new board? --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144714
> PS - what's the correct way to write the past tense of > the verb "to ping"? Pingued? Pung? I started with > "pinged" but that would probably be pronounced with a > soft G... "pang"Article: 144715
Hello Thomas-- Thank you so much for your response! > > Your suspection is almost right. As you already found the problem on > the pin, I suggest to get rid of these Warnings before they bite you > next. Yes, this is exactly what I have done. After changing my Verilog code, it finally passes timing analysis! > If the timing requirement could not be achieved, you are not > guaranteed, that your design will always work in the intended way, as > in some situations your data will need longer to be correct than your > clock signal allows, which means your clock will sample wrong data. > It may be possible, that the slack is so small, that you will > experience this only on some devices or on some temperatures, a large > slack might affect every device on every temperature, but due to the > nature of the path it may be undetected for longer time, until you set > the device in the condition, when this long path is sensible. I found that the timing analysis warnings were caused by signals crossing between clock domains. I implemented a synchronizer with flip-flops to safely propagate the signals. (Reference: http://www.fpga4fun.com/CrossClockDomain.html) Now that the signals do not explicitly cross clock domains, I have no problem with the classical timing analysis. > > A typical long path in an adder through the carry. This adder will > have no problem for pairs of input numbers that didn't stress the > carry (e.g. 0 and n, 1+4,...). If you want to add two numbers that > stress carry you will see that some bits have the correct value and > other the wrong value, leading to complete strange results. > Yes, you are very right about this weird behavior. I was wondering why these strange results were observed. Hopefully I will not see anything strange now that there are no problems with timing analysis. > bye Thomas > Thank you once again for your help! NicholasArticle: 144716
On Dec 26, 3:14=A0pm, Muzaffer Kal <k...@dspia.com> wrote: > On Fri, 25 Dec 2009 21:38:48 -0700, Rob Doyle <radioe...@gmail.com> > wrote: > > > > >If I *had* to add another write port to the memory - can you do that > >using memories? =A0I can't see it... > > One thing you can do is to =A0have two copies of your register file and > keep a 'most-recently-written' state for each location. Then each read > path =A0has an additional 2-1 mux after it controlled by the same signal > (and a comparator for the read address). This should give the datapath > you want but whether the extra delay is acceptable depends on your > requirements. > -- > Muzaffer Kal > > DSPIA INC. > ASIC/FPGA Design Services > > http://www.dspia.com Xilinx supports 3-port memories as well if it helps. You can have one read/write port and two read ports with 3 different addresses. You can either infer it or instantiate the component directly. Cheers, -- AmalArticle: 144717
hello, Amal wrote: > Xilinx supports 3-port memories as well if it helps. You can have one > read/write port and two read ports with 3 different addresses. > You can either infer it or instantiate the component directly. the OP and the thread are speaking about multiple write port, because multiple read ports are trivially implemented. However, simultaneously having 2 read AND 2 write ports (4 simultaneous addresses, for example) is not as easy and I guess that few synthesisers will infer the correct SRAM blocks. > Cheers, > -- Amal happy new year, yg -- http://ygdes.com / http://yasep.orgArticle: 144718
On Sun, 27 Dec 2009 11:12:54 +0100, Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote: >hi folks, > >I have a very elderly Nallatech Strathnuey board ... >thanks in advance, and happy 2010, I guessed at your email... if you don't hear from me, let me know. Happy New Year! - BrianArticle: 144719
mac <alexc@theworld.com> wrote: > >> PS - what's the correct way to write the past tense of >> the verb "to ping"? Pingued? Pung? I started with >> "pinged" but that would probably be pronounced with a >> soft G... > >"pang" Like in to ring? So ping would be ping pang pung? We tried to ping him. We pang him. He has been pung. Hmmm. Like the sound of that. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 144720
On Mon, 28 Dec 2009 12:56:56 GMT, nico@puntnl.niks (Nico Coesel) wrote: >mac <alexc@theworld.com> wrote: > >> >>> PS - what's the correct way to write the past tense of >>> the verb "to ping"? Pingued? Pung? I started with >>> "pinged" but that would probably be pronounced with a >>> soft G... >> >>"pang" > >Like in to ring? So ping would be ping pang pung? >We tried to ping him. >We pang him. >He has been pung. >Hmmm. Like the sound of that. ..but the verb ring in the context of marking birds or drawing a circle with a pen would be 'ringed'Article: 144721
We proudly announce the 6th annual Digilent Design Contest, organized within the Technical University of Cluj-Napoca, sponsored by Digilent and Xilinx! The goal of this international student contest is to encourage students to develop their hardware digital design skills. We invite teams of students (one or two members), from all over the world, to put in practice their ideas. Teams have 3 months to design and implement a digital design project of their choice and present the final version in May 2010 in Cluj-Napoca, Romania. We provide students with free, state-of-the-art FPGA or microcontroller Digilent boards to develop their projects. The most creative and complex solutions are rewarded with generous prizes! Visit us on the web for more information: http://www.digilentinc.com/events/ro2010 or write to: hardwarecontest@digilent.ro.Article: 144722
On Dec 28, 3:40 am, whygee <y...@yg.yg> wrote: > hello, > > Amal wrote: > > Xilinx supports 3-port memories as well if it helps. You can have one > > read/write port and two read ports with 3 different addresses. > > You can either infer it or instantiate the component directly. > > the OP and the thread are speaking about multiple write port, > because multiple read ports are trivially implemented. > However, simultaneously having 2 read AND 2 write ports > (4 simultaneous addresses, for example) is not as easy > and I guess that few synthesisers will infer the correct > SRAM blocks. The OP doesn't need four ports from a single memory, only three are needed. If two write ports are needed, there is no way to fake that, at least no easy way. Three ports are needed, two write and one read. Then as many read ports can be added as needed by duplicating the memory with separate read addresses. If the OP can use the same address for one write port and the read port, then this is just a two port memory with read/write capability. If a two write, one read port memory with three addresses is needed and only two addresses can be input to the memory, then a third memory can be used to "arbitrate" between two duplicated, two address, one write, one read port memories. When a write happens, the data is written to the memory connected to that write port. The third memory is just one bit wide and the bit at the corresponding address is set or reset to indicate which port the most recent write has been from. When a read is done, a mux selects from the appropriate memory block. The only fly in the ointment is that the "flag" memory has to have two write and two read ports. So it can't be done in a block ram, but must be made of logic and FFs. That is some savings over doing the entire memory in logic if it is wider than one bit... but still a PITA and quite a mess. But if you *have* to have this memory and the part does not support it... I guess you have no choice, eh? RickArticle: 144723
This is in Altera cylone-3. I have this code which seems to run OK in RTL and gatelevel simulation but I m getting glitches in signaltap and in oscilloscope. The clock is running at 100 MHz but data is being written and read from a Ram every 5 us or so. I am getting glitches in State 2 and 3. The STATE is getting assigned in separate sequential process. Also do I need to put all the signals being checked in the always block ( e.g counter and count_down_cnt etc). always @(STATE or counter) begin: FSM_COMBO1_I case(STATE) ST0 : begin if (!wrempty) begin next_STATE <= ST1; rdreq1 <= 1'b1; end else begin next_STATE <= ST0; rdreq <= 1'b0; end end ST1: begin rdreq <= 1'b0; if (counter == q1_out[19:12] ) begin next_STATE <= ST2; output1 <= 1'b1; counter_data<= q1_immediate[11:0]; counter_sload <= 1'b1; counter_cnt_en <= 1'b1; end else begin next_STATE1_I <= ST1; output1 <= 1'b0; counter_sload <= 1'b0; counter_cnt_en <= 1'b0; end end ST2: begin counter_sload <= 1'b0; if (count_down_cnt == 12'd1) begin next_STATE<= ST3; output1 <= 1'b0; counter_cnt_en <= 1'b0; end else begin next_STATE <= ST2; output1 <= 1'b1; counter_cnt_en <= 1'b1; end end ST3: begin next_STATE <=ST0; end default: begin next_STATE <= ST0; output1 <= 1'b0; rdreq1 <= 1'b0; counter_cnt_en <= 1'b0; counter_data <= 12'd0; counter_sload <= 1'b0; counter_cnt_en <= 1'b0; end endcase end Thanks for your suggestions/ideas.Article: 144724
For certainreasons, I could not use battery on my board, so the Virtex5 bitstream encryptioncould not be used. In this situation, what could I do to protect my design on areasonable level? My design hasVirtex5 and XCF16P, and the two devices are linked on JTAG chain, and I programXCF16P with my design through JTAG chain. I have set the security options inboth BitGen and iMPACT utilities, so I can prevent any JTAG readback/partialreconfiguration though JTAG chain. However I have the following questions: 1. Although inhardware, XCF16P will be disabled after configuration is done. But with minorfly wire modifications in hardware, the attacker could access XCF16P afterconfiguration. And I found that using the combination of USER_ACCESS_VIRTEX5 +STARTUP_VIRTEX5 could make FPGA read back data from XCF16P, it is possible? 2. Since Idisabled the possibility of reading back via JTAG, need I initiateBSCAN_VIRTEX5 + ICAP_VIRTEX5 and clear the entire FPGA once JTAG chain activityis found? Thanks a lot!
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