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Messages from 144925

Article: 144925
Subject: Re: SystemVerilog Verification Example using Quartus and ModelSim
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Fri, 15 Jan 2010 17:24:02 +0100
Links: << >>  << T >>  << A >>
On Fri, 15 Jan 2010 07:32:13 -0800 (PST), jjlindula wrote:

[me]
>> using SystemVerilog's object-oriented programming features,
>> and those definitely require top-end features of the simulator
>> that you simply won't get in the cheaper or "student" editions.

[you]
>Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will
>that be okay?

I'm afraid not.

You will probably find that quite a few of the SV design features
are fully supported in that version - interfaces, always_comb,
structs, .* port connection, that sort of thing - but I would
be astonished if you had access to any of the big-ticket
verification stuff such as classes and randomization.  To
find out, try these little examples.  Be sure to give the
files ".sv" extension, or alternatively use the -sv compile
option to the vlog command.

<example 1>
module enum_test;  // probably works OK
  typedef enum {first, second, third} ordinal;
  ordinal which;
  initial begin
    which = second;
    $display("this should print 'second': %s", which.name());
  end
endmodule

<example 2>
module random_test;  // I don't expect this to work in MSim AE
  integer i, ok;
  initial begin
    repeat (10) begin
      ok = randomize(i) with {i inside {1,2,4,8,16};};
      if (ok)
        $display("random value is %0d", i);
      else
        $display("randomization FAILED");
    end
  end
endmodule

<example 3> 
module struct_test; // this probably OK
  typedef struct {int a; bit b;} s_ab;
  s_ab ab;
  initial begin
    ab = '{15, 0};
    $display("ab.a should be 15: %0d", ab.a);
    $display("ab.b should be 0: %0d", ab.b);
  end
endmodule

<example 4>
module string_test;  // not sure about this one
  string s1, s2;
  int i;
  initial begin
    s1 = "hello";
    i = 7;
    $sformat(s2, "%s, i=%0d", s1, i);
    $display("Should print 'hello, i=7': %s", s2);
    $display("The word 'hello' has %0d characters", s1.len());
  end
endmodule

<example 5>
module class_test; // no chance of this working!
  class C;
    int a;
    string name;
    function new(string n = "unnamed", int v=0);
      name = n;
      a = v;
    endfunction
    function void print();
      $display("%s.a=%0d", name, a);
    endfunction
  endclass
  initial begin
    C c1 = new;
    C c2 = new("c2", 5);
    $display("Next line should say unnamed.a=0");
    c1.print();
    $display("Next line should say c2.a=5");
    c2.print();
  end
endmodule

All these examples run just fine in the full version.
-- 
Jonathan Bromley

Article: 144926
Subject: Re: SystemVerilog Verification Example using Quartus and ModelSim
From: gtwrek@sonic.net (Mark Curry)
Date: 15 Jan 2010 16:47:05 GMT
Links: << >>  << T >>  << A >>
In article <oi51l5dco9u5ncgo207pg8s8s4g6b0mb83@4ax.com>,
Jonathan Bromley  <jonathan.bromley@MYCOMPANY.com> wrote:
>On Fri, 15 Jan 2010 07:32:13 -0800 (PST), jjlindula wrote:
>
>[me]
>>> using SystemVerilog's object-oriented programming features,
>>> and those definitely require top-end features of the simulator
>>> that you simply won't get in the cheaper or "student" editions.
>
>[you]
>>Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will
>>that be okay?
>
>I'm afraid not.
>
>You will probably find that quite a few of the SV design features
>are fully supported in that version - interfaces, always_comb,
>structs, .* port connection, that sort of thing - but I would
>be astonished if you had access to any of the big-ticket
>verification stuff such as classes and randomization.  To
>find out, try these little examples.  Be sure to give the
>files ".sv" extension, or alternatively use the -sv compile
>option to the vlog command.
>
<snipped (good!) examples>

Actually, modelsim SE supports a large set of SystemVerilog.
All the examples work except for example 2 with
Modelsim SE.  SE supports all of the "design" features
of SystemVerilog as well as SystemVerilog classes. 
You need Questa for the constraint solver and SystemVerilog
Assertions.  Which makes sense as that's the harder
problem to solve for tool vendors.  

Now, I'm using SE - which is NOT a "Starter Edition" as the OP indicated.
I thought the starter product was "DE" or something like that.

Your mileage may vary - Mentor likes to slice and dice their
product definition / licensing to (confusing) extremes... 

--Mark


Article: 144927
Subject: Re: SystemVerilog Verification Example using Quartus and ModelSim
From: "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
Date: Fri, 15 Jan 2010 17:13:22 -0000
Links: << >>  << T >>  << A >>
> Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will
> that be okay?

As the others have said probably not.

The OEM /Starter Editions are all knobbled a bit, they run at reduced
speed or functionality.

The base 'normal' spec of Modelsim is PE (Properly Expensive), this is
superceded by SE (Specially Expensive).


[Particularly here in the UK where tools prices seem to be the same in 
as the guys from the States get them in $ (1 ~ $1.6)]



Nial. 



Article: 144928
Subject: Re: SystemVerilog Verification Example using Quartus and ModelSim
From: "HT-Lab" <hans64@ht-lab.com>
Date: Fri, 15 Jan 2010 18:14:15 -0000
Links: << >>  << T >>  << A >>

"Mark Curry" <gtwrek@sonic.net> wrote in message 
news:4b509c09$0$1597$742ec2ed@news.sonic.net...
> In article <oi51l5dco9u5ncgo207pg8s8s4g6b0mb83@4ax.com>,
> Jonathan Bromley  <jonathan.bromley@MYCOMPANY.com> wrote:
>>On Fri, 15 Jan 2010 07:32:13 -0800 (PST), jjlindula wrote:
>>
>>[me]
>>>> using SystemVerilog's object-oriented programming features,
>>>> and those definitely require top-end features of the simulator
>>>> that you simply won't get in the cheaper or "student" editions.
>>
>>[you]
>>>Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will
>>>that be okay?
>>
>>I'm afraid not.
>>
>>You will probably find that quite a few of the SV design features
>>are fully supported in that version - interfaces, always_comb,
>>structs, .* port connection, that sort of thing - but I would
>>be astonished if you had access to any of the big-ticket
>>verification stuff such as classes and randomization.  To
>>find out, try these little examples.  Be sure to give the
>>files ".sv" extension, or alternatively use the -sv compile
>>option to the vlog command.
>>
> <snipped (good!) examples>
>
> Actually, modelsim SE supports a large set of SystemVerilog.
> All the examples work except for example 2 with
> Modelsim SE.  SE supports all of the "design" features
> of SystemVerilog as well as SystemVerilog classes.
> You need Questa for the constraint solver and SystemVerilog
> Assertions.

SVA (and PSL) are supported in Modelsim DE (much cheaper than SE/Questa and it 
runs under Linux :-), but you are correct regarding the rest.

Hans
www.ht-lab.com


> Which makes sense as that's the harder
> problem to solve for tool vendors.
>
> Now, I'm using SE - which is NOT a "Starter Edition" as the OP indicated.
> I thought the starter product was "DE" or something like that.
>
> Your mileage may vary - Mentor likes to slice and dice their
> product definition / licensing to (confusing) extremes...
>
> --Mark
> 



Article: 144929
Subject: Re: SystemVerilog Verification Example using Quartus and ModelSim
From: "HT-Lab" <hans64@ht-lab.com>
Date: Fri, 15 Jan 2010 18:21:02 -0000
Links: << >>  << T >>  << A >>

"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote in 
message news:7rbm1tFrl4U1@mid.individual.net...
>> Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will
>> that be okay?
>
> As the others have said probably not.
>
> The OEM /Starter Editions are all knobbled a bit, they run at reduced
> speed or functionality.
>
> The base 'normal' spec of Modelsim is PE (Properly Expensive), this is
> superceded by SE (Specially Expensive).

:-)

>
>
> [Particularly here in the UK where tools prices seem to be the same in 
> as the guys from the States get them in $ (1 ~ $1.6)]

That is indeed very annoying, Mentor is not the only one doing it.

http://www.amanwithapencil.com/adobe.html

Hans
www.ht-lab.com


>
>
>
> Nial.
> 



Article: 144930
Subject: Re: Which WebPack for old Spartan and Spartan-2?
From: Gabor <gabor@alacron.com>
Date: Fri, 15 Jan 2010 10:49:24 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 15, 9:27=A0am, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Thu, 14 Jan 2010 18:36:05 -0500, "Leland C. Scott" <kc8...@arrl.net> w=
rote:
>
> >I'm looking for a good stable version of WebPack that supports the old
> >Spartan and Spartan-2 devices for legacy product maintenance. Any
> >recommendations?
>
> >Regards;
>
> I would suggest 7.1 as stable and pretty good; but check the documentatio=
n for
> supported devices before downloading.
>
> - Brian

I believe you need to go back to 4.2 for the original Spartan
series and XC4000 parts.  This version will also work with
Spartan 2 but not Spartan 2e.  You need at least 5.1 for
Spartan 2e, but if you're going to have multiple versions
you might as well use version 7.1  I have also heard that
version 6.3 is quite stable, although I skipped that version.
If you want a version that is sill supported, you might
consider 10.1 for the Spartan 2.

regards,
Gabor

Article: 144931
Subject: Re: SystemVerilog Verification Example using Quartus and ModelSim
From: Anssi Saari <as@sci.fi>
Date: Sat, 16 Jan 2010 00:40:08 +0200
Links: << >>  << T >>  << A >>
Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> writes:

> You will probably find that quite a few of the SV design features
> are fully supported in that version - interfaces, always_comb,
> structs, .* port connection, that sort of thing - but I would
> be astonished if you had access to any of the big-ticket
> verification stuff such as classes and randomization.  To
> find out, try these little examples.  Be sure to give the
> files ".sv" extension, or alternatively use the -sv compile
> option to the vlog command.

Well, since all I have at home is the Altera free edition and in fact
it seems it's the only free Modelsim out for Linux right now (well,
Actel has a 45 day trial), I tried these out. Only example complains
about missing support:

Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct  1 2009
-- Compiling module random_test
** Warning: ex2.sv(5): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.

And trying to run it gives:

# vsim random_test      
# Loading sv_std.std
# Loading work.random_test
VSIM 3> run -all
# ** Fatal: ex2.sv(5): Unable to check out verification license for randomize() feature.
#    Time: 0 ps  Iteration: 0  Process: /random_test/#INITIAL#3 File: ex2.sv
# Fatal error in Module random_test at ex2.sv line 5
# 
# HDL call sequence:
# Stopped at ex2.sv 5 Module random_test

But all the others work. Not bad for a freebie...

Article: 144932
Subject: Re: SystemVerilog Verification Example using Quartus and ModelSim
From: "jjlindula@hotmail.com" <jjlindula@hotmail.com>
Date: Fri, 15 Jan 2010 16:39:49 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 15, 2:40=A0pm, Anssi Saari <a...@sci.fi> wrote:
> Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> writes:
> > You will probably find that quite a few of the SV design features
> > are fully supported in that version - interfaces, always_comb,
> > structs, .* port connection, that sort of thing - but I would
> > be astonished if you had access to any of the big-ticket
> > verification stuff such as classes and randomization. =A0To
> > find out, try these little examples. =A0Be sure to give the
> > files ".sv" extension, or alternatively use the -sv compile
> > option to the vlog command.
>
> Well, since all I have at home is the Altera free edition and in fact
> it seems it's the only free Modelsim out for Linux right now (well,
> Actel has a 45 day trial), I tried these out. Only example complains
> about missing support:
>
> Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct =A01 2009
> -- Compiling module random_test
> ** Warning: ex2.sv(5): (vlog-2186) SystemVerilog testbench feature
> (randomization, coverage or assertion) detected in the design.
> These features are only supported in Questasim.
>
> And trying to run it gives:
>
> # vsim random_test =A0 =A0 =A0
> # Loading sv_std.std
> # Loading work.random_test
> VSIM 3> run -all
> # ** Fatal: ex2.sv(5): Unable to check out verification license for rando=
mize() feature.
> # =A0 =A0Time: 0 ps =A0Iteration: 0 =A0Process: /random_test/#INITIAL#3 F=
ile: ex2.sv
> # Fatal error in Module random_test at ex2.sv line 5
> #
> # HDL call sequence:
> # Stopped at ex2.sv 5 Module random_test
>
> But all the others work. Not bad for a freebie...

Thanks everyone for your input. My question is relating to the cost of
a simulator that supports SystemVerilog Verfication, just how much
should I expect to spend for one license? If its too expensive I'll
have to stick with sytem testbenches.

joe

Article: 144933
Subject: Re: Which WebPack for old Spartan and Spartan-2?
From: ghelbig <ghelbig@lycos.com>
Date: Fri, 15 Jan 2010 17:16:55 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 15, 10:49=A0am, Gabor <ga...@alacron.com> wrote:
> On Jan 15, 9:27=A0am, Brian Drummond <brian_drumm...@btconnect.com>
> wrote:
>
> > On Thu, 14 Jan 2010 18:36:05 -0500, "Leland C. Scott" <kc8...@arrl.net>=
 wrote:
>
> > >I'm looking for a good stable version of WebPack that supports the old
> > >Spartan and Spartan-2 devices for legacy product maintenance. Any
> > >recommendations?
>
> > >Regards;
>
> > I would suggest 7.1 as stable and pretty good; but check the documentat=
ion for
> > supported devices before downloading.
>
> > - Brian
>
> I believe you need to go back to 4.2 for the original Spartan
> series and XC4000 parts. =A0This version will also work with
> Spartan 2 but not Spartan 2e. =A0You need at least 5.1 for
> Spartan 2e, but if you're going to have multiple versions
> you might as well use version 7.1 =A0I have also heard that
> version 6.3 is quite stable, although I skipped that version.
> If you want a version that is sill supported, you might
> consider 10.1 for the Spartan 2.
>
> regards,
> Gabor

That matches my memory:  4.2i was the last version that supported the
Spartan and XC4000 series.  4.2i is "pre-XST", so high-level language
support is no longer available.

Version 6.3 is the last version with EDK support for the Spartan-II.

There may not be a (single) version that supports (all of) the Spartan-
I and Spartan-II devices.

$.02,
Gary.

Article: 144934
Subject: Altera Quartus II on Debian GNU/Linux
From: Giorgos Tzampanakis <gt67@hw.ac.uk>
Date: Sat, 16 Jan 2010 01:34:22 +0000 (UTC)
Links: << >>  << T >>  << A >>
I want to run Quartus on my Debian computer. I see that Altera doesn't
officially support Debian. Has anyone here managed to run Quartus on
Debian? What was your experience?

Article: 144935
Subject: Re: Altera Quartus II on Debian GNU/Linux
From: whygee <yg@yg.yg>
Date: Sat, 16 Jan 2010 03:23:10 +0100
Links: << >>  << T >>  << A >>
Hi,

Giorgos Tzampanakis wrote:
> I want to run Quartus on my Debian computer. I see that Altera doesn't
> officially support Debian. Has anyone here managed to run Quartus on
> Debian? What was your experience?

My experience with EDA tools on Linux is :
use RedHat (or its free sibling Fedora).
This is the same syndrom as Windows :
all the companies have a "corporate" version
of Linux distributed (and sold, and supported)
by RH so everybody uses it...
I have Debian and Slackware but am quite limited :-(
For example, Xilinx does not work well on Slackware.
I'm now configuring a brand new netbook
with Fedora and I expect many things to work there.

good luck and keep us informed,
Altera is on my install list !
yg
-- 
http://ygdes.com / http://yasep.org

Article: 144936
Subject: Re: Altera Quartus II on Debian GNU/Linux
From: General Schvantzkoph <schvantzkoph@yahoo.com>
Date: 16 Jan 2010 03:00:35 GMT
Links: << >>  << T >>  << A >>
On Sat, 16 Jan 2010 01:34:22 +0000, Giorgos Tzampanakis wrote:

> I want to run Quartus on my Debian computer. I see that Altera doesn't
> officially support Debian. Has anyone here managed to run Quartus on
> Debian? What was your experience?

It requires RHEL, it doesn't run on Fedora, don't know if it will work on 
Debian. I use a CentOS5.4 VM on top of Fedora 12, that works perfectly.

Article: 144937
Subject: Re: Altera Quartus II on Debian GNU/Linux
From: General Schvantzkoph <schvantzkoph@yahoo.com>
Date: 16 Jan 2010 03:04:51 GMT
Links: << >>  << T >>  << A >>
On Sat, 16 Jan 2010 03:00:35 +0000, General Schvantzkoph wrote:

> On Sat, 16 Jan 2010 01:34:22 +0000, Giorgos Tzampanakis wrote:
> 
>> I want to run Quartus on my Debian computer. I see that Altera doesn't
>> officially support Debian. Has anyone here managed to run Quartus on
>> Debian? What was your experience?
> 
> It requires RHEL, it doesn't run on Fedora, don't know if it will work
> on Debian. I use a CentOS5.4 VM on top of Fedora 12, that works
> perfectly.

BTW Xilinx tools mostly work on Fedora. The only thing that doesn't work 
is FPGA Editor which requires MOTIF, Fedora uses LESTIF which doesn't 
work. I use the same CentOS VM for any Xilinx tool that won't run 
directly on Fedora.

Article: 144938
Subject: Which WebPack for old Spartan and Spartan-2?
From: "Leland C. Scott" <kc8ldo@arrl.net>
Date: Sat, 16 Jan 2010 00:07:02 -0500
Links: << >>  << T >>  << A >>
I'm looking for a good stable version of WebPack that supports the old
Spartan and Spartan-2 devices for legacy product maintenance. Any
recommendations?

Regards;

Leland C. Scott
KC8LDO





Article: 144939
Subject: Re: Altera Quartus II on Debian GNU/Linux
From: Anssi Saari <as@sci.fi>
Date: Sat, 16 Jan 2010 13:52:48 +0200
Links: << >>  << T >>  << A >>
Giorgos Tzampanakis <gt67@hw.ac.uk> writes:

> I want to run Quartus on my Debian computer. I see that Altera doesn't
> officially support Debian. Has anyone here managed to run Quartus on
> Debian? What was your experience?

Well, I've run the Quartus beta in Debian 5.0 (Lenny). It seemed to
work just fine, but I only ran a couple of small example designs from
Altera.

Article: 144940
Subject: CPLD programming sequence XC9500
From: "gopal_amlekar" <gopal_amlekar@n_o_s_p_a_m.yahoo.com>
Date: Sat, 16 Jan 2010 06:29:25 -0600
Links: << >>  << T >>  << A >>
Hello,
I want to understand a few things about CPLD programming.

There is a configuration sequence followed for FPGA. For e.g. XAPP188 Table
7 on page 11 shows the device configuration sequence to transfer a bit
stream.
Similarly, is there any sequence for CPLD XC9500?

What I understood is that the .jed file is transferred instead of .bit file
in the SHIFT-DR state. Is this correct?

After transferring the .jed file does XC9500 also need the JSTART
instruction and switching to Run-Test-Idle state?

Is the entire .jed file transferred or there is some header or similar
information which is skipped?

Also, how to read the Device IDCODE of the CPLD? How to issue the IDCODE
instruction? 

Thanks for support...
	   
					
---------------------------------------		
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com

Article: 144941
Subject: Re: Altera Quartus II on Debian GNU/Linux
From: Anssi Saari <as@sci.fi>
Date: Sat, 16 Jan 2010 15:10:14 +0200
Links: << >>  << T >>  << A >>
General Schvantzkoph <schvantzkoph@yahoo.com> writes:

> BTW Xilinx tools mostly work on Fedora. The only thing that doesn't work 
> is FPGA Editor which requires MOTIF, Fedora uses LESTIF which doesn't 
> work.

To be exact, what Fedora does not have is old Openmotif 2.2 which
provides libXm.so.3. A rude hack is installing Openmotif 2.3 and
symlinking libXm.so.3 to libXm.so.4... I got it started then, but
opening files didn't work.

I've also noticed that in ISE 10.1, one of the xilperls is linked
against libdb-4.1, which also isn't in Fedora. EDK seems to call that
one on occasion. But that's a small library and easily compiled from
source.

Article: 144942
Subject: Re: CPLD programming sequence XC9500
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Sat, 16 Jan 2010 13:29:29 +0000 (UTC)
Links: << >>  << T >>  << A >>
gopal_amlekar <gopal_amlekar@n_o_s_p_a_m.yahoo.com> wrote:
> Hello,
> I want to understand a few things about CPLD programming.

> There is a configuration sequence followed for FPGA. For e.g. XAPP188 Table
> 7 on page 11 shows the device configuration sequence to transfer a bit
> stream.
> Similarly, is there any sequence for CPLD XC9500?

> What I understood is that the .jed file is transferred instead of .bit file
> in the SHIFT-DR state. Is this correct?

> After transferring the .jed file does XC9500 also need the JSTART
> instruction and switching to Run-Test-Idle state?

> Is the entire .jed file transferred or there is some header or similar
> information which is skipped?

> Also, how to read the Device IDCODE of the CPLD? How to issue the IDCODE
> instruction? 

The .jed describes a bitmap.The jedecfile has to be interpreted first into a
bitmap. The bitmap is then transfered in a complicated way
into the CPLD. The procedures are described somehow in the 1532 Jedec files
and in the files found when searching XILINX.com with "algorithm jedec"
("Device Programming Specification").

xc3sprog on sourceforge implements a reader for jedecfiles and a
XC95X(L|V) programmer with these documents and the sources found in the last
naxjp version with sources (naxjp-079). Read the documents and the sources 
http://sourceforge.net/projects/xc3sprog/develop
to understand what's going on.

B.t.w., for the Coolrunner 2 the Jedecfile describes the bits in a logical
order and before transfering in the XC2C CPLD the bits have to be scrambled
in physical order with .map files for the appropriate device found in the
Xilinx ISE/xbr/data folder.

For basic JTAG experiments , start at www.fpga4fun.com/JTAG.html

Bye

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 144943
Subject: Re: Simulation of VHDL code for a vending machine
From: KMS <kms34655@gmail.com>
Date: Sat, 16 Jan 2010 09:59:14 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 1 2009, 11:53=A0am, "glallenjr" <glalle...@gmail.com> wrote:
> Currently I am studying the "Circuit Design with VHDL" by Volnei A.
> Pedroni. On page 207 the run a simulation but do not provide the test
> bench. I would like to run the same simulation but I am not familiar with
> how to write a testbench. If possible please provide a testbench to mimic
> the simulation shown on page 207. If you are unfamiliar with this book or
> the simulation run, I would also appreciate ANY KIND of testbench which
> could simulate it's funcionality. Also if there are any errors with the
> code, please let me know! Your help is much appreciated! thank you!
>
> Here is the code we are trying to implement:
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
>
> entity vending_machine is
> =A0 =A0 Port ( clk, rst : IN =A0STD_LOGIC;
> =A0 =A0 =A0 =A0 =A0 =A0nickel_in, dime_in, quarter_in : IN =A0BOOLEAN;
> =A0 =A0 =A0 =A0 =A0 =A0candy_out, nickel_out, dime_out, quarter_out: OUT =
STD_LOGIC);
> end vending_machine;
>
> architecture fsm of vending_machine IS
> =A0 =A0 =A0 =A0 TYPE state IS (st0, st5, st10, st15, st20, st25, st30, st=
35, st40, st45);
> =A0 =A0 =A0 =A0 SIGNAL present_state, next_state: STATE;
>
> begin
> =A0 =A0 =A0 =A0 PROCESS(rst, clk)
> =A0 =A0 =A0 =A0 BEGIN
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 IF(rst=3D'1') THEN
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 present_state <=3Dst0;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ELSIF(clk' EVENT AND clk =3D'1') THEN
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 present_state <=3D next_s=
tate;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 END IF;
> =A0 =A0 =A0 =A0 END PROCESS;
>
> =A0 =A0 =A0 =A0 PROCESS(present_state, nickel_in, dime_in, quarter_in)
> =A0 =A0 =A0 =A0 BEGIN
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CASE present_state IS
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN st0 =3D>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 candy_out=
 <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 nickel_ou=
t <=3D'0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 dime_out =
<=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 IF (nicke=
l_in) THEN next_state <=3D st5;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ELSIF (di=
me_in) THEN next_state <=3D st10;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ELSIF (qu=
arter_in) THEN next_state <=3D st25;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ELSE next=
_state <=3Dst0;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 END IF;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN st5 =3D>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 candy_out=
 <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 nickel_ou=
t <=3D'0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 dime_out =
<=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 IF (nicke=
l_in) THEN next_state <=3D st10;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ELSIF (di=
me_in) THEN next_state <=3D st15;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ELSIF (qu=
arter_in) THEN next_state <=3D st30;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ELSE next=
_state <=3Dst5;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 END IF;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN st10 =3D>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 candy_out=
 <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 nickel_ou=
t <=3D'0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 dime_out =
<=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 IF (nicke=
l_in) THEN next_state <=3D st15;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ELSIF (di=
me_in) THEN next_state <=3D st20;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ELSIF (qu=
arter_in) THEN next_state <=3D st35;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ELSE next=
_state <=3Dst10;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 END IF;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN st15 =3D>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 candy_out=
 <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 nickel_ou=
t <=3D'0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 dime_out =
<=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 IF (nicke=
l_in) THEN next_state <=3D st20;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ELSIF (di=
me_in) THEN next_state <=3D st25;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ELSIF (qu=
arter_in) THEN next_state <=3D st40;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ELSE next=
_state <=3Dst15;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 END IF;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN st20 =3D>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 candy_out=
 <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 nickel_ou=
t <=3D'0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 dime_out =
<=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 IF (nicke=
l_in) THEN next_state <=3D st25;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ELSIF (di=
me_in) THEN next_state <=3D st30;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ELSIF (qu=
arter_in) THEN next_state <=3D st45;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ELSE next=
_state <=3Dst20;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 END IF;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN st25 =3D>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 candy_out=
 <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 nickel_ou=
t <=3D'0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 dime_out =
<=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 next_stat=
e <=3D st0;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN st30 =3D>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 candy_out=
 <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 nickel_ou=
t <=3D'1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 dime_out =
<=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 next_stat=
e <=3D st0;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN st35 =3D>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 candy_out=
 <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 nickel_ou=
t <=3D'0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 dime_out =
<=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 next_stat=
e <=3D st35;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN st45 =3D>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 candy_out=
 <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 nickel_ou=
t <=3D'0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 dime_out =
<=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 next_stat=
e <=3D st35;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 END CASE;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 END PROCESS;
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 END fsm;
>
> --------------------------------------- =A0 =A0 =A0 =A0
> This message was sent using the comp.arch.fpga web interface onhttp://www=
.FPGARelated.com



Hi,

I recommend you change your BOOLEANs to STD_LOGIC. Also, assuming this
is targeting real hardware, remember that the insertion of coins is
asynchronous and this is a synchronous design. You'll need some logic
for metastability and to create a one clock-wide pulse to your state
machine.

You can do something like this for a testbench:

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

library ieee;
use ieee.std_logic_1164.all;

-- Add your library and packages declaration here ...

entity vending_machine_tb is
end vending_machine_tb;

architecture TB_ARCHITECTURE of vending_machine_tb is
  -- Component declaration of the tested unit
  component vending_machine
    port
      (
      clk         : in  std_logic;
      rst         : in  std_logic;
      nickel_in   : in  std_logic;
      dime_in     : in  std_logic;
      quarter_in  : in  std_logic;
      candy_out   : out std_logic;
      nickel_out  : out std_logic;
      dime_out    : out std_logic;
      quarter_out : out std_logic
      );
  end component;

  -- Stimulus signals - signals mapped to the input and inout ports of
tested entity
  signal clk         : std_logic :=3D '0';
  signal rst         : std_logic :=3D '0';
  signal nickel_in   : std_logic :=3D '0';
  signal dime_in     : std_logic :=3D '0';
  signal quarter_in  : std_logic :=3D '0';
  -- Observed signals - signals mapped to the output ports of tested
entity
  signal candy_out   : std_logic;
  signal nickel_out  : std_logic;
  signal dime_out    : std_logic;
  signal quarter_out : std_logic;

  -- Add your code here ...

begin

  -- Unit Under Test port map
  UUT : vending_machine
    port map
      (
      clk         =3D> clk,
      rst         =3D> rst,
      nickel_in   =3D> nickel_in,
      dime_in     =3D> dime_in,
      quarter_in  =3D> quarter_in,
      candy_out   =3D> candy_out,
      nickel_out  =3D> nickel_out,
      dime_out    =3D> dime_out,
      quarter_out =3D> quarter_out
      );

  -- Add your stimulus here ...
  clk <=3D not clk after 50ns;

  Stimulus: process

    begin

      wait for 200 ns;

      rst <=3D'1';

      wait for 200 ns;

      rst <=3D'0';

      wait for 200 ns;

      nickel_in <=3D'1';

      wait for 1 us;

      nickel_in <=3D'0';

      wait for 1 us;

      dime_in <=3D'1';

      wait for 1 us;

      dime_in <=3D'0';

      wait for 1 us;

      quarter_in <=3D'1';

      wait for 1 us;

      quarter_in <=3D'0';

      -- add more...

      wait;

    end process;

end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_vending_machine of vending_machine_tb is
	for TB_ARCHITECTURE
		for UUT : vending_machine
			use entity work.vending_machine(fsm);
		end for;
	end for;
end TESTBENCH_FOR_vending_machine;

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

I didn't simulate your design to check its operation. This TB is
simple but it will get you started.

KMS

Article: 144944
Subject: Re: Altera Quartus II on Debian GNU/Linux
From: Mike Treseler <mtreseler@gmail.com>
Date: Sat, 16 Jan 2010 11:37:39 -0800
Links: << >>  << T >>  << A >>
Giorgos Tzampanakis wrote:
> I want to run Quartus on my Debian computer. I see that Altera doesn't
> officially support Debian. Has anyone here managed to run Quartus on
> Debian? What was your experience?

It works on opensuse.

       -- Mike Treseler


Article: 144945
Subject: Re: Altera Quartus II on Debian GNU/Linux
From: Michael S <already5chosen@yahoo.com>
Date: Sat, 16 Jan 2010 11:39:35 -0800 (PST)
Links: << >>  << T >>  << A >>


Giorgos Tzampanakis wrote:
> I want to run Quartus on my Debian computer. I see that Altera doesn't
> officially support Debian. Has anyone here managed to run Quartus on
> Debian? What was your experience?

Quartus on Ubuntu is one of requiring themes of Altera forum
See here for example for one of the latest threads:
http://alteraforums.org/forum/showthread.php?t=5163&highlight=ubuntu
There was a wiki entry somewhere. I think they forgot to mention that
on x64 before Quartus you have to install 32-bit libraries.

Since Ubuntu is based on Debian I'd guess most things said about
Ubuntu should be applicable to other Debian variants. More or less ;)

Article: 144946
Subject: Which WebPack for old Spartan and Spartan-2?
From: "Leland C. Scott" <kc8ldo@arrl.net>
Date: Sat, 16 Jan 2010 17:59:57 -0500
Links: << >>  << T >>  << A >>
I'm looking for a good stable version of WebPack that supports the old,
Spartan and Spartan-2 devices for legacy product maintenance. Any
recommendations?

Regards;

Leland C. Scott
KC8LDO




Article: 144947
Subject: Re: Simulation of VHDL code for a vending machine
From: Gabor <gabor@alacron.com>
Date: Sat, 16 Jan 2010 19:23:14 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 16, 12:59=A0pm, KMS <kms34...@gmail.com> wrote:
> Hi,
>
> I recommend you change your BOOLEANs to STD_LOGIC.

If you change the booleans to std_logic, you'll need
to change all the if statements to have a comparison
operator like
if (nickel_in) then . . .
becomes
if (nickel_in =3D '1') then . . .

If you're not trying to synthesize this logic, I'm not really
clear why you shouldn't use booleans, but then I would
normally have used Verilog.

On the other hand, if you make the code synthesizable,
you can use the Xilinx webpack to generate a testbench
template automatically.  That often saves the headache
of writing the signal declarations, instantiations and
initialization logic.

Regards,
Gabor

Article: 144948
Subject: Re: Altera Quartus II on Debian GNU/Linux
From: Giorgos Tzampanakis <gt67@hw.ac.uk>
Date: Sun, 17 Jan 2010 04:29:19 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 2010-01-16, Michael S <already5chosen@yahoo.com> wrote:

> Quartus on Ubuntu is one of requiring themes of Altera forum
> See here for example for one of the latest threads:
> http://alteraforums.org/forum/showthread.php?t=5163&highlight=ubuntu
> There was a wiki entry somewhere. I think they forgot to mention that
> on x64 before Quartus you have to install 32-bit libraries.
>
> Since Ubuntu is based on Debian I'd guess most things said about
> Ubuntu should be applicable to other Debian variants. More or less ;)

I think I'll try it and see what happens. However, I'm not perfectly clear
on whether the Linux version is free or not. If it's not, I'm not going to
bother going through the pain of installing it, I'll just use the Windows
version.

So, is it free? I'm talking about the Web Edition.

Article: 144949
Subject: Re: Altera Quartus II on Debian GNU/Linux
From: Michael S <already5chosen@yahoo.com>
Date: Sun, 17 Jan 2010 02:07:07 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 17, 6:29 am, Giorgos Tzampanakis <g...@hw.ac.uk> wrote:
> On 2010-01-16, Michael S <already5cho...@yahoo.com> wrote:
>
> > Quartus on Ubuntu is one of requiring themes of Altera forum
> > See here for example for one of the latest threads:
> >http://alteraforums.org/forum/showthread.php?t=5163&highlight=ubuntu
> > There was a wiki entry somewhere. I think they forgot to mention that
> > on x64 before Quartus you have to install 32-bit libraries.
>
> > Since Ubuntu is based on Debian I'd guess most things said about
> > Ubuntu should be applicable to other Debian variants. More or less ;)
>
> I think I'll try it and see what happens. However, I'm not perfectly clear
> on whether the Linux version is free or not. If it's not, I'm not going to
> bother going through the pain of installing it, I'll just use the Windows
> version.
>
> So, is it free? I'm talking about the Web Edition.

AFAIK, Web Edition for Linux is still in beta. Still, I see no
technical reasons why it wouldn't work for you.
https://www.altera.com/support/software/download/altera_design/quartus_we/dnl-quartus_we.jsp



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