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On 4/30/2013 10:26 PM, jg wrote: >> >> Ok, my goal. >> I need a uP and some logic, but I would like to do it with one part. >> 208 pins just won't fit into my package. > > That's both very broad, and vague. > How much uP and how much Logic ? > > You can get 'some logic' as small as QFN32, (Xilinx, Lattice) but if you really want both in one package, look at Cypress PSoC series. > > I think the new PSoC4 comes in 44 pins, and fits "a uP and some logic" > I am looking at using the SAM4L in a 48 TQFP @ 48Mhz. I can use software to create a 100nSec pulse. Thanks hamiltonArticle: 155151
"hamilton" <hamilton@nothere.com> wrote in message news:klr4oh$6h3$1@dont-email.me... > On 4/30/2013 10:26 PM, jg wrote: >>> >>> Ok, my goal. >>> I need a uP and some logic, but I would like to do it with one part. >>> 208 pins just won't fit into my package. >> >> That's both very broad, and vague. >> How much uP and how much Logic ? >> >> You can get 'some logic' as small as QFN32, (Xilinx, Lattice) but if you >> really want both in one package, look at Cypress PSoC series. >> >> I think the new PSoC4 comes in 44 pins, and fits "a uP and some logic" >> > > I am looking at using the SAM4L in a 48 TQFP @ 48Mhz. > > I can use software to create a 100nSec pulse. > > Thanks > > hamilton > Really? You can do most things in software, but creating 100ns pulse from a 48MHz clock without any hardware assist is sure gonna be tricky! PendleburyArticle: 155152
Greetings all, Has anyone hereabouts any experience with the use of Equivalence Checking tools in an FPGA context, for instance OneSpin EC-360 or Mentor FormalPro? Thanks in anticipation, Robert --------------------------------------- Posted through http://www.FPGARelated.comArticle: 155153
Dear Fellow Students and Researchers, I am sharing one useful announcement for those who are interested in writing and publishing research papers in the field of Reconfigurable Computing - FPGA, Embedded, VLSI, ASIC based designs. Please have a look to the following call for paper on Reconfigurable Computing. http://us6.forward-to-friend.com/forward/show?u=77fb907e5c2fb6cc2d4ffd642&id=214e464b5f http://www.hctl.org/STL/callforpaper.html Thank you! Best Regards, Raj Gaurav MishraArticle: 155154
I have a Microblaze design in SDK that I am trying to debug. I have an IP block with some registers that I can read and write. I have opened a new memory monitor window so I can see the registers updating. The trouble is that if I do a write to a register then the monitor does not update. I have to open another monitor to a new address range, then go back to the original monitor, then the register will show its new value. It as if the monitor is not being refreshed. Has anybody seen this? Thanks Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 155155
>The Xilinx built-in blockRAM FIFOs seem pretty nice, but is there any way t= >o infer them? Probably not. They're not that useful otherwise, unless you= > want to instantiate the primitive (not really), use CoreGen (no), and simu= >late using a unisim (who's got the time?). > >I always thought it'd be nice if Synplify could infer the Systemverilog pus= >h_front and pop_back queue commands as a FIFO and then use its own SynCore = >tool to make a FIFO from that. I might have to wait another 7-8 years for = >that one. > Yes, just create your own FIFO in Verilog or VHDL. I have done this and XST will create a BRAM FIFO for you. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 155156
On 09/05/2013 13:27, RCIngham wrote: > Greetings all, > > Has anyone hereabouts any experience with the use of Equivalence Checking > tools in an FPGA context, for instance OneSpin EC-360 or Mentor FormalPro? > > Thanks in anticipation, > Robert > > --------------------------------------- > Posted through http://www.FPGARelated.com > Hi Robert, From my limited experience I can tell that EC tools are a great solution for RTL to RTL but RTL to gate could give you some grey hairs. The problem with RTL to gate (or synthesis netlist) is that all synthesis tools complicate the EC process by adding/removing registers (register retiming, physical synthesis), choosing fsm encoding, inferring DSP's, convert gate clocks etc. Luckily a high-end synthesis tool (like Precision/Synplify) can help the EC process by generating an EC guide file (e.g. Precision's FYI file) which basically tells the EC tool what it has done. However AFAIK this guide file is not produce by XST/QNS/Vivado(?) so you might have to budget in a high-end synthesis tool. Hans www.ht-lab.comArticle: 155157
On Wednesday, April 17, 2013 8:16:08 PM UTC+2, Kevin Neilson wrote: > I used to work on the development a high-level design tool but it never w= orked out well. Plus, Verilog/VHDL keep getting more abstract all the time= . But I'm always interested to hear about these other tools. >=20 >=20 >=20 > If you can't use a lookup, the Horner-style Maclaurin for y=3Dexp(x) isn'= t too hard. Something like: >=20 >=20 >=20 > y=3D1; temp=3D1; >=20 > for n =3D 1 to N >=20 > temp =3D temp * x/n; >=20 > y =3D y + temp; >=20 > end >=20 >=20 >=20 > Accuracy depends on N. You can store the reciprocals of n in a ROM so yo= u don't have to do divides. If x is purely imaginary, just use a sin/cos l= ookup. The general idea for these tool seems promising. I have only tried vivado h= ls up until now and it looks really promising. Even though it does not seem= fully functional yet...These tool are still very immature but in my opinio= n they have the potential to become the norm quite soon... I managed to obtain a university license for the calypto catapult C. Does a= nyone know if the C-core feature is activated in such a license?=20Article: 155158
Jon, Did the synthesis tool infer a BRAM addressed by your own index counters, or did it infer a FIFO hard macro, using the built-in address HW in the FIFO? The OP was seeking the latter. I have not seen any synthesis tools automatically employ built-in FIFO address HW for RTL-described indexing counters and full/empty logic. AndyArticle: 155159
On Tuesday, April 23, 2013 10:13:42 PM UTC+2, Kevin Neilson wrote: > That's my rant. It's still pretty decent, but ought to be cheaper if it= 's going to coredump like freeware. I never had too many problems with Modelsim...But all hardware tools and si= mulators are very expensive. More than what would be logical for their cost= . But it is a small market with few competitive tools and since there is la= ck of options even these high prices are paid...Is there a open alternative= that is competitive? That would help the situation a lot. GHDL for example= ? Has anyone used it? does it fare well compared to other commercial simula= tors?Article: 155160
On 13/05/2013 14:56, turin231@gmail.com wrote: > On Tuesday, April 23, 2013 10:13:42 PM UTC+2, Kevin Neilson wrote: >> That's my rant. It's still pretty decent, but ought to be cheaper if it's going to coredump like freeware. > > I never had too many problems with Modelsim...But all hardware tools and simulators are very expensive. More than what would be logical for their cost. But it is a small market with few competitive tools and since there is lack of options even these high prices are paid...Is there a open alternative that is competitive? That would help the situation a lot. GHDL for example? Has anyone used it? does it fare well compared to other commercial simulators? > If your designs are not that large and you are happy with a single language then I would recommend the free OEM version of Modelsim. You can get it from Altera, Microsemi, Lattice etc. Xilinx Isim is also free and getting better with every version. Altera also has a paid for Modelsim AE version which sits just below PE in terms of speed and capacity, the price in the UK is about a 1000 pounds. Hans www.ht-lab.comArticle: 155161
Hello Robert! Am 09.05.13 14:27, schrieb RCIngham: > Has anyone hereabouts any experience with the use of Equivalence Checking > tools in an FPGA context, for instance OneSpin EC-360 or Mentor FormalPro? A while around I've take some action with OneSpin. The goal was to show that xst procuduce correct netlists. It was a bit tricky to get all running with scripts, but in the end it showed us some VHDL constructs that are problematic for the synthesizer. regards, BartArticle: 155162
Greetings all, Further to previous thread(s), has anyone here experience in setting up a linting tool such as Spyglass or LEDA? How long did it take? My thoughts are that a suite of test-case files is needed to test for detection of each code breach, and that preparing that would take a week or 2. Thanks in advance, Robert --------------------------------------- Posted through http://www.FPGARelated.comArticle: 155163
>Greetings all, > >Further to previous thread(s), has anyone here experience in setting up a >linting tool such as Spyglass or LEDA? How long did it take? > >My thoughts are that a suite of test-case files is needed to test for >detection of each code breach, and that preparing that would take a week or >2. > >Thanks in advance, >Robert > > > > >--------------------------------------- >Posted through http://www.FPGARelated.com > Setup can be very simple. Most tools use the same command line syntax as verilog so all you have to do is configure your code for synthesizable only and remove all the bus functional models from your testbench. You only need a suite if you have multiple configurations to test. One test checks for all violations in the same pass. John Eaton --------------------------------------- Posted through http://www.FPGARelated.comArticle: 155164
>>Greetings all, >> >>Further to previous thread(s), has anyone here experience in setting up a >>linting tool such as Spyglass or LEDA? How long did it take? >> >>My thoughts are that a suite of test-case files is needed to test for >>detection of each code breach, and that preparing that would take a week >or >>2. >> >>Thanks in advance, >>Robert >> >Setup can be very simple. Most tools use the same command line syntax as >verilog so all you have to do is configure your code for synthesizable >only >and remove all the bus functional models from your testbench. > >You only need a suite if you have multiple configurations to test. One >test >checks for all violations in the same pass. > > >John Eaton > A clarification. My intention is to test the tool(s), to check whether they find the rule breaches correctly... --------------------------------------- Posted through http://www.FPGARelated.comArticle: 155165
How long it will take to test the linting tool depends entirely on the number and complexity of the rules you are trying to enforce. If you have half a dozen simple rules, a couple of weeks is probably plenty of time. If you have a hundred rules, many of which are rather complex, two months might not be enough time. What code language are you wanting to lint, VHDL or Verilog? What kind of policies are you trying to enforce? Hazardous, frequently misused or mistake-prone usage? Maintainability guidelines (e.g. unused declarations)? Local style guide? AndyArticle: 155166
Hello, I'm trying to implement a DDR2-RAM-Controller for the ARTIX-7 FPGA and I have some "problems" during generation of the simulation models from the MIG-tool. Only the top-level of the DDR2-memory-controller is generated in VHDL, the instantiated moduls are generated in Verilog. This is a problem, because I don't have a mixed-language simulator. Are there any experiences using the DDR2-controller of the new 7-series from XILINX? Thank you, BodoArticle: 155167
On Friday, April 26, 2013 7:01:41 PM UTC-7, studywireless wrote: > >> > > >> Posted through http://www.FPGARelated.com > > > > > >Hi, > > >maybe the Xiliny Zynq 7000 Series is what you are loking for. > > >Dual Core ARM processor + FPGA fabric. > > > > > >Have a nice synthesis > > > Eilert > > > > > > > Hi Eilert, > > The problem with Xilinx Zynq are > > > > 1. Its relatively new and I am not sure if Xilinx can ship the board for us > > as other customers are waiting for it. So its going to take some time when > > Xilinx can start shipping to small customers like us (Its just my guess). > > > > 2. As the board is new, the software/tool support will be lagging the > > hardware. It will take some time before things stabilize. > > > > 3. It has 68 differential I/O, so that gives me 136 I/O pins, but we need > > more I/O pins. > > > > > > > > --------------------------------------- > > Posted through http://www.FPGARelated.com There are two Zynq boards available from Xilinx. The ZC702 with a 7Z020-CLG484 and the ZC706 with a 7Z045-FFG900 device and both boards are listed as in stock at Avnet. The ZC702 only has a single FMC LPC interface with 136 I/O, but the ZC706 has two FMC LPC interfaces for a total of 272 I/O. If you still want to use a PowerPC then the last version available would be on the ML507. This predates the adoption of the FMC standard and the expansion header only provides 64 I/O. Ed McGettigan -- Xilinx Inc.Article: 155168
That is really useful, are you powering the EPC2 with the JTAG or it used a power supply?Article: 155169
>How long it will take to test the linting tool depends entirely on the number and complexity of the rules you are trying to enforce. > >If you have half a dozen simple rules, a couple of weeks is probably plenty of time. If you have a hundred rules, many of which are rather complex, two months might not be enough time. > >What code language are you wanting to lint, VHDL or Verilog? > >What kind of policies are you trying to enforce? Hazardous, frequently misused or mistake-prone usage? Maintainability guidelines (e.g. unused declarations)? Local style guide? > >Andy VHDL. All of the above for preference. We have many rules. Precise number subject to next week's document review. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 155170
>Hello, >I'm trying to implement a DDR2-RAM-Controller for the ARTIX-7 FPGA and I >have some "problems" >during generation of the simulation models from the MIG-tool. Only the >top-level of the DDR2-memory-controller >is generated in VHDL, the instantiated moduls are generated in Verilog. >This is a problem, because I don't have a mixed-language simulator. >Are there any experiences using the DDR2-controller of the new 7-series from >XILINX? >Thank you, >Bodo > I had some experience with Virtex-4 and V5 DDR2 Controllers some time ago. The underlying logic was generated in VHDL, but the Micron DDR2 models were only available in Verilog. Fortunately, we had some mixed-language licences. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 155171
Does anybody have any experience using the kits below? http://www.dallaslogic.com/prod_niomite.htm http://www.dallaslogic.com/prod_quicgate.htm Looks like the only one currently available is the Quicgate board. I'm looking for something cheap and simple to learn VHDL and the Altera Quartus design tools. Right now I want to stick with Altera since one of our sister companies has used the Cyclone III device with and ARM IP core. Sooner or later I'm going to have to be responsible for supporting the design at our location. The free version of the design tools looks like it should fit my needs for now. Also I think I'll need a JTAG cable to program the chip. The one from Altera is rather expensive. How ever there is one that claims to be compatible. And for a whole lot less money. http://cutedigi.com/programmeremulator/altera-usb-blaster-fpga-cpld-compatible-jtag-cable.html Anybody used one of these? Regards; Leland C. Scott "If you love wealth more than liberty, the tranquility of servitude better than the animating contest of freedom, depart from us in peace. We ask not your counsel nor your arms. Crouch down and lick the hand that feeds you. May your chains rest lightly upon you and may posterity forget that you were our countrymen." Samuel Adams, (1722-1803)Article: 155172
On 05/22/2013 04:38 PM, Leland C. Scott wrote: > Does anybody have any experience using the kits below? > > http://www.dallaslogic.com/prod_niomite.htm > > http://www.dallaslogic.com/prod_quicgate.htm > > Looks like the only one currently available is the Quicgate board. I'm > looking for something cheap and simple to learn VHDL and the Altera Quartus > design tools. Right now I want to stick with Altera since one of our sister > companies has used the Cyclone III device with and ARM IP core. Sooner or > later I'm going to have to be responsible for supporting the design at our > location. The free version of the design tools looks like it should fit my > needs for now. > > Also I think I'll need a JTAG cable to program the chip. The one from Altera > is rather expensive. How ever there is one that claims to be compatible. And > for a whole lot less money. > > http://cutedigi.com/programmeremulator/altera-usb-blaster-fpga-cpld-compatible-jtag-cable.html > > Anybody used one of these? > > Regards; > > Leland C. Scott > > "If you love wealth more than liberty, the tranquility of servitude better > than the > animating contest of freedom, depart from us in peace. We ask not your > counsel > nor your arms. Crouch down and lick the hand that feeds you. May your chains > rest > lightly upon you and may posterity forget that you were our countrymen." > > Samuel Adams, (1722-1803) You may have a look at Terasic's DE0-Nano board http://www.terasic.com.tw/cgi-bin/page/archive.pl?No=593. It has the programming cable included on the board: you only need a conventional USB cable. And it also has some peripherials (A/D, accelerometer, some leds and some (very small!) switches and buttons. And no, I have no connection to them -I am just happy with this board! PereArticle: 155173
Does anybody know how big a BRAM or DSP48 is in terms of CLBs? (In a Virtex 5/6/7 part.) I was wondering, in terms of die size, whether it's better to use a multiplier or, say, four 36-bit fabric adders?Article: 155174
Hi Bodo, Bodo wrote: > Hello, > I'm trying to implement a DDR2-RAM-Controller for the ARTIX-7 FPGA and I > have some "problems" > during generation of the simulation models from the MIG-tool. Only the > top-level of the DDR2-memory-controller > is generated in VHDL, the instantiated moduls are generated in Verilog. > This is a problem, because I don't have a mixed-language simulator. > Are there any experiences using the DDR2-controller of the new 7-series > from XILINX? I'm currently doing a DDR3-design for Artix-7. The controller code itself is also always provided as Verilog, only the top level is VHDL. Besides, when using Vivado, the entire process of generating an example design is broken when you select VHDL for generation. To me it seems like the guy(s) doing the controller design is/are working with Verilog only. Kind of makes sense not to develop versions in two languages in parallel, but it used to be different... I did a DDR2-design on Virtex-4 with an older release of MIG (I believe it was 1.2 or so), and they provided VHDL-code for everything back then (which was good since it needed to be modified quite heavily). The only thign you could do is uses Xilinx' simulation tool, that comes with mixed-language support by default. Greetings, Sean
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