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I've received this email from David Vanden Bout (the author of the student edition lab book). > > Have you installed the patch files from www.xilinx.com? There used to be a problem with P&R hanging for very small designs that could be contained within a single CLB. The patch file fixes that problem. On the other hand, your design could be so large that the P&R software can't route it and respect the pin constraints you've specified. There's no easy fix for that. You may need to do some hand placement. > This does sound like the problem as to test the software I tried the first design in the lab work book (one CLB). This weekend I tried implementing the Quickstart stopwatch design and the place and route was fine. I've downloaded the service pack and I'll give this ago tonight. I'll let you know if this solves the problem. Darrell. In article <7jqnpo$c7r$1@nnrp1.deja.com>, gibsond@bournemouth.ac.uk wrote: > Hi, > > I'm trying to use the student edition of Xilinx F1.5. When I place and > route, if I've locked all the pin in the design to specific locations > the flow engine hangs when it gets to the constructive placer. If I > leave at least one pin un-located there is no problem. Is this a > limitation of the student edition or a known problem. Has anyone else > come across this? Is there a work around other that not locating all > the pins. It is a bit of a pain not being able to specify all > locations. > > Thanks, > > Darrell Gibson. > > Sent via Deja.com http://www.deja.com/ > Share what you know. Learn what you don't. > Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 16851
have you looked at the offerings from Lucent? Look at www.bytech.eurodis.com for hints on an easier route. Mark PS If you want more info please call Garry Bernstein on the telephone number listed.Article: 16852
Adrian Donegan <faulkes65@my-deja.com> wrote in message news:7k2u09$o28$1@nnrp1.deja.com... > The following companies offer solutions of varying price and > specification: Acculogic, Asset Intertech, Corelis, Data I/O, Goepel > and JTAG Technologies. All have home pages on the web. > > Has anyone experience of working with the above companies? We work with the Asset Intertech-tools for Boundary Scan, which are very good, but also quite expensive, maybe due to the fact that the tools are 'overqualified' for what we use them. We normally use it only for converting the .bsm/.hsm-files to .adb-files, and a header file for C, so we can write the whole test-program in C. Of course, the POD is used as well. (My first project I did, had - under test - a boundary scan chain with 9 elements, and all went well, and it was easy to use). We didn't use it for programming devices yet. Right now we are trying to work with the 'Parallel cable III' from Xilinx, in combination with Foundation Series software for programming, but it's not working completelly right now, because we don't have that many chains with only 'known' Xilinx parts, and we didn't succeed in making this work when unknown elements are used (but it's certainly not expensive). In another project we program a BS-element with the free software from Altera, as well as with the ByteBlaster-cable, for which they provide the information to make it on your own on their website http://www.altera.com/document/ds/dsbytemv.pdf. (link taken from newsgroup-message 'Re: JTAG: Altera & Xilinx' from Dave D'Aurelio in this NG from Sat.22nd May) I think every tool can be used on the field, at least, they aren't that big compared to a notebook/PC which will be needed for the above mentioned tools, and if a good test-program was written, they are easy to use. The Asset POD takes it power-supply from the computer it's connected to (I don't know how much power it uses, but that might be a negative point when using a portable computer with batteries), the Altera and XIlinx Cables take their power from the UUT. Next to that, we are trying to implement Boundary Scan without any other tools, but use the Parallel Port directly (although we'll probably need a buffer, probably from the HC244-family), and implement this in programs like HP Vee. I only work since a few months as a test-engineer, so, in other words: I'm no specialist to the matter, these are just my ideas on the subject. Greetings, AlainArticle: 16853
Hi, I am using FPGA Express 3.0 targetting the Xilinx Virtex family. I have 2 questions: Q1: Although my code has no errors and I can synthesize it, when I am using the "View Schematic" option, nothing happens. Does anybody know what might be wrong? Q2: It seems that I can only export the netlist from the optimized version chip. Is it possible to export the netlist for the non-optimized version? Thank you in advance, Bill PS: You can email me at balab@rice.eduArticle: 16854
Synplify version 5.1.1 (free with Actel Desktop) can't cope with the
following code. A very old version of Synplify (2.5) processes it
just fine; FPGA Express has no problem. The compiler blows up
on the line indicated, but in fact the culprit is a couple of
lines later: if I make the divisor a hard-coded constant instead
of the generic, all is well. Before I whinge to Synplicity, has
anyone come across this one? BTW, I know that the generic 'span'
has to be a power of 2; in the real thing there's an assert to
test that. This example intentionally lobotomised.
library ieee;
use ieee.std_logic_1164.all;
entity accum is
generic (span: natural := 8);
port (
clk, rst, UpNotDown: in std_logic;
sigma: out integer range -span to span-1
);
end accum;
architecture counter of accum is
-- compiler blows up at the following line:
signal q: integer range -span*span to span*span-1;
begin
sigma <= q/span; -- change to "q/8" and all is OK
count_proc: process (clk, rst)
begin
if rst='1' then
q <= 0;
elsif rising_edge(clk) then
if UpNotDown='1' then
q <= q+1;
else
q <= q-1;
end if;
end if;
end process;
end counter;
Jonathan Bromley
Article: 16855Hi. We are trying to program two Spartan XL FPGAs in daisy-chain slave serial mode. I think we have all the proper connections (e.g. M0 and M1 tied high, both devices connected to a common CCLK, DOUT of device 1 connected to DIN of device 2 and so on). However, neither device seems to accept our program (that is, INIT goes low at some point during initialization, indicating an error). The program bitstream contains the appropriate header information (0xFF02xxxx), and we're clocking the bits into the devices in what I believe to be the appropriate order (MSB of each longword first). One interesting clue, which one of you may be able to decipher, is that the 1st FPGA's DOUT pin continues to follow its DIN pin indefinitely, instead of going high after the first 40 bits of the bitstream. Thanks for any help, RonArticle: 16856
Well. The examples are quite comprehensive but what one needs may not be
the DSP-type FIR/IIR digital filter. The cost of such filters are very
high. (You have to implement A/D, multipliers, shifters and adders)
I would like to propose another one of much much low-cost. Try majority
filter. The advantage of it is easy, low-cost, simple but it has delay.
It depends on your application. Below shows a filter with 3 clock-cycle
delays. (the last clock cycle is to synchronize with the sys clock to
avoid glitches)
-- Leslie Yip (Loui)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Entity D_FILTER is
port( CLK,NRST: in std_logic;
S_IN: in std_logic_vector(1
downto 0);
DFIR: in std_logic;
S_OUT: out std_logic_vector(1 downto 0)
);
end D_FILTER;
architecture D_FILTER_ARCH of D_FILTER is
signal countA: std_logic_vector(1 downto 0);
signal countB: std_logic_vector(1 downto 0);
signal DS_OUT: std_logic_vector(1 downto 0);
begin
process(CLK, NRST)
begin
if NRST='0' then
countA <= (others=>'0');
elsif CLK='1' and CLK'event then
if S_IN(0) ='1' and countA /= 2 then
countA <= countA + 1;
elsif S_IN(0) ='0' and countA /= 0 then
countA <= countA - 1;
end if;
end if;
end process;
process(CLK)
begin
--if DFIR = '1' then
-- S_OUT <= S_IN;
--else
if CLK='1' and CLK'event then
if countA=2 then
DS_OUT(0) <= '1';
elsif countA = 0 then
DS_OUT(0) <= '0';
end if;
end if;
--end if;
end process;
process(DFIR, S_IN, DS_OUT)
begin
if DFIR = '1' then
S_OUT(0) <= S_IN(0);
else
S_OUT(0) <= DS_OUT(0);
end if;
end process;
process(CLK, NRST)
begin
if NRST='0' then
countB <= (others=>'0');
elsif CLK='1' and CLK'event then
if S_IN(1) ='1' and countB /= 2 then
countB <= countB + 1;
elsif S_IN(1) ='0' and countB /= 0 then
countB <= countB - 1;
end if;
end if;
end process;
process(CLK)
begin
--if DFIR = '1' then
-- S_OUT <= S_IN;
--else
if CLK='1' and CLK'event then
if countB=2 then
DS_OUT(1) <= '1';
elsif countB = 0 then
DS_OUT(1) <= '0';
end if;
end if;
--end if;
end process;
process(DFIR, S_IN, DS_OUT)
begin
if DFIR = '1' then
S_OUT(1) <= S_IN(1);
else
S_OUT(1) <= DS_OUT(1);
end if;
end process;
end D_FILTER_ARCH;
In article <7jvsnt$l1t$1@info-server.surrey.ac.uk>,
nospam_ees1ht@ee.surrey.ac.uk (Hans) wrote:
>
> >
> >I need to implement digital filters (in general) on FPGAs, I want to
do
> >it with VHDL descriptions.
> >Has anyone done this yet?
> >Is there any site where I can get any examples?
> >So, I need some bibliographics references about digital filters
> >implementation.
> >Thanks, and sorry by my poor english.
>
> Have a look at http://www.iowegian.com/loadfir.htm
>
> Hans.
>
>
--
Hong Kong
Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.
Article: 16857Hello everybody I would like to know whether VHDL can specify the delay time in FPGA / ASIC. I know modelling can write: DCHA <= CHA after 12 ns; -- CHA is input, DCHA is delayed output I implement, in the past, in ASIC by using not gates in series with schematic capture. --not --not -- not --not But VHDL synthesizer like FPGA Express will optimize the logic not(s), so would anyone know how to solve the problem? Leslie Yip (Loui) -- Hong Kong Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 16858
Additional: I know using D-flip-flop would be a solution. It can be made one/two/three clock delays but for very little delay, it requires a high-speed clock. In article <7k4cj3$9ju$1@nnrp1.deja.com>, Leslie Yip (/ Loui) <leslie.yip@asmpt.com> wrote: > Hello everybody > > I would like to know whether VHDL can specify the delay time in FPGA / > ASIC. I know modelling can write: > DCHA <= CHA after 12 ns; -- CHA is input, DCHA is delayed output > > I implement, in the past, in ASIC by using not gates in series with > schematic capture. --not --not -- not --not > > But VHDL synthesizer like FPGA Express will optimize the logic not(s), > so would anyone know how to solve the problem? > > Leslie Yip (Loui) > -- > Hong Kong > > Sent via Deja.com http://www.deja.com/ > Share what you know. Learn what you don't. > -- Hong Kong Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 16859
How are you entering your design? VHDL, AHDL, schematic? Unused pins default to Outputs that driven low. There are no built-in pullups so you shouldn't tristate unless something else is driving the pin. The Fast I/O option guarantees setup times not output drive. Everything is kept in the .acf file but I strongly suggest you use the menus to change this file instead of doing manual edits directly. Steve Markus Michel wrote in message <3760CA61.D8331EC1@kius.ch>... >1. Select the I/O pin. >2. Assign.Logic Options.Individual Logic Options.Fast I/O (on/off) > >Hope this helps >Markus > >Thomas Rathgen wrote: > >> Hi folks, >> >> does anyone out there have information how to configure io-pads with >> maxII. I'm wondering how to enable/disable output-ff - for example. >> Is there any information on the web about the available settings in >> maxII - the online help doesn't really help on this. >> >> Much thanks >> >> Tom > > >Article: 16860
I don't use the SPO's of some DP RAM's on XC40150XV. NGDBUILD and XNF2NGD give warnings. Do these warnings imply a possibly bad routing architecture? Shall I use the commands which ignore these pins? I have used following command but the warnings didn't go away: NET "dp_ram_spo<*>" TIG=TS01; Shall this TS01 be defined for write clock of the Dual Port RAM? Shall I use such a command to improve the performance? UtkuArticle: 16861
Hello, does anybody know, where I could get data of curcuits implemented on FPGAs? I would like to analyze multiple examples in order to obtain several statistical characteristics. The results will be a basis for my experiments within my degree dissertation. Thanks a lot for each proposal ! BerndArticle: 16862
In article <7jqnpo$c7r$1@nnrp1.deja.com>, gibsond@bournemouth.ac.uk wrote: > Hi, > > I'm trying to use the student edition of Xilinx F1.5. When I place and > route, if I've locked all the pin in the design to specific locations > the flow engine hangs when it gets to the constructive placer. If I > leave at least one pin un-located there is no problem. Is this a > limitation of the student edition or a known problem. Has anyone else > come across this? Is there a work around other that not locating all > the pins. It is a bit of a pain not being able to specify all > locations. > > Thanks, > > Darrell Gibson. > > Sent via Deja.com http://www.deja.com/ > Share what you know. Learn what you don't. > In case anyone is suffering from the same problem, the service pack and map update do cure the problem. Thanks to everyone for the help. Darrell Gibson. Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 16863
I'm just getting started with Foundation, and as an intro I am trying to mop up an old design of 3 GALS into one XC9500. The GALS were written in ABEL so I decided to implement 3 ABEL macros under a schematic top sheet, the macros being hopefully only slightly modified from the originals. The legacy Abel code uses output enables but Foundation doesn't seem to allow this in macros. This seems an odd restriction? The online help in one place seems to state this explicitly (and rather blandly!) but elsewhere seems to suggest it's OK. There is an example (but not actually worked out) of implementing a peripheral macro (D[0..7], /RD /WR /CS) where the /RD drives an OE control). This seems quite a useful thing to do and I would be disappointed if it's not possible. It has been suggested by a colleague that ABEL doesn't really work very well is this sort of environment, but that would be a shame as I suspect that this sort of GAL mopping up exercise is quite common, as would be the use of .OEs. Can anyone shed light on my darkness? -- Alan Hall, Ipswich, UKArticle: 16864
Hello,
i have three question come up when using Xilinx Foundation:
1) I got the following message by ngd2edif: undriven net "PRLD".
What does it mean, how can i prevent it ?
2) I got another message by ref_2_inst: dangling ports.
Is this a warning or error. Must/Can i do something to prevent it ?
3) I use the following in one of my designs with a XC95108:
Problem is that counter TAKT_TEILER is running with frequency
ABTAST_TAKT,
but MODE_MONITOR is really 0 und stays 0 the whole time (i have
checked it on DEBUG_OUT1,
pin 24). I have another line using MODE_MONITOR, where MODE_MONITOR
seems
also to be wrong. What i am doing wrong ?
Here are part of my source file:
TT0 NODE istype 'reg';
TT1 NODE istype 'reg';
TT2 NODE istype 'reg';
TT3 NODE istype 'reg';
TAKT_TEILER = [TT3..TT0];
DEBUG_OUT1 pin 24 istype 'com';
DEBUG_OUT5 pin 33 istype 'com';
DEBUG_OUT6 pin 34 istype 'com';
DEBUG_OUT7 pin 35 istype 'com';
DEBUG_OUT8 pin 36 istype 'com';
DEBUG_OUT1 = MODE_MONITOR;
TAKT_TEILER.CLK = ABTAST_TAKT & MODE_MONITOR & (ENABLE_COUNTER #
!ENABLE_TRIGGER);
TAKT_TEILER := TAKT_TEILER + 1;
TAKT_TEILER.AR = WANT_RES;
DEBUG_OUT5 = TT0;
DEBUG_OUT6 = TT1;
DEBUG_OUT7 = TT2;
DEBUG_OUT8 = TT3;
Greetings and many thanks for helping,
Martin Maurer (maurerm@in.tum.de)
Article: 16865Copied from Altera help about Fast I/O: A logic option, which can be applied to registers and combinatorial logic, that instructs the Compiler to implement logic in a logic cell or I/O cell that has a fast, direct connection to an input or I/O pin. Turning Fast I/O on can help maximize timing performance, for example, by permitting fast setup times. Turning Fast I/O off prevents the Compiler from implementing logic in a fast logic cell or I/O cell. You can also apply the Fast I/O logic option to pins with the following results: on input pins, the Compiler moves the assignment to the I/O cell or logic cell fed by the input; on output pins, it moves the assignment to the I/O cell or logic cell feeding the output. However, for logic in which an input pin (or an I/O pin) directly feeds a D flipflop that directly feeds an output pin (i.e., with no intervening logic), the MAX+PLUS II software moves a Fast I/O logic option on the output pin through the register and to the input pin. In this case, the register is implemented as an input I/O cell, not an output I/O cell. Hope this helps, Markus Steve W. wrote: > How are you entering your design? VHDL, AHDL, schematic? > Unused pins default to Outputs that driven low. There are no > built-in pullups so you shouldn't tristate unless something else > is driving the pin. The Fast I/O option guarantees setup times > not output drive. Everything is kept in the .acf file but I strongly > suggest you use the menus to change this file instead of doing > manual edits directly. > > Steve > > Markus Michel wrote in message <3760CA61.D8331EC1@kius.ch>... > >1. Select the I/O pin. > >2. Assign.Logic Options.Individual Logic Options.Fast I/O (on/off) > > > >Hope this helps > >Markus > > > >Thomas Rathgen wrote: > > > >> Hi folks, > >> > >> does anyone out there have information how to configure io-pads with > >> maxII. I'm wondering how to enable/disable output-ff - for example. > >> Is there any information on the web about the available settings in > >> maxII - the online help doesn't really help on this. > >> > >> Much thanks > >> > >> Tom > > > > > >Article: 16866
Hi, As part of my Masters project (1997) at the University of Edinburgh I researched how various circuit characteristics effected performance of autolayout on a Motorola FPGA. [Since then the Motorola FPGA has been discontinued.] I developed several techniques for analysing circuits and wrote simple 'c' programs to do this automatically. These techniques were based on research by Mike Hutton, University of Toronto (http://www.eecg.toronto.edu/~mdhutton/gen/). As far as I can remember characteristics monitored included the shape of fanout tree, number of different types of gates etc. As well as this I created circuits with certain characteristics using a tool developed by Mike Hutton called CircGen. If you are interested in any of these techniques please contact me and I'll send you a copy of the relevant parts of my thesis. Cheers, Ruthie Bernd Schmidt wrote: > Hello, > > does anybody know, where I could get data of curcuits implemented on > FPGAs? > > I would like to analyze multiple examples in order to obtain several > statistical characteristics. > The results will be a basis for my experiments within my degree > dissertation. > > Thanks a lot for each proposal ! > > Bernd -- Ruth Faulkner Design Engineer SoCDT UK, Motorola Tel: +44 (0)1606 815436 Fax: +44 (0)1606 815401 Email: r42856@email.sps.mot.comArticle: 16867
Hello Allan ! > I'm just getting started with Foundation, and as an intro I am trying to > mop up an old design of 3 GALS into one XC9500. The GALS were written in > ABEL so I decided to implement 3 ABEL macros under a schematic top > sheet, the macros being hopefully only slightly modified from the > originals. 1. You may not use enables ( ".oe") in a macro, but use instead the "obuft" symbol in the toplevel schematic (that means replacing "obuf" with "obuft") 2. Or you edit your 3 GAL design into one common Abel source without schematic, then you can leave it all unchanged. > > It has been suggested by a colleague that ABEL doesn't really work very > well is this sort of environment, but that would be a shame as I suspect > that this sort of GAL mopping up exercise is quite common, as would be > the use of .OEs. I find ABEL nice for CPLD (did no FPGA) designs, it took me only little effort to transfer older GAL based easyABEL ideas to XILINX CPLDs good luck, Bertram -- Bertram Geiger, bgeiger@EUnet.at HTL Bulme Graz-Goesting - AUSTRIAArticle: 16868
Hi all. I'm currently planning to purchase a Virtex prototype board. The VCC VW-300 ( http://www.vcc.com ) looks appealing. Any advise, suggestion, experience on this (or similar) board ? Thanks a lot, -- Davide.Article: 16869
Hello, This was brought up recently, but are there any erasable replacements for the 8 pin dip Altera EPC1? I'm really looking for something that is pin/function equivalent yet either electronically erasable or UV erasable. Thank you for the help. Garrick Kremesec University of Illinois gkremese@ews.uiuc.eduArticle: 16870
Problem solved, seems to be a layout problem (proper GND and decoupling).
TCK to GND with 1K pull down
TMS,TDI with 1K pull up to VCC
TDO only connected
After power down and again power up the EPC2 configured in a proper way the
connected FLEX devices...
Kind Regards to usergroup
Juergen Otterbach
Juergen Otterbach schrieb:
> Dear all,
> I tried to program an Altera EPC2 serial EEPROM via the JTAG interface.
> I used the Altera MAXPLUSII software and the byteblaster. But the JTAG
> chain check did not find the EPC2 on the bus.
> These is a simple 4 wire interface....and I checked the wires many
> times. Pull ups are all connected as given by the AN of altera..
> without success..
> Did anybody of you have some experience and success doing this job?.
> Please let me know if you use also an EPC2 in JTAG mode having similar
> problems....
>
> Kind Regards
Article: 16871Ron wrote: > Hi. We are trying to program two Spartan XL FPGAs in daisy-chain slave > serial mode. <snip> > > One interesting clue, which one of you may be able to decipher, is that the > 1st FPGA's DOUT pin continues to follow its DIN pin indefinitely, instead of > going high after the first 40 bits of the bitstream. > You are pointing at the problem: The first device never recognized the beginning of the header: eight (roughly) Ones, followed by 0010. My suspicion is that you are starting the serial loading too early, before the devices indicate that they are ready for this, by pulling INIT High. You must then wait another 4 microseconds before issuing the first CCLK ( see parameter TICCK at the botom of page 4-37 of the '99 data book ). Hope this helps Peter Alfke, Xilinx ApplicationsArticle: 16872
Bill- A1: Do you have a license for this feature? If so, then you may be selecting the hierarchy object under the chip instead of the chip itself. This is a common usage error. A2: You can only export an optimized chip. The FPGA Express 3.2 download will be available from the Viewlogic web site tomorrow. Regards, -Jim Bill Balabanos wrote: > Hi, I am using FPGA Express 3.0 targetting the Xilinx Virtex family. > I have 2 questions: > Q1: > Although my code has no errors and I can synthesize it, when I > am using the "View Schematic" option, nothing happens. > Does anybody know what might be wrong? > Q2: > It seems that I can only export the netlist from the optimized version chip. > Is it possible to export the netlist for the non-optimized version? > > Thank you in advance, > Bill > > PS: You can email me at balab@rice.edu -- -------------------------------------------------------- James R. Kipps FPGA Marketing Manager jkipps@viewlogic.com Phone: (508) 303-5246 --------------------------------------------------------Article: 16873
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postings in different sittings, you'll always have this file to go back
to.
Step 4). Use Netscape or Internet explorer and try searching for
various
newsgroups (on-line forums, message boards, chat sites,discussions.)
Step 5). Visit these message boards and post this article as a new
message
by highlighting the text of this letter and selecting paste from the
edit menu.
Fill in the Subject, this will be the header that everyone sees as they
scroll
through the list of postings in a particular group, click the post
message button.
You're done with your first one!
Congratulations...THAT'S IT! All you have to do is jump to different
newsgroups
and post away, after you get the hang of it, it will take about 30
seconds for each
newsgroup! **REMEMBER, THE MORE NEWSGROUPS YOU POST IN, THE MORE
MONEY YOU WILL MAKE!! BUT YOU HAVE TO POST A MINIMUM OF 200** That's
it! You will begin reciving money from around the world within days! You
may
eventually want to rent a P.O.Box due to the large amount of mail you
will receive.
If you wish to stay anonymous, you can invent a name to use, as long as
the
postman will deliver it. **JUST MAKE SURE ALL THE ADDRESSES ARE CORRECT.
** Now the WHY part: Out of 200 postings, say I receive only 5 replies
(a very low
example). So then I made $5.00 with my name at #6 on the letter. Now,
each of the
5 persons who just sent me $1.00 make the MINIMUM 200 postings, each
with my
name at #5 and only 5 persons respond to each of the original 5, that is
another
$25.00 for me, now those 25 each make 200 MINIMUM posts with my name at
#4
and only 5 replies each, I will bring in an additional $125.00!
Now,those 125
persons turn around and post the MINIMUM 200 with my name at #3 and only
receive 5 replies each, I will make an additional $626.00! OK, now here
is the fun
part, each of those 625 persons post a MINIMUM 200 letters with my name
at #2
and they each only receive 5 replies, that just made me $3,125.00!!!
Those 3,125
persons will all deliver this message to 200 newsgroups with my name at
#1 and if
still 5 persons per 200 newsgroups react I will receive $15,625,00! With
a original
investment of only $6.00! AMAZING! When your name is no longer on the
list, you
just take the latest posting in the newsgroups, and send out another
$6.00 to names
on the list, putting your name at number 6 again. And start posting
again. The thing
to remember is, do you realize that thousands of people all over the
world are joining
the internet and reading these articles everyday, JUST LIKE YOU are
now!!
Article: 16874
Leslie Yip (/ Loui) <leslie.yip@asmpt.com> wrote:
>Hello everybody
>
>I would like to know whether VHDL can specify the delay time in FPGA /
>ASIC. I know modelling can write:
> DCHA <= CHA after 12 ns; -- CHA is input, DCHA is delayed output
>
>I implement, in the past, in ASIC by using not gates in series with
>schematic capture. --not --not -- not --not
>
>But VHDL synthesizer like FPGA Express will optimize the logic not(s),
>so would anyone know how to solve the problem?
>
>Leslie Yip (Loui)
Leslie, depending on the amount of delay and the clock you have available,
you can do some creative synchronous logic that delays by a cycle or
half-cycle. I never trust an FPGA nor an ASIC to have the right delay
using your -not-not-not-not- solution -- too much can go wrong!
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
============================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 6000+ other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
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