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Presumably, the reference clock is stable as is the device parameters that affect the delay. If the output ratio is constant, then I would expect the delay to try to stay at one point until the temperature, voltage or reference change. That point may be (is probably) between two of the taps in the delay line, but since the exact duty cycle is probably not critical you could set it up with enough filtering (basically hysterisis) to keep it from jumping back and forth. Basically, the DLL picks the tap in a delay line that is closest to the delay that give the desired output. The finer the delay increment the less the size of the jump (which is why I was suggesting the carry logic might make a good tapped delay line). Alvin E. Toda wrote: > On Sun, 3 Oct 1999, Ray Andraka wrote: > > > Depending on delays in FPGAs is generally a bad practice, as the design becomes > > very sensitive to routing, as well as to process improvements. You might be able > > to reliably use the FPGA circuit delays by constructing a delay lock loop in the > > FPGA logic. It uses feedback to adjust how many delay elements are in the signal. > > You could probably use the carry chain as the delay line, as it has relatively > > short and consistent delays for each "tap". You will have to be careful about the > > routing off the taps though. I haven't tried this to see how well it works, but at > > 25 MHz, you might be able to pull it off. > > It would seem that another consideration would be the amount of > jitter on the clock edge that could be tolerated, since it would > seems that switching between taps would produce such behavior. > Perhaps since the clocking is only needed for a special device, > that specific asynchronous logic be designed so that the sequencing > of signals is always correct and IAW whatever signals come > back from the device. > > --al toda > > ########################################################### > Alvin E. Toda aet@lava.net > sr. engineer Phone: 1-808-455-1331 > 2-Sigma WEB: http://www.lava.net/~aet/2-sigma.html > 1363-A Hoowali St. > Pearl City, Hawaii, USA -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18151
:))Article: 18152
Victor, I'd be interested too; but as far as I recall, there's a CPLD (MAX7k or so) inside; so you would need the programming bitstream as well.... OTOH, the byte blaster consists only of some drivers; I think Altera has the schematic on their website. CU, Georg -- All opinions expressed are mine, not my employers'. Georg Diebel, Inst. for Integrated Circuits, Technical University of Munich Mailto:G_Diebel@lis.e-technik.tu-muenchen.de Phone: 0049-89-289-28578 Homepage: http://www.lis.e-technik.tu-muenchen.de/people/gd.htmlArticle: 18153
Hello all I don't know how to post a new message since I haven't accessed this site long. I can't locate the post new message link. My problem is: Is there anyone using the new device, "APEX" from ALtera? (EPF20K100) I don't know whether it can tolerate +5.0 Volt input. Of course it can output +5V using open drain but it doesn't mention about +5V input in datasheet. Will it be damaged? Thank you. Leslie Yip ymyip@ieee.org Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18154
Hi Leslie Yip (/ Loui) wrote: [...] > I don't know whether it can tolerate +5.0 Volt input. Of course it can > output +5V using open drain but it doesn't mention about +5V input in > datasheet. Will it be damaged? From the '99 DataBook: Absolute Max Ratings (Apex 20K family): DC in voltage : 4.6V DC operating conditions: Maximum High-Level input voltage : 4.1V Looks like it doesn't like 5V... Nicolas MATRINGE DotCom S.A. Conception electronique 16 rue du Moulin des Bruyeres Tel 00 33 1 46 67 51 11 92400 COURBEVOIE Fax 00 33 1 46 67 51 01 FRANCEArticle: 18155
This is a multi-part message in MIME format. --------------8D22BA24804B54ACD5A0339D Content-Type: text/plain; charset=koi8-r Content-Transfer-Encoding: 7bit Dear friends, I need to implement counter, clocked by clk, clk*2, clk*4 or clk*8 in Virtex. What do you think about clock multiplexing? Should I better use clock enable at appropriate periods? Your experiences in clock multiplexing will be appreciated --------------8D22BA24804B54ACD5A0339D Content-Type: text/x-vcard; charset=koi8-r; name="fliser6.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Ilia Oussorov Content-Disposition: attachment; filename="fliser6.vcf" begin:vcard n:Oussorov;Ilia x-mozilla-html:TRUE org:Robert Bosch GmbH, FV/FLI adr:;;P.O.Box 10 60 50;Stuttgart;;D-70049;Germany version:2.1 email;internet:fliser6@fli.sh.bosch.de tel;fax:+49-(0)-711-8117602 tel;work:+49-(0)-711-8117057 x-mozilla-cpt:;0 fn:Ilia Oussorov end:vcard --------------8D22BA24804B54ACD5A0339D--Article: 18156
In article <37F7BAF6.B3A3999C@ids.net>, Ray Andraka <randraka@ids.net> wrote: > Who is Norm? > > I'm not sure if the polynomial is correct for ATM or not. If the polynomial is > x^43 + 1 then you need 43 delays, not the 42 you have shown. Think of 1 as > x^0. In your drawing d0 should be e+q43. The '+' is the one bit sum, which is > the exclusive OR of the serial data input and the feedback data path(s). The > output can be taken off anywhere along the delay queue. You may want to take > it from immediately AFTER the first register if the design is highly pipelined > (as it would likely be for an FPGA implementation). This of course is the > scrambler. The descrambler has feed-forward instead of feedback, also by 43 > delays. > > Note that this scrambler is for serialized data, and as such may have too high > a bit rate to be done in the FPGA. My guess is that you are using an external > serializer, in which case you will need to transform this to the parallel form > for the scrambler rather than this serial one. The translation to a parallel > design is not trivial, and will take some time to derive. > > Rémi SEGLIE wrote: > > > I have to do an ATM scrambler in a FPGA and I wonder some questions : > > Norm says that the polynome is x^43+1, it's enabled only during payload and > > that the basic diagram is : > > > > ------------------------------- > > | __ __ __ | > > V | | | | | | | > > Ei -->+-----| |-- | |-- ... --| |--| > > | |__| |__| |__| > > V > > Yi > > > > (sorry for this poor draw) > > In others words : > > d0 = e + q42 > > d1 = q0 > > d2 = q1 > > ... > > d42 = q41 > > > > Is it right ? > > > > Thank you for your help. > > > > Rémi SEGLIE > > Hardware Design Engineer > > company : CELOGIC > > www : http://www.celogic.com/ > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka > > Tank you for your help Norm is for "standard" (sometimes I forget my basic english). I solve the problem on friday. The polynom is ok, I've done a mistake about where to get the output. A few answers to your email : About degree : I start from 0 (d0 for Q0) so there's, of course, 43 registers. The + means xor. Standards always show serial scrambler so I thought that it's easier to talk about them. In my FPGA, I transform the "serie" version in 8 bits parallel "version" , looking the content of all registers after 8 clock cycles. Of course you can use this method for 16 bits version. My mistake was to take the output after the register but it must be taken before ! (when I wrote this message I have any idea and I thought the diagram was wrong). I test it and it's ok !! Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18157
-- This is a personal view which may or may not be shared by my employer Atmel Sweden Ulf Samuelsson ulf 'a't atmel 'd'o't com >On Fri, 27 Aug 1999 15:40:07 -0400, Joshua Lamorie <jpl@xiphos.ca> >wrote: > >>Daniel Figuerola Estrada wrote: >>> Has anyone worked with those two technologies and could give his opinion >>> of them? >> >>Why look at them as mutually exclusive? We develop a controller board >>(very small, PCMCIA form-factor) that has both a microcontroller AND an >>FPGA. This allows for some amazing flexibility and utility. Especially >>because of all sorts of neat devices already on the die on the uC. >> We develop an FPGA which has a 30 MHz RISC processor *inside* the FPGA as a hardwired core. In addition it has both SRAM and other peripherals like UARTs etc. Best of both worlds!!! >> >>Joshua Lamorie >>Systems Designer >>Xiphos Technologies Inc. >Article: 18158
Actually, the output can be taken from after any register. The output from any register is just a copy of the input to the first register delayed by a number of clocks. rseglie@my-deja.com wrote: > Tank you for your help > > Norm is for "standard" (sometimes I forget my basic english). > > I solve the problem on friday. The polynom is ok, I've done a mistake > about where to get the output. > > A few answers to your email : > About degree : I start from 0 (d0 for Q0) so there's, of course, 43 > registers. > The + means xor. > > Standards always show serial scrambler so I thought that it's easier to > talk about them. > In my FPGA, I transform the "serie" version in 8 bits parallel "version" > , looking the content of all registers after 8 clock cycles. Of course > you can use this method for 16 bits version. > > My mistake was to take the output after the register but it must be > taken before ! (when I wrote this message I have any idea and I thought > the diagram was wrong). > I test it and it's ok !! > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18159
If the clock multiples are truly integer multiples, then why not always clock the counter with the 8x clock and use clock enables when clocking is required. It's a lot safer than muxing clocks, and it allows you to use the clock distribution the way it was intended. Ilia Oussorov wrote: > Dear friends, > I need to implement counter, clocked by clk, clk*2, clk*4 or clk*8 in > Virtex. What do you think about clock multiplexing? Should I better use > clock enable at appropriate periods? > Your experiences in clock multiplexing will be appreciated > > ------------------------------------------------------------------------ > > Ilia Oussorov <fliser6@fli.sh.bosch.de> > Robert Bosch GmbH, FV/FLI > > Ilia Oussorov > Robert Bosch GmbH, FV/FLI <fliser6@fli.sh.bosch.de> > HTML Mail > P.O.Box 10 60 50 Fax: +49-(0)-711-8117602 > Stuttgart Work: +49-(0)-711-8117057 > D-70049 Netscape Conference Address > Germany Netscape Conference DLS Server > Additional Information: > Last Name Oussorov > First Name Ilia > Version 2.1 -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18160
DesignPRO is a contract engineering design organization based in Ottawa, Canada. We specialize in digital chip development, and offer a complete spectrum of turnkey product development services, including: * system design; * chip and board specification; * FPGA and ASIC design and verification; * PCB design and manufacturing, * DSP coding; * firmware and software development; * hardware and software integration testing; With EXPERIENCE and REUSABLE BLOCKS in the following areas: * ATM & Packet over SONET/SDH - X@STS-1, X@STS-3c, X@STS-12c, X@STS-48c * High speed access products, xDSL, T1/E1, Cable Modem; * Crosspoint Switch Technology @ 5 Gbps; * ATM, PPP, 8b10b, HDLC, SDLC, TCP/IP, UTOPIA (Level I, II & III), Ethernet, PCI, VME; * Wireless - CDMA, GPS, LMDS, PCS. DesignPRO is a proud member of the Altera Consultant Alliance Program (ACAP) and the Xilinx XPERT Program. DesignPRO's list of customers includes many of the key communications companies in the world, including Nortel Networks, Lucent Technologies - Ascend Communications, Motorola, Newbridge Networks, and many other mid-size and smaller firms. For additional information, visit our website at www.designpro.org or contact, Andrew Bunsick General Manager DesignPRO Inc. www.designpro.org abunsick@designpro.org Phone: (613) 596-5030 Fax: (613) 596-5163Article: 18161
Hi, I wondering how much Programmable Design work is done using ABEL. I find it useful for small to medium CPLD designs. I am curious about how widespread is its use? Anyone else use it on a regular basis? Bob WArticle: 18162
I have figured out what I need to do to obtain a (possibly unroutable) design with maximal packing: use the option "map -c 1". Thanks to Xilinx for their help. This will pack a design as much as it can, without needing to know ahead of time how many slices or CLB it takes, no need to floorplan either to get the answer. Then I do the sum of all the small modules assuming maximal packing, then I assume packing won't be better than 85% on the overall design and I get an estimate for the whole design. Martin Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18163
Damjan Lampret wrote:
> Hi,
>
> anyone knows of any free SDRAM and/or PCI controllers?
>
> regards, Damjan
For a PCI-bus interface (in VHDL) try
http://www.tkt.cs.tut.fi/~havu/pci/models.html
For other models you may also check out the VHDL FAQ at
http://www.vhdl.org/comp.lang.vhdl/ .
Section 3.2 of part 1 lists a couple of VHDL model sites.
--
Edwin
Article: 18164I only use Abel for PLD design. Anything larger than a small PLD, I use an FPGA. Sometimes in the FPGA I use Abel for state machines or combinatorial logic...but keep my data path in schematic. Easy to use, and works great. Bob Weber <rweber@txc.com> wrote in article <6g4K3.1176$GH4.2498@client>... > Hi, > > I wondering how much Programmable Design work is done using ABEL. I find it > useful for small to medium CPLD designs. I am curious about how widespread > is its use? > > Anyone else use it on a regular basis? > > Bob W > > > >Article: 18165
Paper Deadline Extended to October 7:
FPGA 2000
Call for Papers
Eighth ACM International Symposium on Field-Programmable Gate Arrays
Monterey, California
February 10-11, 2000
Submissions Due: October 7, 1999
The annual ACM/SIGDA International Symposium on Field-Programmable
Gate Arrays is the premier conference for presentation of advances in
all areas related to FPGA technology. For FPGA 2000, we are
soliciting submissions describing novel research and development in
the following (and related) areas of interest:
* FPGA Architecture: Logic block & routing architectures, I/O
structures and circuits, new architectures, Field-Programmable
Interconnect Chips and Devices (FPIC/FPID), Field-Programmable Analog
Arrays (FPAA).
* CAD for FPGAs: Placement, routing, logic optimization, technology
mapping, system-level partitioning, logic generators, testing and
verification. CAD for FPGA-based accelerators.
* Applications: Innovative use of FPGAs, exploitation of FPGA
features, novel circuits, high-performance and
low-power/mission-critical applications, DSP techniques, uses of
reconfiguration, FPGA-based cores.
* FPGA-based computing engines: Compiled accelerators, reconfigurable
computing, adaptive computing devices, systems and software.
* Rapid-prototyping: Fast prototyping for system level design,
Multi-Chip Modules (MCMs), logic emulation.
Authors are invited to submit PDF of their paper (12 pages maximum) by
October 1, 1999 via E-mail to hauck@ee.washington.edu. Notification
of acceptance will be sent by November 17, 1999. The authors of the
accepted papers will be required to submit the final camera-ready copy
by December 1, 1999. A proceedings of the accepted papers will be
published by ACM, and included in the Annual ACM/SIGDA CD-ROM
Compendium publication. Address questions to:
Scott Hauck
Program Chair, FPGA 2000
Dept. of EE, University of Washington
Box 352500
Seattle, WA 98195-2500
Phone: (206) 543-2150
Fax: (206) 543-3842
Email: hauck@ee.washington.edu
General Chair: Steve Trimberger, Xilinx
Program Chair: Scott Hauck, U. of Washington
Finance Chair: Sinan Kaptanoglu
Publicity Chair: Herman Schmit, Carnegie Mellon
Program Committee:
Miron Abramovici, Lucent David Lewis, U. of Toronto
Ray Andraka, Andraka Consulting Fabrizio Lombardi, Northeastern U.
Mike Bershteyn, Quickturn Wayne Luk, Imperial College
Michael Butts, Synopsys Margaret Marek-Sadowska, UCSB
Jason Cong, UCLA Jan Rabaey, UCB
Eugene Ding, Lucent Jonathan Rose, U. of Toronto
Carl Ebeling, U. of Washington Martine Schlag, UCSC
Reiner Hartenstein, U. Kaiserslautern Herman Schmit, Carnegie Mellon
Scott Hauck, U. of Washington Tim Southgate, Altera
Brad Hutchings, BYU Russ Tessier, U. Mass. - Amherst
Sinan Kaptanoglu, Actel Steve Trimberger, Xilinx
Tom Kean, Algotronix John Wawrzynek, UCB
Martin Wong, UT at Austin
Sponsored by ACM SIGDA, with support from Xilinx, Altera, Actel,
Lucent, Vantis and Cypress.
Please visit the web site <http://www.ece.cmu.edu/~fpga2000> for more
information.
Article: 18166Abel was and is the standard for EPLD and low to moderate size FPGA designs. Abel is much more compact than VHDL and much more focused for FPGA designs than VHDL. Typically 1 page of Abel equals 5 pages of VHDL. If you have Data I/O (Mincs) Synario w/ VHDL you can do designs in either Abel or VHDL and automatically convert from one another. Abel is real handy if you need to change devices across manufactures or accurately compare different devices. You can start a design in Xilinx and finish it with Lattice painlessly. Simply choose the new device, regenerate the device fit and your are done. .Article: 18167
This example still works, but it's all a matter of understanding the
architecture and the capabilities of the synthesis tool.
So for xc3000/xc5200, you can create an asynchronous preset by adding
inverters to both d and q pins of the flip-flop. The libraries guide
demonstrates this method for the xc5200 FDP.
assign in_1 = ~in_1;
always @(posedge clk or posedge reset)
if (reset)
out_1 <= 0;
else
out_1 <= in_1;
assign out = ~out_1;
Joseph H Allen wrote:
>
> In article <FIyJ7v.2uv@world.std.com>,
> Joseph H Allen <jhallen@world.std.com> wrote:
>
> >Also will this always work correctly with inferred D flip flops?
>
> In fact this method does not work correctly. For example, if I want a
> flip-flop which is to be preset in a family which does not have a preset
> option built into the CLB flip flops (like XC5000 series), this problem will
> occur:
>
> When you bring the reset signal out to a pin it works correctly, and
> 'out' is 1 after configuration.
>
> module top(in,out,reset,clk)
> input in,reset,clk;
> output out;
> reg out;
>
> always @(posedge clk or posedge reset)
> if(reset) out <= 1;
> else out <= in;
>
> endmodule
>
> But when I follow the direction you suggest, it fails and out is 0 after
> configuration:
>
> module top(in,out,clk)
> input in,clk;
> output out;
> reg out;
>
> wire reset;
>
> always @(posedge clk or posedge reset)
> if(reset) out <= 1;
> else out <= in;
>
> endmodule
>
> There really needs to be a module like 'ROC' for VHDL.
> --
> /* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
> int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
> +r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
> ]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
--
Paulo //\\\\
| ~ ~ |
( O O )
__________________________________oOOo______( )_____oOOo_______
| . |
| / 7\'7 Paulo Dutra (paulo@xilinx.com) |
| \ \ ` Xilinx hotline@xilinx.com |
| / / 2100 Logic Drive (800) 255-7778 |
| \_\/.\ San Jose, California 95124-3450 USA |
| Oooo |
|________________________________________oooO______( )_________|
( ) ) /
\ ( (_/
\_)
Article: 18168Hi, I need a link for download the M1 foundation software, or whatever to make place and route and download the design to a xc4000 FPGAs series using a XChecker cable. Regards, Marcelo MoisanArticle: 18169
Depends on what you are doing. For mathemeatically intense data-path stuff, VHDL code can be more compact than ABEL. VHDL is also supported by more simulators etc. John Cain wrote: > Abel was and is the standard for EPLD and low to moderate size FPGA designs. > Abel is much more compact than VHDL and much more focused for FPGA designs > than VHDL. Typically 1 page of Abel equals 5 pages of VHDL. If you have > Data I/O (Mincs) Synario w/ VHDL you can do designs in either Abel or VHDL > and automatically convert from one another. > > Abel is real handy if you need to change devices across manufactures or > accurately compare different devices. You can start a design in Xilinx and > finish it with Lattice painlessly. Simply choose the new device, regenerate > the device fit and your are done. > > . -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18170
In article <37F938C9.70273FBC@xilinx.com>,
Paulo Dutra <paulo@xilinx.com> wrote:
>This example still works, but it's all a matter of understanding the
>architecture and the capabilities of the synthesis tool.
>So for xc3000/xc5200, you can create an asynchronous preset by adding
>inverters to both d and q pins of the flip-flop. The libraries guide
>demonstrates this method for the xc5200 FDP.
Uh huh. So bascially it's broken and you can't expect code which takes
advantage of the abstractions offered by verilog to work properly.
Hopefully this will be fixed in a future version of foundation express.
Actually it's not that big of a deal. You just have to waste a pin for a
redundant reset signal.
I didn't try it, but I guess this will be broken in XC4000 too. XC4000 FFs
have presets, but the tool will not know to configure them that way if the
reset line has been optimized out.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 18171http://www.xilinx.com if you have a current license. I don't think you need a license for the download, but you will for PAR. Marcelo Moisan wrote: > Hi, I need a link for download the M1 foundation software, or whatever to > make place and route and download the design to a xc4000 FPGAs series > using a XChecker cable. > > Regards, Marcelo Moisan -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18172
On Tue, 05 Oct 1999 13:01:38 GMT, flavioas@my-deja.com wrote: > > > Hi, > > We are looking for some papers on how to >implement multiplierless filter structures in >FPGAs. Papers like "Design of multiplierless >digital data transmission filters with >powers-of-two coefficients" H. Samueli. and others >talking about "CSD coefficients" will be helpfull. >Can any one help? > We are trying to subscribe to this newsgroup, >using outlook express to connect to the server : >nntp-serv.cl.cam.ac.uk, and getting the message: >"you have no permission to talk to this server". >So, How to subscribe? > > Thanks in advance, > > Flávio Andrade > > >Sent via Deja.com http://www.deja.com/ >Before you buy. There are some interesting papers at the U of K. on automatic filter generation using sparce numbers of ones in the coefficients to minimize the size of the constant multipliers. try: ftp://ftp.tisl.ukans.edu/pub/projects/DSP/FPGA/Filters_and_CAD.pdf for one. Dave DeckerArticle: 18173
On Mon, 27 Sep 1999 02:08:29 GMT, simon_bacon@my-deja.com wrote: >Does anyone have a definition of the REV on the Virtex flip-flops? >A search at Xilinx reveals nothing. This connection pairs with >INIT on each FF -- INIT seems to be set/reset. INIT connects to the slice's SR input, and REV connects to the slice's BY input. these two are documented in the data sheet - SR is, among other things, the sync or async 'set', and BY is, among other things, the sync or async 'reset' (the ac specs give a setup/hold on SR/BY for sync operation, and a delay to XQ/YQ for async operation). in this context, 'set' means that the F/F is loaded with the value specified in the configuration, and 'reset' means that the other value is loaded. an INIT=S attribute would give a configuration '1', and INIT=R gives a configuration '0'. if you look at an FDCE in fpga editor, for example, you'll see that your async reset signal is connected to SR/INIT, with the F/F configuring to '0'. evanArticle: 18174
Hi,
We are looking for some papers on how to
implement multiplierless filter structures in
FPGAs. Papers like "Design of multiplierless
digital data transmission filters with
powers-of-two coefficients" H. Samueli. and others
talking about "CSD coefficients" will be helpfull.
Can any one help?
We are trying to subscribe to this newsgroup,
using outlook express to connect to the server :
nntp-serv.cl.cam.ac.uk, and getting the message:
"you have no permission to talk to this server".
So, How to subscribe?
Thanks in advance,
Flávio Andrade
Sent via Deja.com http://www.deja.com/
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