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Hi Simon, The circuit in the applications note works. Did you connect VCC and GND to 2032? You need external power supply to 2032. Mankit Simon Moon <simonmoon@bigfoot.com> wrote in article <7onmrl$ag1$1@spitting-spider.aracnet.com>... > I am trying to program a Lattice ispLSI2032 part with a homemade cable. Using > AN8003.pdf for connections between the '244 and the parallel port and the 2032 > datasheet for pin connections on the chip, I constructed a circuit which is > identical to one of the circuits found in the newsgroups and on the web, but > differs from 3 other circuits I found later. > > Since the circuit doesn't work, I was wondering if anyone has a circuit KNOWN > to work with the 2032... > > ??? >Article: 17551
Just an idea ... How do you reset/initialize your registers? Make sure your registers are set/reset properly at startup, otherwise simulation and the real application will differ completely. See STARTUP, STARTBUF. Sandra Dominikus wrote: > > Hi, > > I have a Problem with a XILINX 4010E. > I have written a source code in VHDL, synthesized it with LEONARDO, > placed and routed with ALLIANCE and then tried to implement this on a > XILINX 4010E (download with XCHECKER cable ). > After all these steps, I simulated the design with MODELSIM, and up to > the placed design it all works fine, but the implementation on XILINX > makes troubles. > > e.g. I have a shiftregister in my design, all control-logic-signals > (clk, enable) are ok, the timing of the signals is ok, the input data > are ok, but the final content of the register is not, what it should be. > > an other example is a "memory", when a learn-signal is high, there is a > register where a given input-data should be written into: the learn > signal and the input data are ok, what is stored in the registers > afterwards is completely different from the original input-data > > The whole design is synchronous and the clk works at about 1 MHz (seems > not too high). > > has anyone some idea, what could be the reason for this strange > behaviour ? > > THANX, > Sandra Dominikus.Article: 17552
Can anyone tell me something about Analog FPGA's ? I check programmable logic jump station, and it appears as though most of the analog FPGA's are dead or dying. I had heard something about NASA developing a new type of analog FPGA for use in evolutionary electronics but cannot find anything else about this. Cheers -- --------------------------------------------------------------------------------------------- David Braendler http://gene.bsee.swin.edu.au/daveb/index.htm Centre for Intelligent Systems Swinburne University of Technology --------------------------------------------------------------------------------------------Article: 17553
In article <37AAF9E0.EA5D2BD5@studenten.iaik.tu-graz.ac.at>, Sandra Dominikus <sdominik@studenten.iaik.tu-graz.ac.at> writes >Hi, > >I have a Problem with a XILINX 4010E. >I have written a source code in VHDL, synthesized it with LEONARDO, >placed and routed with ALLIANCE and then tried to implement this on a >XILINX 4010E (download with XCHECKER cable ). >After all these steps, I simulated the design with MODELSIM, and up to >the placed design it all works fine, but the implementation on XILINX >makes troubles. > >e.g. I have a shiftregister in my design, all control-logic-signals >(clk, enable) are ok, the timing of the signals is ok, the input data >are ok, but the final content of the register is not, what it should be. > >an other example is a "memory", when a learn-signal is high, there is a >register where a given input-data should be written into: the learn >signal and the input data are ok, what is stored in the registers >afterwards is completely different from the original input-data > >The whole design is synchronous and the clk works at about 1 MHz (seems >not too high). > >has anyone some idea, what could be the reason for this strange >behaviour ? > >THANX, > Sandra Dominikus. > Are you programming via JTAG? If so, this is a known issue. check out Xilinx answer #6136 from their website. -- Kindest Regards | gerry@devantech | We manufacture Pic programmers, 8031, Gerald Coe | .demon.co.uk | 68302, 64180, 80C188EB cpu modules. http://www.devantech.demon.co.uk | Full custom uP control systems designed.Article: 17554
Hi,
I have a homebrew card that contains an inmos T425 transputer connected
to a Xilinx XC4000E-3 FPGA and a Motorola DSP56002 DSP processor.
I ordered the Xilinx Student Edition 1.5 from Barnes & Nobles. What are
the limitiations of the tools that come with the book? What is the max
number of gates that I can use using these tools? And is there a FAQ on
FPGA? Now, this is my first look into FPGA, so I pretty much no nothing
about it. Thanks.
Ram
--
,,,,
/'^'\
( o o )
-oOOO--(_)--OOOo-------------------------------------
| Ram Meenakshisundaram
| Senior Software Engineer
| OpenLink Financial Inc
| .oooO Phone: (516) 227-6600 x267
| ( ) Oooo. Email: rmeenaks@olf.com
---\ (----( )--------------------------------------
\_) ) /
(_/
Article: 17555This is a multi-part message in MIME format. --------------19D933429AA2BDAB5936B2C9 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Also with logicore of scaled 1/2 accumulator 53%, 23.5MHz (whole design)! with VHDL text instead logicore 52% 23MHz! Summary: I should' t use logicore for basic components!!! --------------19D933429AA2BDAB5936B2C9 Content-Type: text/x-vcard; charset=us-ascii; name="fliser6.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Ilia Oussorov Content-Disposition: attachment; filename="fliser6.vcf" begin:vcard n:Oussorov;Ilia x-mozilla-html:TRUE org:Robert Bosch GmbH, FV/FLI adr:;;P.O.Box 10 60 50;Stuttgart;;D-70049;Germany version:2.1 email;internet:fliser6@fli.sh.bosch.de tel;fax:+49-(0)-711-8117602 tel;work:+49-(0)-711-8117057 x-mozilla-cpt:;0 fn:Ilia Oussorov end:vcard --------------19D933429AA2BDAB5936B2C9--Article: 17556
Hi,
What would it take to emulate say a T225 or T425 transputer on a FPGA
(without any external links). Since I am new at this, what would be an
ideal FPGA to do this. Can I accomplish this on a XC4003E?? How many
gates would I need on the FPGA to do this. Thanks.
Ram
--
,,,,
/'^'\
( o o )
-oOOO--(_)--OOOo-------------------------------------
| Ram Meenakshisundaram
| Senior Software Engineer
| OpenLink Financial Inc
| .oooO Phone: (516) 227-6600 x267
| ( ) Oooo. Email: rmeenaks@olf.com
---\ (----( )--------------------------------------
\_) ) /
(_/
Article: 17557We've got a client who is using transputers, but INMOS apparently lost the 'receipe', and they quit making some of them. Anyway, we looked at doing a reverse engineered version on an FPGA, and figured out that it would be a pretty big. Some of those also have hardware floating point processors, which are very big. It's possible to do, though. We never really came up with an estimate for gate count, but I'm sure it would never fit into an XC4003E. As a comparison, you can look at our SLC1655 8-bit RISC VHDL processor on FPGA at http://www.silicore.net. At 80% utilization, 1/2 K ROM and some RAM, that part fits on a lucent ORCA 2C15 part. That means that it would fit somewhere between a Xilinx XC4013 - XC4025. If you're interested in FPGA microprocessors, there's a good page listing a bunch of them at: http://www.io.com/~guccione/HW_list.html He's also got some FPGA sizes in there, too. -- Wade D. Peterson Silicore Corporation 3525 E. 27th St. No. 301, Minneapolis, MN USA 55406 TEL: (612) 722-3815, FAX: (612) 722-5841 URL: http://www.silicore.net/ E-MAIL: peter299@maroon.tc.umn.edu Ram Meenakshisundaram <rmeenaks@olf.com> wrote in message news:37B04CFB.DA77A8F0@olf.com... > Hi, > > What would it take to emulate say a T225 or T425 transputer on a FPGA > (without any external links). Since I am new at this, what would be an > ideal FPGA to do this. Can I accomplish this on a XC4003E?? How many > gates would I need on the FPGA to do this. Thanks. > > Ram > > -- > > ,,,, > /'^'\ > ( o o ) > -oOOO--(_)--OOOo------------------------------------- > | Ram Meenakshisundaram > | Senior Software Engineer > | OpenLink Financial Inc > | .oooO Phone: (516) 227-6600 x267 > | ( ) Oooo. Email: rmeenaks@olf.com > ---\ (----( )-------------------------------------- > \_) ) / > (_/ > > >Article: 17558
Ram Meenakshisundaram wrote in message <37B04CFB.DA77A8F0@olf.com>... >What would it take to emulate say a T225 or T425 transputer on a FPGA > (without any external links). Since I am new at this, what would be an >ideal FPGA to do this. Can I accomplish this on a XC4003E?? How many >gates would I need on the FPGA to do this. Thanks. I have thought on this before. (If you configure a big array of FPGAs as CPUs, you might as well have them talk to each other.) The answer: it depends. By "emulate" do you mean drop-in-replace? If so, I can't say, because I never studied the transputer instruction set architecture, and because it depends upon whether you are willing to handle divide, floating point, etc., in software. If you mean "build a new machine in the transputer *style*", with high integration of on-chip components and instruction set support for message sends and fast task switching, etc., then here's a few back-of-the-envelope estimates for you. I recall the inmos T414, 1985, which had a 32-bit processor, 2KB of on-chip RAM, 4 10? Mb/s links, and an integrated DRAM controller. A T414-20 had a 20 MHz clock and did about 10 million transputer instructions per second. (I think. I am not a transputer expert.) A pipelined 16-bit datapath for a two-cycled 32-bit RISC requires about 8x9=72 CLBs, and its control unit could be ~50 CLBs. A full 32-bit datapath adds another 72 CLBs. Consider the 2 KB of on-chip RAM. In an XC4000, each CLB can store 32 bits. 2KB * 8 b/B * 1 CLB/32 bits = 512 CLBs, or about half of an XC4025E. Or just 4 of the 512 B embedded RAM blocks on a Virtex part. I assume you were hoping to target an XC4000 so let's reduce our on-chip RAM requirements to 128 B (32 CLBs) and move on. An EDO DRAM controller w/ page mode support requires a 12-bit register and comparator, a 12-bit mux, and some state machine logic. Call it 20 CLBs. The four serial links (10 MHz is slow and easy) are each ~12-16 CLBs, although if you time multiplex them you may be able to make four links from one implementation plus a register file. Totals: CLBs What 72-144 CPU datapath 50 CPU control 32 128 B on-chip RAM 20 DRAM controller 20-64 4 serial links ---- 194-310 CLBs An expert might fit it in a 196 CLB XC4005E/XL, more likely you would require 1) an XC4008E or XC4010XL and 2) hand-mapping and floorplanning experience. (The XC4003E, with 10x10 CLBs, will probably prove too small. You could build a minimalist 16-bit wide datapath in about 4x9 CLBs and could build a CPU there, but you probably won't have room for links or memory controller.) If you are more interested in exactly implementing the transputer instruction set architecture, and IIRC it is a stack machine, then consider the example of the MSL16 microprocessor. See Leong, P.H.W, P.K. Tsang, and T.K. Lee, "A FPGA based Forth microprocessor", pp. 254-255, in Proc. IEEE Symp. on FPGAs for Custom Computing Machines 1998, and at http://www.cse.cuhk.edu.hk/~phwl/msl16/msl16.html, and Paul Lee Wai Lun's thesis and presentation, "FPGA Implementation of a Forth Processor", at http://home.hkstar.com/~wail/project-7260/project.htm. To implement a legacy ISA in an FPGA, I advise building a simplified implementation hidden behind a binary rewriting system! Jan Gray www3.sympatico.ca/jsgray/homebrew.htmArticle: 17559
If I recall correctly, someone either working with Ian Page at Oxford (the hardware compilation group), or the related spinoff Embedded Solutions, Ltd. had coded up a minimal integer ALU transputer core on an FPGA (using the occam/CSP-like Handel-C hardware design language, or a predecessor) a couple years ago. I think it was pretty low in gate count, possibly fitting an XC4003E, but it would certainly form only a very small portion of a full transputer, since timers, process scheduler, some floating point support, etc. are needed to form a "real" transputer of the T225 or T425 class. I would guess the need for at least a 10K+ gate FPGA to do the job (but others who read this group may offer more intelligent answers). Adding one or more links (after all, what is a transputer without them?) and the associated DMA engines would cause the hardware to grow significantly larger still, perhaps getting into the 50K gate region. Transputing without links would probably be done better using the KRoC or SPoC approaches on a current microprocessor. Jim --------------------------------------------- James Wolffe Sr Member Technical Staff Northrop Grumman Norden Systems Melville NY USA Ram Meenakshisundaram <rmeenaks@olf.com> wrote in message news:37B04CFB.DA77A8F0@olf.com... > Hi, > > What would it take to emulate say a T225 or T425 transputer on a FPGA > (without any external links). Since I am new at this, what would be an > ideal FPGA to do this. Can I accomplish this on a XC4003E?? How many > gates would I need on the FPGA to do this. Thanks. > > Ram > > -- > > ,,,, > /'^'\ > ( o o ) > -oOOO--(_)--OOOo------------------------------------- > | Ram Meenakshisundaram > | Senior Software Engineer > | OpenLink Financial Inc > | .oooO Phone: (516) 227-6600 x267 > | ( ) Oooo. Email: rmeenaks@olf.com > ---\ (----( )-------------------------------------- > \_) ) / > (_/ > > >Article: 17560
Hello,
My name is Asher an I am looking for some advice on how I can decrease
the amount of space that my VHDL code takes up on my FPGA (Altera
EPF10K20RC240-4). I here that using LPM or megafunctions is one way to
decrease the amount of space but I wanted to know exactly why and under
what conditions this was true.
According to Altera LPM (Library of Parameterized Modules) is a
technology-independent library of logic functions that are parameterized
to achieve scalability and adaptability. I wondered, however, if this
also meant that the code was efficient and compact for any FPGA or just
a select few that were compatible with LPM. I would really appreciate
any good comments or suggestions on this matter?
One other thing... Here is a page of code that I have written. I wanted
to know if anyone could spot anything that could be done more
efficiently. If you see something that doesn't look like it's the best
way to do it please offer a better technique.
Anyhow, to summarize this code was made for the HEDS-9100 G00 /
HEDS-5500 G02 optical encoder made by HP. SEE:
http://www.hp.com/HP-COMP/motion/heds9000.html The current accuracy of
this code/device is .72 degrees with 500 counts per revolution (CPR) on
the codewheel. The VHDL code posted below calculates the angle and
speed of rotation.
You comments and suggestions on optimization are appreciated...
Best regards,
>Asher<
<<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>
Asher C. Martin
805 West Oregon Street
Urbana, IL 61801-3825
(217) 367-3877
E-MAIL: martin2@acm.uiuc.edu
http://fermi.isdn.uiuc.edu
telnet://fermi.isdn.uiuc.edu
ftp://feynman.isdn.uiuc.edu
<<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>
-- //////////////////////////////////////////////////
-- // by Asher C. Martin //
-- // martin2@acm.uiuc.edu //
-- // http://fermi.isdn.uiuc.edu //
-- // Robotics and Computer Vision Laboratory //
-- // University of Illinois at Urbana-Champaign //
-- //////////////////////////////////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY angle IS
-- All input and outputs from the FPGA are defined below.
PORT
(
ain : IN STD_LOGIC; -- CHANNEL A FROM OPTICAL ENCODER
bin : IN STD_LOGIC; -- CHANNEL B FROM OPTICAL ENCODER
reset_switch : IN STD_LOGIC; -- IF ANGLE GETS OFFSET THEN RESET THIS
LINE
clock : IN STD_LOGIC; -- SYSTEM CLOCK
angle : OUT INTEGER RANGE 0 TO 500; -- Angle in Deg. = 360/500*angle
speed : OUT INTEGER RANGE 0 TO 127 := 0; -- Speed of rotation
moved : OUT STD_LOGIC; -- Moved goes high for each +.72 degree move
clockwise : OUT STD_LOGIC -- Clockwise (CW) is high for CW rotation
);
END angle;
ARCHITECTURE angle_architecture OF angle IS
SIGNAL angle_counter : INTEGER RANGE 0 to 500;
SIGNAL speed_counter : INTEGER RANGE 0 to 127 := 0;
SIGNAL clock_counter : INTEGER RANGE 0 to 1000000;
SIGNAL start : std_logic := '0';
SIGNAL aold : std_logic;
SIGNAL bold : std_logic;
SIGNAL dir : std_logic_vector(1 downto 0) := "00";
BEGIN
-- THE FOLLOWING CODE EVALUATES WHAT IS HAPPENING TO CHANNEL A
grab_data: PROCESS (clock)
begin
if (reset_switch = '0') then
angle_counter <= 0;
speed_counter <= 0;
elsif (clock'event and clock='1') then
clock_counter <= clock_counter + 1;
if (start = '1') then
if (clock_counter = 100000 and speed_counter > 0) then
speed_counter <= speed_counter - 1;
clock_counter <= 0;
end if;
else
speed_counter <= speed_counter;
end if;
dir <= (bin xor bold) & (ain xor aold);
aold <= ain;
bold <= bin;
case dir is
when "00" => --no change
moved <= '0'; --leave cw output alone
when "01" => -- clockwise rotation
start <= (start xor '1');
if (start = '1') then
speed_counter <= 127;
clock_counter <= 0;
end if;
if (ain = '1' and bin = '0') then
angle_counter <= angle_counter + 1;
moved <= '1';
clockwise <= '1';
end if;
when "10" => --ccw rotation
if (bin = '1' and ain = '0') then
angle_counter <= angle_counter - 1;
moved <= '1';
clockwise <= '0';
end if;
when others => -- this is an error condition...either a bad
sensor or rotation is faster than clock
end case;
end if;
--end if;
END PROCESS grab_data;
-- THE CURRENT ANGLE IS NOW LOCATED AT "ANGLE_OUTPUT"
angle <= angle_counter;
speed <= speed_counter;
END angle_architecture;
Article: 17561See http://www.xilinx.com/programs/xse1.htm for complete information on the Xilinx Student Edition Software. Ram Meenakshisundaram wrote: > Hi, > > I have a homebrew card that contains an inmos T425 transputer connected > to a Xilinx XC4000E-3 FPGA and a Motorola DSP56002 DSP processor. > I ordered the Xilinx Student Edition 1.5 from Barnes & Nobles. What are > the limitiations of the tools that come with the book? What is the max > number of gates that I can use using these tools? And is there a FAQ on > FPGA? Now, this is my first look into FPGA, so I pretty much no nothing > about it. Thanks. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Anna Acevedo Tel: USA 408-879-5338 Xilinx University Program Fax: USA 408-879-4442 2100 Logic Dr. email: anna.acevedo@xilinx.com San Jose, CA 95124 USA Hot Web Site: http://www.xilinx.com/programs/univ.htm * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *Article: 17562
In article <EbZr3.85$Q4.1543@paloalto-snr1.gtei.net>, Jan Gray <jsgray@acm.org.nospam> writes >Ram Meenakshisundaram wrote in message <37B04CFB.DA77A8F0@olf.com>... >>What would it take to emulate say a T225 or T425 transputer on a FPGA >> (without any external links). Since I am new at this, what would be an >>ideal FPGA to do this. Can I accomplish this on a XC4003E?? How many >>gates would I need on the FPGA to do this. Thanks. > >I have thought on this before. (If you configure a big array of FPGAs as >CPUs, you might as well have them talk to each other.) > >The answer: it depends. By "emulate" do you mean drop-in-replace? If so, I >can't say, because I never studied the transputer instruction set >architecture, and because it depends upon whether you are willing to handle >divide, floating point, etc., in software. My company talked to some FPGA specialists about this, and the conclusion was that it is probably possible, though I was not involved in the discussions and don't know the details. However, the cost/benefit didn't seem to justify it. However, if someone *were* to consider doing it, we might be interested in supporting it financially to a modest extent in case our Last Time Buy turns out insufficient. The spec is for a software compatible T425 clone, with roughly equivalent (or better) performance and a PCB footprint not *too* much larger. One of the problems of a commercial operation would, of course, be inmos patents; I looked through the abstracts, and I think some of them would be impossible to bypass in a transputer clone. >If you mean "build a new machine in the transputer *style*", with high >integration of on-chip components and instruction set support for message >sends and fast task switching, etc., then here's a few back-of-the-envelope >estimates for you. <Snip detailed CLB estimates> If you are not cloning the transputer exactly, then I think you would change several things. For example, I would only put on one link and use Brian O'Neill's C416 self-routing crosspoint or something similar (Brian is working on improved links, faster and with more functionality). I wouldn't put the on-chip ram in; I would rather interface to an external cache controller. The original transputer idea was, I think, that all data would fit into the on-chip ram, and sometimes the program as well. That has not turned out so - code and data have both grown faster than any conceivable on-chip ram. >To implement a legacy ISA in an FPGA, I advise building a simplified >implementation hidden behind a binary rewriting system! This is crucial if you are not building a binary-compatible clone: where are you going to get your software. Firstly, you need compilers for your favoured languages. Secondly, linking for a multiprocessor system is not, as inmos found, as simple as linking for a multiprocessor system. I would suggest that the ARM instruction set (intellectual property rights permitting) would be a good idea; IIRC the early ARM cpus were implemented in "about 32000 transistors" - what that would be in CLBs, I don't know. -- Alec CawleyArticle: 17563
James Wolffe wrote: > If I recall correctly, someone either working with Ian Page at Oxford (the > hardware compilation group), or the related spinoff Embedded Solutions, Ltd. > had coded up a minimal integer ALU transputer core on an FPGA (using the > occam/CSP-like Handel-C hardware design language, or a predecessor) a couple > years ago. I think it was pretty low in gate count, possibly fitting an > XC4003E, but it would certainly form only a very small portion of a full > transputer, since timers, process scheduler, some floating point support, > etc. are needed to form a "real" transputer of the T225 or T425 class. I > would guess the need for at least a 10K+ gate FPGA to do the job (but others > who read this group may offer more intelligent answers). > > Adding one or more links (after all, what is a transputer without them?) and > the associated DMA engines would cause the hardware to grow significantly > larger still, perhaps getting into the 50K gate region. Transputing without > links would probably be done better using the KRoC or SPoC approaches on a > current microprocessor. Gate counts are such a bad thing to use for comparisons of size... An integer-only transputer would probably fit into a Xilinx Virtex XCV400. It might fit into an XCV300, but certainly not a 200. The reason why I say this is that a 32x32 integer multiply that is fully pipelined takes about 150k "virtex gates". The rest of the transputer core is probably around 100k "virtex gates". Then there is the links and other peripheral logic... This is assuming that a transputer does a 32x32 multiply in an effective single cycle. If it takes longer then the multiply unit could be shaved down somewhat. Remember that a 400k gate Virtex is very roughly equivalent to a 100k gate XC4000. Plan on at least doubling the gate count if you want to do floating point. David Kessner davidk@free-ip.com http://www.free-ip.comArticle: 17564
Isn't the A5933 made obsolote by AMCC? Homann Le mer Michel <michel.lemer@ago.fr> writes: > Steven Derrien wrote: > > > Hi, > > > > I'm looking for advice, tips , or whatever information that would help > > me with this : We'd like to design a Virtex daughter (WWW.Xilinx.com/) > > board to plug on a s5933 matchmaker PCI prototype board > > (www.amcc.com/XXX/). the daughterboard would include > > > > - One SRAM Bank > > - A programmable clock > > - A power supply/Voltage regulator > > - A small XCV50 for the daughterboard control > > - An Atmel EEPROM for XCV50 configuration > > - A large Virtex device to implement custom designs > > > > The control FPGA would be initialised by an EEPROM on the board, and > > would allow the second FPGA configuration through SelectMap mode with > > configuration data coming from the PCI Bus. > > > > I'm wondering about the complexity of the PCB design for this board as > > relatively high clock frequency would be used (over 60 Mhz), and as > > different supply voltage are needed : Amcc prototype board can supply > > its daughterboard with 5v voltage, however Virtex chips require both > > 2.5v and 3.3v supply voltage. > > > > This would just be a prototype used for academic purpose, so we don't > > really care about EMC , PCI compliance or whatsoever, we just want it to > > work on a standard x86 PCI slot ... > > > > Can anyone gives me some tips or share experience on various problems I > > may encounter. Specificallly I'd like to have an estimation about the > > time required to design such a board : We would be four people involved > > in the design, half of them having PCD CAD tool experience (although not > > for such kind of boards). > > > > Thanks > > > > Steven > > Hello > > We are working on a similar project with the S5933 and 5 fpgas (2 virtex). > The duration of the project depends mainly of the custom part. > Our S5933 can only meet 33Mhz. Fully synchronous or asynchronous design? > From my point of view, two unrelated clocks is the most difficult point. > You should define if you want or not burst transfer, slave and master mode, > mailbox, interrupt, 1 up to 4 BAR .... > 3.3 V is not a problem as the I/O is 5V TTL compatible. > The 2.5V regulator should be able to supply enough current. > > Hope this helps, > > Michel Le Mer > Gerpi sa (Xilinx Xpert) > 3, rue du Bosphore > Alma city > 35000 Rennes (France) > (02 99 51 17 18) > http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi.htm > -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 17565
James Wolffe wrote:
> If I recall correctly, someone either working with Ian Page at Oxford (the
> hardware compilation group), or the related spinoff Embedded Solutions, Ltd.
> had coded up a minimal integer ALU transputer core on an FPGA (using the
> occam/CSP-like Handel-C hardware design language, or a predecessor) a couple
> years ago. I think it was pretty low in gate count, possibly fitting an
> XC4003E, but it would certainly form only a very small portion of a full
> transputer, since timers, process scheduler, some floating point support,
> etc. are needed to form a "real" transputer of the T225 or T425 class. I
> would guess the need for at least a 10K+ gate FPGA to do the job (but others
> who read this group may offer more intelligent answers).
I remember this. I downloaded it a while back when it was announced, but I
seem to have lost it. Does anyone have this? I believe it was called xputer.c
>
>
> Adding one or more links (after all, what is a transputer without them?) and
> the associated DMA engines would cause the hardware to grow significantly
> larger still, perhaps getting into the 50K gate region. Transputing without
> links would probably be done better using the KRoC or SPoC approaches on a
> current microprocessor.
Yes, links would be nice, but I wanted to do it as a proof of concept. Once
I can get a single transputer chip emulated in FPGA, it would be a starting
point into the much larger link-based FPGA Xputer. How would speed affect
this? Would it be faster or slower than the T425?? What kind of performance
can I expect from something like this??
Ram
--
,,,,
/'^'\
( o o )
-oOOO--(_)--OOOo-------------------------------------
| Ram Meenakshisundaram
| Senior Software Engineer
| OpenLink Financial Inc
| .oooO Phone: (516) 227-6600 x267
| ( ) Oooo. Email: rmeenaks@olf.com
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Article: 17566In article <37B07DC8.6EDC8F4D@free-ip.com>, David Kessner <davidk@free- ip.com> writes >This is assuming that a transputer does a 32x32 multiply in an effective >single cycle. Would that it did. A T425 does a shift and add until one of the operands goes to zero. -- Alec CawleyArticle: 17567
One way is to use a good FPGA synthesis tool. The VHDL reader in Altera is not a very "good" synthesis tool and usually ends up producing large slow designs. Synopsys Design Compiler is not a good FPGA synthesis tool either and again tends to produces large slow designs. Try using Synopsys FPGA Express or Synplicity Synplify. I have used both. We own FPGA Express. It tends to produce smaller faster designs than Design Compiler (our ASIC synthesis tool). Other than that, you can use a larger part. The larger the part, the more efficient place and route you get (sometimes). You are concerned about area. Area and speed usually trade off (larger area = higher speed than small area). Good Luck, PJ In article <37B06647.1DD4F4DE@acm.uiuc.edu>, "Asher C. Martin" <martin2@acm.uiuc.edu> wrote: > Hello, > > My name is Asher an I am looking for some advice on how I can decrease > the amount of space that my VHDL code takes up on my FPGA (Altera > EPF10K20RC240-4). I here that using LPM or megafunctions is one way to > decrease the amount of space but I wanted to know exactly why and under > what conditions this was true. > > According to Altera LPM (Library of Parameterized Modules) is a > technology-independent library of logic functions that are parameterized > to achieve scalability and adaptability. I wondered, however, if this > also meant that the code was efficient and compact for any FPGA or just > a select few that were compatible with LPM. I would really appreciate > any good comments or suggestions on this matter? > > One other thing... Here is a page of code that I have written. I wanted > to know if anyone could spot anything that could be done more > efficiently. If you see something that doesn't look like it's the best > way to do it please offer a better technique. > > Anyhow, to summarize this code was made for the HEDS-9100 G00 / > HEDS-5500 G02 optical encoder made by HP. SEE: > http://www.hp.com/HP-COMP/motion/heds9000.html The current accuracy of > this code/device is .72 degrees with 500 counts per revolution (CPR) on > the codewheel. The VHDL code posted below calculates the angle and > speed of rotation. > > You comments and suggestions on optimization are appreciated... > > Best regards, > > >Asher< > > <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>> > Asher C. Martin > 805 West Oregon Street > Urbana, IL 61801-3825 > (217) 367-3877 > E-MAIL: martin2@acm.uiuc.edu > http://fermi.isdn.uiuc.edu > telnet://fermi.isdn.uiuc.edu > ftp://feynman.isdn.uiuc.edu > <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>> > > -- ////////////////////////////////////////////////// > -- // by Asher C. Martin // > -- // martin2@acm.uiuc.edu // > -- // http://fermi.isdn.uiuc.edu // > -- // Robotics and Computer Vision Laboratory // > -- // University of Illinois at Urbana-Champaign // > -- ////////////////////////////////////////////////// > > LIBRARY ieee; > USE ieee.std_logic_1164.all; > USE ieee.std_logic_arith.all; > > ENTITY angle IS > > -- All input and outputs from the FPGA are defined below. > PORT > ( > ain : IN STD_LOGIC; -- CHANNEL A FROM OPTICAL ENCODER > bin : IN STD_LOGIC; -- CHANNEL B FROM OPTICAL ENCODER > reset_switch : IN STD_LOGIC; -- IF ANGLE GETS OFFSET THEN RESET THIS > LINE > clock : IN STD_LOGIC; -- SYSTEM CLOCK > angle : OUT INTEGER RANGE 0 TO 500; -- Angle in Deg. = 360/500*angle > speed : OUT INTEGER RANGE 0 TO 127 := 0; -- Speed of rotation > moved : OUT STD_LOGIC; -- Moved goes high for each +.72 degree move > clockwise : OUT STD_LOGIC -- Clockwise (CW) is high for CW rotation > ); > END angle; > > ARCHITECTURE angle_architecture OF angle IS > SIGNAL angle_counter : INTEGER RANGE 0 to 500; > SIGNAL speed_counter : INTEGER RANGE 0 to 127 := 0; > SIGNAL clock_counter : INTEGER RANGE 0 to 1000000; > SIGNAL start : std_logic := '0'; > SIGNAL aold : std_logic; > SIGNAL bold : std_logic; > SIGNAL dir : std_logic_vector(1 downto 0) := "00"; > BEGIN > > -- THE FOLLOWING CODE EVALUATES WHAT IS HAPPENING TO CHANNEL A > grab_data: PROCESS (clock) > begin > if (reset_switch = '0') then > angle_counter <= 0; > speed_counter <= 0; > elsif (clock'event and clock='1') then > clock_counter <= clock_counter + 1; > if (start = '1') then > if (clock_counter = 100000 and speed_counter > 0) then > speed_counter <= speed_counter - 1; > clock_counter <= 0; > end if; > else > speed_counter <= speed_counter; > end if; > dir <= (bin xor bold) & (ain xor aold); > aold <= ain; > bold <= bin; > case dir is > when "00" => --no change > moved <= '0'; --leave cw output alone > when "01" => -- clockwise rotation > start <= (start xor '1'); > if (start = '1') then > speed_counter <= 127; > clock_counter <= 0; > end if; > if (ain = '1' and bin = '0') then > angle_counter <= angle_counter + 1; > moved <= '1'; > clockwise <= '1'; > end if; > when "10" => --ccw rotation > if (bin = '1' and ain = '0') then > angle_counter <= angle_counter - 1; > moved <= '1'; > clockwise <= '0'; > end if; > when others => -- this is an error condition...either a bad > sensor or rotation is faster than clock > end case; > end if; > --end if; > END PROCESS grab_data; > > -- THE CURRENT ANGLE IS NOW LOCATED AT "ANGLE_OUTPUT" > angle <= angle_counter; > speed <= speed_counter; > > END angle_architecture; > Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17568
As a note, Synopsys DC is not an FPGA synthesis tool - that's why they have
FPGA Compiler for FPGAs.
Adam
phil_jackson@my-deja.com wrote:
> One way is to use a good FPGA synthesis tool. The VHDL reader in Altera
> is not a very "good" synthesis tool and usually ends up producing large
> slow designs. Synopsys Design Compiler is not a good FPGA synthesis tool
> either and again tends to produces large slow designs. Try using
> Synopsys FPGA Express or Synplicity Synplify. I have used both. We own
> FPGA Express. It tends to produce smaller faster designs than Design
> Compiler (our ASIC synthesis tool). Other than that, you can use a
> larger part. The larger the part, the more efficient place and route you
> get (sometimes). You are concerned about area. Area and speed usually
> trade off (larger area = higher speed than small area).
>
> Good Luck,
> PJ
>
> In article <37B06647.1DD4F4DE@acm.uiuc.edu>,
> "Asher C. Martin" <martin2@acm.uiuc.edu> wrote:
> > Hello,
> >
> > My name is Asher an I am looking for some advice on how I can decrease
> > the amount of space that my VHDL code takes up on my FPGA (Altera
> > EPF10K20RC240-4). I here that using LPM or megafunctions is one way
> to
> > decrease the amount of space but I wanted to know exactly why and
> under
> > what conditions this was true.
> >
> > According to Altera LPM (Library of Parameterized Modules) is a
> > technology-independent library of logic functions that are
> parameterized
> > to achieve scalability and adaptability. I wondered, however, if this
> > also meant that the code was efficient and compact for any FPGA or
> just
> > a select few that were compatible with LPM. I would really appreciate
> > any good comments or suggestions on this matter?
> >
> > One other thing... Here is a page of code that I have written. I
> wanted
> > to know if anyone could spot anything that could be done more
> > efficiently. If you see something that doesn't look like it's the
> best
> > way to do it please offer a better technique.
> >
> > Anyhow, to summarize this code was made for the HEDS-9100 G00 /
> > HEDS-5500 G02 optical encoder made by HP. SEE:
> > http://www.hp.com/HP-COMP/motion/heds9000.html The current accuracy of
> > this code/device is .72 degrees with 500 counts per revolution (CPR)
> on
> > the codewheel. The VHDL code posted below calculates the angle and
> > speed of rotation.
> >
> > You comments and suggestions on optimization are appreciated...
> >
> > Best regards,
> >
> > >Asher<
> >
> > <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>
> > Asher C. Martin
> > 805 West Oregon Street
> > Urbana, IL 61801-3825
> > (217) 367-3877
> > E-MAIL: martin2@acm.uiuc.edu
> > http://fermi.isdn.uiuc.edu
> > telnet://fermi.isdn.uiuc.edu
> > ftp://feynman.isdn.uiuc.edu
> > <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>
> >
> > -- //////////////////////////////////////////////////
> > -- // by Asher C. Martin //
> > -- // martin2@acm.uiuc.edu //
> > -- // http://fermi.isdn.uiuc.edu //
> > -- // Robotics and Computer Vision Laboratory //
> > -- // University of Illinois at Urbana-Champaign //
> > -- //////////////////////////////////////////////////
> >
> > LIBRARY ieee;
> > USE ieee.std_logic_1164.all;
> > USE ieee.std_logic_arith.all;
> >
> > ENTITY angle IS
> >
> > -- All input and outputs from the FPGA are defined below.
> > PORT
> > (
> > ain : IN STD_LOGIC; -- CHANNEL A FROM OPTICAL ENCODER
> > bin : IN STD_LOGIC; -- CHANNEL B FROM OPTICAL ENCODER
> > reset_switch : IN STD_LOGIC; -- IF ANGLE GETS OFFSET THEN RESET
> THIS
> > LINE
> > clock : IN STD_LOGIC; -- SYSTEM CLOCK
> > angle : OUT INTEGER RANGE 0 TO 500; -- Angle in Deg. = 360/500*angle
> > speed : OUT INTEGER RANGE 0 TO 127 := 0; -- Speed of rotation
> > moved : OUT STD_LOGIC; -- Moved goes high for each +.72 degree move
> > clockwise : OUT STD_LOGIC -- Clockwise (CW) is high for CW
> rotation
> > );
> > END angle;
> >
> > ARCHITECTURE angle_architecture OF angle IS
> > SIGNAL angle_counter : INTEGER RANGE 0 to 500;
> > SIGNAL speed_counter : INTEGER RANGE 0 to 127 := 0;
> > SIGNAL clock_counter : INTEGER RANGE 0 to 1000000;
> > SIGNAL start : std_logic := '0';
> > SIGNAL aold : std_logic;
> > SIGNAL bold : std_logic;
> > SIGNAL dir : std_logic_vector(1
> downto 0) := "00";
> > BEGIN
> >
> > -- THE FOLLOWING CODE EVALUATES WHAT IS HAPPENING TO CHANNEL A
> > grab_data: PROCESS (clock)
> > begin
> > if (reset_switch = '0') then
> > angle_counter <= 0;
> > speed_counter <= 0;
> > elsif (clock'event and clock='1') then
> > clock_counter <= clock_counter + 1;
> > if (start = '1') then
> > if (clock_counter = 100000 and speed_counter > 0) then
> > speed_counter <= speed_counter - 1;
> > clock_counter <= 0;
> > end if;
> > else
> > speed_counter <= speed_counter;
> > end if;
> > dir <= (bin xor bold) & (ain xor aold);
> > aold <= ain;
> > bold <= bin;
> > case dir is
> > when "00" => --no change
> > moved <= '0'; --leave cw output alone
> > when "01" => -- clockwise rotation
> > start <= (start xor '1');
> > if (start = '1') then
> > speed_counter <= 127;
> > clock_counter <= 0;
> > end if;
> > if (ain = '1' and bin = '0') then
> > angle_counter <= angle_counter + 1;
> > moved <= '1';
> > clockwise <= '1';
> > end if;
> > when "10" => --ccw rotation
> > if (bin = '1' and ain = '0') then
> > angle_counter <= angle_counter - 1;
> > moved <= '1';
> > clockwise <= '0';
> > end if;
> > when others => -- this is an error condition...either a
> bad
> > sensor or rotation is faster than clock
> > end case;
> > end if;
> > --end if;
> > END PROCESS grab_data;
> >
> > -- THE CURRENT ANGLE IS NOW LOCATED AT "ANGLE_OUTPUT"
> > angle <= angle_counter;
> > speed <= speed_counter;
> >
> > END angle_architecture;
> >
>
> Sent via Deja.com http://www.deja.com/
> Share what you know. Learn what you don't.
--
"Sometimes I think the surest sign that there's intelligent life on
other planets is that none of it has tried to contact us."
- Calvin, "Calvin and Hobbes"
Article: 17569
phil_jackson@my-deja.com wrote:
>
> One way is to use a good FPGA synthesis tool. The VHDL reader in Altera
> is not a very "good" synthesis tool and usually ends up producing large
> slow designs. Synopsys Design Compiler is not a good FPGA synthesis tool
> either and again tends to produces large slow designs. Try using
> Synopsys FPGA Express or Synplicity Synplify.
Also might try Leonardo Spectrum.
http://www.synplicity.com/
http://www.exemplar.com/index.html
http://www.synopsys.com/products/fpga/fpga_express.html
Any of these three tools will produce better results than the default
VHDL complier in Max Plus Two. I have used all three.
As for Asher's code, I notice one thing that might reduce design size.
SIGNAL clock_counter : INTEGER RANGE 0 to 1000000;
I don't think that clock_counter can ever get larger than 100000. The
SIGNAL declaration may require a larger register (and larger
incrementers and comparators). I doubt (but have NOT tried) that any
tool is smart enough to notice this.
So I'd suggest you try changing clock_counter to a smaller range,
perhaps 0 to 131071?
--
Phil Hays
"Irritatingly, science claims to set limits on what
we can do, even in principle." Carl Sagan
Article: 17570CLBs are a much more accurate way of describing how much logic is used in an FPGA design. A maximum performance 32x32 integer multiplier can be done in about 260 Virtex clbs. That's about 2/3rds of an XCV50, the smallest Virtex part. Based on the nominal 50k gate size of that part, the full blown 32x32 multiplier is roughly 33k marketing gates (or less than 1/4 the size you projected). If you back off on the performance, a 16x16 multiplier, an accumulator and a little bit of logic will give you a 32x32 multiplier with better than 30MHz data rates in under 80 clbs. You need to design to the architecture (in this case using partial products) to get an efficient design in an FPGA. If you just copy a multiplier designed for an ASIC, you are likely to get dismal results in terms of both performance and area. David Kessner wrote: > Gate counts are such a bad thing to use for comparisons of size... > > An integer-only transputer would probably fit into a Xilinx Virtex XCV400. > It might fit into an XCV300, but certainly not a 200. The reason why I > say this is that a 32x32 integer multiply that is fully pipelined takes about > 150k "virtex gates". The rest of the transputer core is probably around > 100k "virtex gates". Then there is the links and other peripheral logic... > > This is assuming that a transputer does a 32x32 multiply in an effective > single cycle. If it takes longer then the multiply unit could be shaved down > somewhat. > > Remember that a 400k gate Virtex is very roughly equivalent to a > 100k gate XC4000. > > Plan on at least doubling the gate count if you want to do floating > point. > > David Kessner > davidk@free-ip.com > http://www.free-ip.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17571
Greetings, Thanks for the advice... would anyone happen to know if LPM functions are necessary to reduce the amount of space that VHDL takes up on an FPGA? Best regards, >Asher< <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>> Asher C. Martin 805 West Oregon Street Urbana, IL 61801-3825 (217) 367-3877 E-MAIL: martin2@acm.uiuc.edu http://fermi.isdn.uiuc.edu telnet://fermi.isdn.uiuc.edu ftp://feynman.isdn.uiuc.edu <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>Article: 17572
hello, i'm looking for a PCI core in the form of VHDL or Verilog source code that is surely synthesizable and provides all kinds of stuffs neeeded to develop an ASIC with PCI interface. Please, somebody tell me who sells this kind of reliable PCI core, or where I should find information on it.Article: 17573
Hello, I'm a french teacher and I'm trying to design an application on the XS40 board composed by a software part in java and an hardware part with a FPGA. This application will be an example of codesign for the lessons I will teach to my students. I have looking to the Docs, faqs and news and I found nothing about communicating datas between Java and XS40 board. The problem I'm trying to solve are the following ones. To begin my application, I have implemented on the FPGA the example which displays on Leds of the board, a number transfered from the PC. This example works fine with the xsport command. But if I try to do the same thing using Java, here are the problems - When I start my Java application which opens a communication with the parallel port using java.comm classes, some datas are automaticaly sent to the board, and the number 3 is displayed on the Leds. - When I try to send a number from Java to the board, the number is never displayed on Leds. - I don't find java class which allow to read the parallel port. It seems that Java.comm parallel classes only allow to write on the parallel port (and not to read). Have anybody some solutions to solve my problems, and some examples in Java for sending and recieving datas with the XS40 board ? Thank you very much for your help. /--------------------------------------+---+----\ / \ | \ | Laurent FREUND \o| | | freund@ismea.grp-esim.imt-mrs.fr \ | | Groupe ESIM, Laboratoire EII \ | | Technopole de Chateau-Gombert u+---/| | 13451 Marseille Cedex 20 France | | | Tel: 04 91 05 44 24 | | | Fax: 04 91 05 45 69 \ | \ http://pc-freund.grp-esim.imt-mrs.fr / \------------------------------------------------/Article: 17574
Alec Cawley <alec@cawley.demon.co.uk> writes: > The original transputer idea was, I think, that all > data would fit into the on-chip ram, and sometimes the program as well. There are machines where this is the case - I think DRA Malvern built a radar deconvolver based on ~400 T2s that had no external memory. It all fit into a 19 inch enclosure less than 10cm high. But main advantage of the on-chip memory in the pre-T9 transputers was that the processes workspace would live there. Together with the local scoping of occam, which the compiler made good use of, scalar variables could be accessed very quickly. The equivalent C program usually was a factor of about two slower just because of this. In some cases, I also moved (small) work arrays on-chip to good advantage. Jan
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