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In article <fliptronE4xsAM.1Lw@netcom.com>, fliptron@netcom.com says... > In article <32f51952.49206535@news.alt.net> zx80@dgiserve.com (Peter) writes: > > > >Perhaps this whole business illustrates how some FPGA vendors are > >dependent on someone else's silicon foundry. > > > >We all know that many/most FPGAs (including Xilinx) are made by Sharp, > >Seiko/Epson, etc but I am sure few people realised that if one of > >these foundries decide to drop something, you can say bye bye to your > >FPGAs. > > > >Somehow I cannot believe that Xilinx in particular would rely on such > >an arrangement, however. > >Peter. > > Xilinx AND Altera normally are not as exposed as this little episode has > demonstrated, because they run their products in multiple fabs with > multiple foundary partners. What this episode demonstrates is the problem > of using non mainstream process technology. I would guess that the > situation is far worse for AntiFuse FPGA vendors, since the technology is > far from mainstream, and it is unlikely that multiple foundaries can be > supported with the process modifications needed to support the fuses, and > that the independent fabs will run it the same way. > > Philip Freidin Philip makes a good point. Any Lattice PLD customers out there? <g> [i.e. interesting non-mainstream process requirements, no captive fab] On another hand, if one looks to a PLD/FPGA vendor with a *captive* (i.e. internal) fab, what happens when their fab line catches a virus and they can't produce the goods? You can't [be guaranteed to] win, there is no perfect *and* economical scenario. There are umpteen different ways to screw up, and umpteen different ways to reduce exposure/risk. But (unless you are Maxim!) there are relatively few opportunities to excite customers with boring and unadventurous processes. **************************************************************** Bob Elkind mailto:eteam@aracnet.com 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ****** Video processing, R&D, ASIC, FPGA design consulting *****Article: 5251
In article <32F30BB7.625C@bc.sympatico.ca>, Tom_Burgess@bc.sympatico.ca says... > Ilan Ron wrote: > About a year ago after experiencing burned fingers from a maxed out > (2.5W@32 MHz) 30,000 gate 4013 design,(well, lots of busy RAM) I > suggested to Xilinx that it would be real easy to build a utility that > would give approximate energy per netlist node transition info (in > picojoules) from the xnf netlist and speed file and an added "power" (R, > C, V) file? > > Xdelay could do this (I claim). From this, one could manually estimate > the power from the node transition frequencies. Or wait a year or more > for the affordable simulation people to realize that power dissipation is > a hot feature and provide hooks to get power info, if it was available in > some standard form. I also pointed out that the need will get worse with > higher speed, density, utilization etc. So far, no sign of progress, but > ultimately customer pressure will prevail. > > I don't think that leaving it totally up to the customer to go through > the guts of the design and figure out the buffers, shortlines, longlines > etc. and relate them back to the netlist and the expected stimulus will > cut it anymore. I mean, WHO can DO this? It will be TOO easy to make a > dense, fast design that just burns too much power. If you don't have the > data, you are stumbling in the dark. <chomp> > regards, tom burgess Right on, Tom. This has been requested on numerous occasions, going back as far as 1992, to my knowledge. Even a crude tool that counts the number of active FFs driven by each clock node, and plops the right numbers into a .XLS format spreadsheet file, would give most customers 80% of the information they're looking for! Several times over the years, various folks from Xilinx have acknowledged that the idea merited development, and that the effort/expense could be modest. But nothing has ever come out of the idea that Tom and others have proposed. Anyone out there feel up to writing an awk script for hacking .LCA or .XNF files? -- Bob **************************************************************** Bob Elkind mailto:eteam@aracnet.com 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ****** Video processing, R&D, ASIC, FPGA design consulting *****Article: 5252
Philip Freidin wrote: > < snip > > > Xilinx AND Altera normally are not as exposed as this little episode has > demonstrated, because they run their products in multiple fabs with > multiple foundary partners. What this episode demonstrates is the problem > of using non mainstream process technology. I would guess that the > situation is far worse for AntiFuse FPGA vendors, since the technology is > far from mainstream, and it is unlikely that multiple foundaries can be > supported with the process modifications needed to support the fuses, and > that the independent fabs will run it the same way. > > Philip Freidin I would disagree. I've been using Actel/anti-fuse parts for years and for the act 1 and act 2 parts, they've always had multiple foundries: Texas Instruments and Matsushita Electric Company. More recently, I've seen the Act 3 parts from both Matsushita and Winbond. Also, Lockheed-Martin (formerly Loral (formerly IBM)) makes Act 2 1280's and will be coming out with Act 1 1020's. Parts also come from, for Act 2 devices, from Winbond and Chartered, in the 1200XL, which is a code compatible upgrade of the 1200 family. Since compatible parts come from some many foundries, it's actually hard keeping track of where individual parts are made! rkArticle: 5253
Scott McIntosh wrote: > > Hello, > I'm using a Xilinx 4013E PG223 chip and currently the rest > of the hardware is to be mounted with wire wrap sockets. Problem > so far is I'm unable to find an 18x18,223 wire wrap socket. Are > these just not available? Any other suggestions? > > Thanks, > Scott McIntosh > gtd750a@prism.gatech.edu Try the Mill-Max company. They are EXCELLENT people with a very good technical staff.Article: 5254
Ed Vogel wrote: > > I am considering the design of a dynamically reconfigurable logic > platform. It is more in line with tinkering than a serious product > application. Has anyone else tried to build an in circuit programmable > interface inside an FPGA or CPLD? > > Look at the XC6200 series (Xilinx) it is designed for dynamic reconfiguration and the routing bitstream is given.Article: 5255
In article <y4ybdbfu4d.fsf@mailhost.neuroinformatik.ruhr-uni-bochum.de>, Jan Vorbrueggen <jan@mailhost.neuroinformatik.ruhr-uni-bochum.de> wrote: >The most elaborate scheme I know of is in the Airbus A320. Every major >functional block is implemented at least three times using different software >by teams not allowed to talk to each other... >The only common mode failure I can think of are errors in the function and >integral tables the teams use to write their software... Unfortunately, "not allowed to talk to each other" is not strong enough. Some simple experiments demonstrated years ago that programming teams tend to arrive at similar solutions -- with similar bugs -- when they are all given the same problem. The only way to get truly different code is to have active coordination which makes *sure* that different teams are using different approaches. For example, as I recall, the shuttle's main flight software uses a fairly sophisticated preemptive timeslicing system, while the backup system uses a rigid system of "commutator multiplexing": fixed timeslices and tasks that are carefully broken up into pieces that fit within the slices. For another example, one display system for commercial airliners had two computers. One did the main job, taking the basic data (airspeed, altitude, etc.) and generating a display from it. The other looked at the display and worked backward from it to derive the presumed input data, sounding the alarm if it disagreed with the real data significantly. This was a particularly slick example because the second system wouldn't even be using the same (say) trig functions, but rather the inverses of them. -- "We don't care. We don't have to. You'll buy | Henry Spencer whatever we ship, so why bother? We're Microsoft."| henry@zoo.toronto.eduArticle: 5256
Aage Farstad wrote: > > Hi all, > > Can anybody give me a hint of what's wrong with my newsreader? Every > time I try to open a message from this guy, my newsreader (netscape3.0) > says: No Such article, Perhaps the article has expired! He is the only > one treated this way! > > Best Regards Aage Farstad > > aage.farstad@ffi.no Mine too, Seems Mr Knapp has the ULTIMATE in security - WRITE ONLY MEMORY :-)Article: 5257
Julio Cezar David de Melo <demelo@cpdee.ufmg.br> wrote: >Well, I am currently working exactly on the PCI dev kit, and I aggree >with you about its many bugs. It helped me a little with understanding >the basic behaviour of the PCI bus, but is some miles away from >following the PCI specification. I looked at it, decided it was a waste of time from the start, and am going ahead with my own bus interface. Besides, my PCI glue logic connects to five other busses, so it's really more of a router than a bus driver anyway. Altera's stuff didn't really seem flexible enough to handle something like this. ToddArticle: 5258
Dear sir, Does anyone have an experience with XACT and Orcad interface? I translate and verify my design until I get VST and AST files. I want to simulate my design in Orcad Simulation tools. The XACT manual tells me that I have to convert AST to STM file. That is I have to convert an ASCII file to a binary file for the ORCAD simulation editor. I call ASCTOVST program for the conversion but when I run the ASCTOVST commmand it says " Could not open file controll.ast Type any key to continue Command 'asctovst.exe controll.ast' failed, rc=-125 Press any key to continue." I don't know why the ASCTOVST cannot read my controll.ast file. I send an email to Xilinx Company but they say it is the problem with the ORCAD program. If anybody knows the reason, please inform me. I got stuck at this point for about 2 weeks. I will be appreciated for your help. Best regard Orachat Sukmarg Email : orachat@asu.eduArticle: 5259
Henry Spencer <henry@zoo.toronto.edu> wrote: > In article <y4ybdbfu4d.fsf@mailhost.neuroinformatik.ruhr-uni-bochum.de>, > Jan Vorbrueggen <jan@mailhost.neuroinformatik.ruhr-uni-bochum.de> wrote: > >The most elaborate scheme I know of is in the Airbus A320. Every major > >functional block is implemented at least three times using different software > >by teams not allowed to talk to each other... > >The only common mode failure I can think of are errors in the function and > >integral tables the teams use to write their software... > Unfortunately, "not allowed to talk to each other" is not strong enough. > Some simple experiments demonstrated years ago that programming teams tend > to arrive at similar solutions -- with similar bugs -- when they are all > given the same problem. The only way to get truly different code is to > have active coordination which makes *sure* that different teams are using > different approaches. A real-life example of this is the Ping-of-Death bug which allowed you to crash a networked machine with a single ping command. This appeared in many systems, some of which (eg. Linux) didn't share any code at all with the BSD reference implementations. -- It's not so much an afterlife, more a sort of apres-vie. --DNA -- Erik Corry erik@arbat.com http://inet.uni-c.dk/~ehcorry/ +45 86166287Article: 5260
Tom Burgess wrote: > About a year ago after experiencing burned fingers from a maxed out > (2.5W@32 MHz) 30,000 gate 4013 design,(well, lots of busy RAM) I > suggested to Xilinx that it would be real easy to build a utility that > would give approximate energy per netlist node transition info (in > picojoules) from the xnf netlist and speed file and an added "power" (R, > C, V) file? > > Xdelay could do this (I claim). ..... Great idea! I agree that we are quickly approaching a power limited situation with current FPGAs. With high density, clock rates and pin count these FPGAs can blow 5+ watts. As such, power is becoming a critical parameter. I don't think anyone can really do this well manualy. Your utility could make some assumptions regarding the correlation between signals and print out estimated power at say 10%, 30% and 100 toggle rates. Maybe the user could actually associate the correlations with named nets, as well as clock rate and I/O loading. Theis reminds me of a few other things I'd like to get out the report generator: 1- Signals names PPR was having a difficult time placing, routing or meeting timing. 2- The gate count of an equivalent ASIC. 3- Tristate bus contention warnings 4- Ground bounce warnings - BradArticle: 5261
In article <5d345c$8al@news.asu.edu>, orachat@imap2.asu.edu says... <skipped stuff> > I send an email to Xilinx Company but they say it is the problem > with the ORCAD program. > > If anybody knows the reason, please inform me. I got stuck at this > point for about 2 weeks. I will be appreciated for your help. > > Best regard > Orachat Sukmarg > Email : orachat@asu.edu OrCad is an authorized Xilinx "partner". In this capacity, all questions relating to the various OrCad interfaces to the various Xilinx backend products are handled directly and exclusively by OrCad. In the two or three instances in which I've wanted support, I've found at least one person or another at OrCad who is extremely knowledgeable with respect to the subtleties of supporting Xilinx designers. The OrCad website has lot of information, including FAQs, online [ http://www.orcad.com ]. Tech support is available by phone and email. For email tech support contact, see http://www.orcad.com/cgi-win/techsupp.exe Hope this helps, Bob Elkind **************************************************************** Bob Elkind mailto:eteam@aracnet.com 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ****** Video processing, R&D, ASIC, FPGA design consulting *****Article: 5262
This is another test to debug a problem sending news via Internet Explorer for readers using Netscape 3.0. All others please disregard. -- Steven Knapp E-mail: optmagic@ix.netcom.com Programmable Logic Jump Station: http://www.netcom.com/~optmagicArticle: 5263
> > Steve Schossow wrote: > > > > I've been using the Altera FPGAs for 6 months or so and one of the first > > things that bugged me was the cost of the BitBlaster. $200 for a little > > box (with an Altera FPGA in it no less) just to download the parts. > > > > So I dabble in programming and wrote a short program to wiggle a couple > > of bits on the printer port to download my 81188 and 10K50 parts. > > > > It works great and is at least as fast as the BitBlaster. It reads the > > design's .ttf file created when you do place and route. > > > > Any interest? I'll e-mail or post depending on how many responses I > > get. > Or you could use Atmel's AT17C series in system programmable serial EEPROM FPGA configuration memories, which work with *all* SRAM FPGAs. For more information or to request a FREE sample pay a visit to http://www.atmel.com/atmel/products/products22.html Martin.Article: 5264
Henry Spencer <henry@zoo.toronto.edu> writes: > Unfortunately, "not allowed to talk to each other" is not strong enough. > Some simple experiments demonstrated years ago that programming teams tend > to arrive at similar solutions -- with similar bugs -- when they are all > given the same problem. The only way to get truly different code is to > have active coordination which makes *sure* that different teams are using > different approaches. Yes, of course "common thinking" (aka as being in the same tur) is another possible failure mode. I think Airbus' approach is directed mainly at reducing reliance on the correctness of the basic tools (development environments, compilers, silicon, board layout). But I'm also inclined to think that if, for instance, you make the languages used for the different implementations different enough (e.g., C and Lisp 8-)), then the approaches used by the implementors - even if the top-level algorithms are basically the same (which they must be - they're implementing the same design!) - will be different enough to catch some (most?) of those "common thinking" errors. > For another example, one display system for commercial airliners had two > computers. One did the main job, taking the basic data (airspeed, > altitude, etc.) and generating a display from it. The other looked at the > display and worked backward from it to derive the presumed input data, > sounding the alarm if it disagreed with the real data significantly. This > was a particularly slick example because the second system wouldn't even > be using the same (say) trig functions, but rather the inverses of them. Slick indeed. Actually, I think this a basic idea not taught (and used) enough: trying to think of ways/test cases that will allow one to validate software. Another good example are (physical) perservation laws in simulations. JanArticle: 5265
I'm trying to decide if it is worth buying Xilinx Foundation BASE as oppose to the standard XACT Step package (because its much cheaper). Can anyone tell me if it is any good, what are its limitations - I've looked on Xilinx home page and can't find a good description of what it can or can't do! Thanks Peter.Article: 5266
In article: <32f0a065.6625677@news.alt.net> zx80@dgiserve.com (Peter) writes: > > Orcad with Xilinx library and Xact > Interesting. Was this SDT/386? And how did you manage with simulation? > VST? > has a good simulator. My experience of VST was very bad. > Sorry - off topic :) it may be off topic but i'm just starting (late) to try VST. any hints as to the expected problems. (using SDT386 1.2, Xact 5.2/6.0 and latest?? VST) if its long/interesting/detailed is it worth a new thread??? TIA -- steve goodwinArticle: 5267
>In article <32F2441F.3A7E@prism.gatech.edu>, Scott McIntosh <gtd750a@prism.gatech.edu> writes...
>>Hello,
>> I'm using a Xilinx 4013E PG223 chip and currently the rest
>>of the hardware is to be mounted with wire wrap sockets. Problem
>>so far is I'm unable to find an 18x18,223 wire wrap socket. Are
>>these just not available? Any other suggestions?
>
I have had similar problems. (i've since bypassed the problem by always
going straight to PCB).
At one time i purchased the augat custom pga socket makeing kit which
basically included a bunch of wire wrap socket pins and some phenolic
base boards. After all my parts ran out I've used the following
technique.
Find a bunch of wire-wrap sockets with machined pins. Rip appart the
sockets to get the pins. Drill your wire-wrap board holes to get a press
fit when the pins are inserted. Insert all the pins and press in place.
A stack of plain wrap cards placed undneath gives support to the board
while pressing in the pins. I use a drill press as a press (don't get
caught).
Eric
--
Eric Pearson -- Focus Systems -- Waterloo, Ontario
ecp@focus-systems.on.ca (519) 746-4918
"We Engineer Innovative Imaging Solutions"
Article: 5268Power estimation tools have been around for years in the ASIC business, but their prices are normally way above even the most expensive FPGA design tools. I cannot see why one could not do a hook into Viewsim (or whatever simulator one has) but presumably such a product would undermine the marketing of the present solutions. I too would have found power estimation extremely useful. I have spent a lot of time on this myself. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.Article: 5269
pac1 <pac1@waikato.ac.nz> wrote in article <5d4a0k$aec@netserv.waikato.ac.nz>... | I'm trying to decide if it is worth buying Xilinx Foundation BASE as | oppose to the standard XACT Step package (because its much cheaper). | | Can anyone tell me if it is any good, what are its limitations - I've | looked on Xilinx home page and can't find a good description of what it | can or can't do! The real difference between BASE and the Step package is the size of the device that you can create. The BASE package has all the same features but is limited to FPGA devices with about 3,000 usable gates. It has no such gate-size limitation on the CPLD devices. The families supported include: XC2000 FPGAs: All devices XC3x00A FPGAs: XC3x20A, XC3x30A, XC3x42A (but not XC3x64A, XC3x90A, XC3195A) XC4000 FPGAs: XC4002A, XC4003/E (but not larger devices) XC5200 FPGAs: XC5202, XC5204 (but not larger devices) XC7300 FPGAs: All XC9500 FPGAs: All You can also find out about Xilinx' XACTstep evaluation package at: http://www.xilinx.com/products/software/xacteval.htm If you are interested in the Foundation BASE package, also be sure to check out the packages offered by APS. They provide the Foundation tools and some innovative development boards. There is information on the Web at: http://www.erols.com/aaps/#PROGAMMABLE I hope this was helpful. -- Steven Knapp E-mail: optmagic@ix.netcom.com Programmable Logic Jump Station: http://www.netcom.com/~optmagicArticle: 5270
gonzo@res114.dana01.swarthmore.edu wrote in article <5d2jpf$phk@larch.cc.swarthmore.edu>... | Julio Cezar David de Melo <demelo@cpdee.ufmg.br> wrote: | >Well, I am currently working exactly on the PCI dev kit, and I aggree | >with you about its many bugs. It helped me a little with understanding | >the basic behaviour of the PCI bus, but is some miles away from | >following the PCI specification. | | I looked at it, decided it was a waste of time from the start, and am | going ahead with my own bus interface. Besides, my PCI glue logic | connects to five other busses, so it's really more of a router than a | bus driver anyway. Altera's stuff didn't really seem flexible enough | to handle something like this. You may also want to check out the Xilinx solution. I believe that it is more robust and has some fairly comprehensive protocol testing. There is more information available at: http://www.xilinx.com/products/logicore/lounge/pcim/pcim.htm -- Steven Knapp E-mail: optmagic@ix.netcom.com Programmable Logic Jump Station: http://www.netcom.com/~optmagicArticle: 5271
Has anyone done a side by side power dissipation comparison between large FPGAs such as the Altera 10K50V and the Xilinx 4036XL? Does anyone have experience with both Altera 10K and Xilinx 4000EX? Which device is a 'better' product?Article: 5272
We needed wire wrap sockets for a XILINX 4025...We got them from Samtec for
about $36 each.
Al Morrow
MediaLink Technologies
Scott McIntosh <gtd750a@prism.gatech.edu> wrote:
{Hello,
{ I'm using a Xilinx 4013E PG223 chip and currently the rest
{of the hardware is to be mounted with wire wrap sockets. Problem
{so far is I'm unable to find an 18x18,223 wire wrap socket. Are
{these just not available? Any other suggestions?
{Thanks,
{ Scott McIntosh
{ gtd750a@prism.gatech.edu
Article: 5273We have Workview office and the XACT tools, but unfortunately I don't have the documentation handy. Is it possible to do back annotation from a placed & routed Xilinx design so that the workview simulator (speedwave) gives correct timing information? And how is this done? -- Nicholas C. Weaver Ash C++ durbatuluk, ash C++ gimbatul, nweaver@cs.berkeley.edu ash C++ thrakatuluk agh burzum-ishi krimpatul! http://www.cs.berkeley.edu/~nweaver/ It is a tale, told by an idiot, full of sound and fury, .signifying nothing.Article: 5274
Steve Casselman wrote: Well....:) I just read a simular paper where the design was reconfigurable switches and 2-bit processors. You want to prototype a FPGA in an FPGA. Sounds very feasible for a small device. Thanks Steve, that sounds like a very reasonable approach. Is this perhaps a BYU "nanoprocessor" paper?
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Compare FPGA features and resources
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