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In Article<32E6069F.6F02@nfs.jozsef.kando.hu>, <szab@nfs.jozsef.kando.hu> write: > > My thesis is designing an universal GAL programmer. I have > got only ONE programming method. Because of internal incompatibility > of 16v8s and 20v8s from different manufacturers my method isn't > universal. > > Does anyone know differences between SGS's and AMD's method? > > Thanks for your help. > > Attila I don't think there are _ANY_ standard methods for programming PALs. Not only does each PAL-making company have its own algorithms, they are often different for different versions of the same chip from the same company. I think the only way to build a universal PAL programmer is to have it contain a lot of programmable pin-drivers (with control of voltage, current, slew-rate...) and then have a processor control them - hoping you can get the algorithms from the chip companies (not published by them normally). Regards Assaf SarfatiArticle: 5101
In article <5bo65g$mhn@news.global2000.net>, Encore Electronics
<encore@shell.global2000.net> writes
>Greetings... our customer generates JEDEC files for boards we build for
>him, and we do the programming of Lattice in-system-programmable parts on
>the board. I've got an older version of the code in .JED format, and a
>newer version he just created from scratch after losing the original
>source logic code (.LIF or .LDF files). The newer version naturally
>doesn't work, and we don't know exactly what's in the older one.
>
>Is there a way to reverse-compile the working .JED file to something
>humanly-understandable that we can tweak, so he can re-compile it again?
>I'm not too keen on the idea of taking the fuse map and writing out on a
>sheet of paper to see what fuses are blown and open, and then figuring out
>the logic from that.
>
>The part in question is the ispLSI1032... fortunately we haven't had this
>problem (yet) with the much larger ispLSI3256 he's also using on the
>board.
>
>Help?
>
>Tom Moeller
>Encore Electronics
>
Page 3-2 of the Synario User Manual (in the excellent Lattice starter
kit) states:
If you have JEDEC files that you want to convert to ABEL-HDL files to
use in a Synario project, you can use jed2ahdl in the Synario DOS
Window. You can bring up the Synario DOS window by pressing Crtl+Alt+D.
The options of jed2ahdl are listed below:
jed2ahdl infile -o outfile -report mapfile
......
It doesn't work for me. A Lattice rep told me it was in the full
Synario system but was also public domain. I haven't found it yet.
Regards,
--
nick toop
Article: 5102Philip Chong wrote: > > Hi folks: > > In article <32E533DE.7645@netcom.com>, vcc <vcc@netcom.com> wrote: > >Virtual Computer Corp. announces The First Reconfigurable Processing Unit > ^^^^^ > >on a PCI Board > > [Rest deleted] > > Is this true? What of the DEC Pamette, which (AFAIK) came out last > year: > > http://www.research.digital.com/SRC/pamette/ > > (I don't want to knock VCC; they've got some great stuff. But where's > the truth in advertising?) > > Phil Thanks: All other devices used in RCs before this were FPGAs, devices never meant for reconfigurable computing. All reconfigurable computers (including our own) were built upon those devices. FPGAs as such have had no real forethought put into an interface that can be easily used and understood. For example the 6216 has *control* registers that can be programmed to make the interface behave differently. It's like an FPGA but it is not. The 6200 has just as many wires as an FPGA but many of them are used for the micro interface. This makes the 6200 more powerful than an FPGA when the interface is used and less powerful then an FPGA when it is not used (some will like this, some will not). The XC6200 has so many features that say "I am not a FPGA" that you can not really pigeon hole it as "just another FPGA." It's not! So what is it? We are calling it a Reconfigurable Processing Unit. I think this distinction is the same as the difference between the microprocessor and the microcontroller. The way to the future for reconfigurable computing is open systems and that starts at open parts. The 6200 is the first and only part to publish full specifications. Already there is free software to program the part (it is fast 2 seconds compile time). There are simulators, emulators, high level languages, low level languages you name it and very soon someone will do it on the 6200! Why? Because they can. "First Reconfigurable Processing Unit on a PCI Board" ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ The "truth in advertising" is we feel XC6216 kicks off a whole new era for reconfigurable computing let us know what you think! Steve Casselman, President Virtual Computer Corp. VCC's Website: http://www.vcc.comArticle: 5103
Has any one used Altera's PCI development kit? If so, I'd like to hear about your experience and opinions. Specifically, does the Altera kit provide a turn-key PCI interface, or is there alot of development work to make it play? -Ray Andraka, P.E. Chairman, the Andraka Consulting Group 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://www.ids.net/~randrakaArticle: 5104
On 21 Jan 1997 15:47:39 GMT, "Jan Gray" <jsgray@acm.org> wrote: >The XC4020E meets your needs: use 2/3 of the device for SRAM >(2/3*28*28*32) and 1/3 for logic. According to www.marshall.com, >an XC4020E-4 is $169 Q1. > >The EPF10K40 on up also provide 2 KB of SRAM. An Oct. 28, 1996 >Altera press release said "The 50,000-gate 0.35-micron >3.3-V EPF10K50 is sampling now. The North >American price is $195 in 100-unit quantities and is >projected at $69 in 5,000-piece units by the middle of 1997." Good price. Must tell everyone in Europe! Using your 2/3 rule, Why not try Lucent OR2C15A. They've been shipping since February 1996, they're in 0.35-micron. They might even be lower cost than the above two. Just my two cents (which is cheaper now the exchange rate's up a bit) Come on people, let's see those quotes, I want that info. PleaseArticle: 5105
In article <32E7C653.3D49@ids.net>, randraka@ids.net says... > Has any one used Altera's PCI development kit? If so, I'd like to hear > about your experience and opinions. Specifically, does the Altera kit > provide a turn-key PCI interface, or is there alot of development work > to make it play? > > -Ray Andraka, P.E. > Chairman, the Andraka Consulting Group > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://www.ids.net/~randraka > We have been looking into PCI on Altera a little bit. They can supply you with a free minimal core that would require develpoment from you, or hook you up with 3rd party vendors that have synthesized PCI into Altera already and can sell it complete to you. The altera web page, http://www.altera.com has got info on this. -- William Vollrath, williamv@pacbell.net LOTS Technology, Inc. http://www.lasertape.comArticle: 5106
George Pontis wrote: > > Having long used Altera devices, I grew accustomed to first rate > telephone support for their software and device information. Now working > on a contract that specifically requires use of a Xilinx part, I am > beginning to realize easy it is to take that support for granted. > > The problem began 8 days ago, as I went to the Xilinx web site to find > out what kind of software would be required to read a pile of schematics > for an XC5206 design. There was almost no information on the site at > all. So I tried calling Xilinx. It took two tries to get an extension of > someone that would actually call back. The response ? "Call the local > rep, and ask them". It took me another three days for the rep to study > the problem and recommend a package. Now purchasing is working with the > distributor, to buy a copy of the specific foundation package. Due to > some sort of typo in the system, the desired package doesn't exist ! But > we can get the closest equivalent for 2X the price, with 2 week delivery > !! It sounds like your problem was on the sales side. Did you call their hotline, (800) 255-7778? > > All this, and then I have to get a Win95 (or 3.1x) computer since the > GUI version won't run on NT. With Xilinx tools, you rarely need the GUI. It is infrequent enough that a dual boot system would be OK (do their command line utilities run on NT?). Their GUI is useful for the LCA editor. Perhaps for the floorplanner as well. But to run place & route, you can simply run 'xmake <top level netlist name>' And of course you can add various command line options if needed. One nice thing about their tools, is that they integrate more easily into a formal methodology than do tools that require you to use a GUI. When you have command lines for each tool you use, you can make your work reproduceable. Also command line tools can be run from make, or from sophisticated design flow management software like vov (www.rtda.com). Regards, David Emrich > If anyone is getting started in the PLD > area and is making an Altera vs Xilinx decision, I recommend that they > include in their criteria ease of use of the tools and company support. > In my case, the www sites foretold a lot about the two organizations.Article: 5107
George Pontis wrote: > > Having long used Altera devices, I grew accustomed to first rate > telephone support for their software and device information. Now > working > on a contract that specifically requires use of a Xilinx part, I am > beginning to realize easy it is to take that support for granted. ... > If anyone is getting started in the PLD > area and is making an Altera vs Xilinx decision, I recommend that they > include in their criteria ease of use of the tools and company support. > In my case, the www sites foretold a lot about the two organizations. Well, it might be that you are just a bit more familiar with Altera than Xilinx. I find it strange to admit it after years of bitching, but Xilinx really does have some pretty decent software and support. There is a hotline available to users at 1-800-255-7778. I need to call every few months, and I always find them to be competent and responsible. By this I mean that while they usually can't respond to my inquiry or problem immediately, they always get back to me within a day or so with an appropriate response. While I can't comment on the Altera process, I'd have to say that Xilinx support is adequate and should not a be a determining factor in a decision about which parts to use. A similar issue exists with the software tools. While I've heard for years that Altera tools are very slick and spiffy, I can't say that the Xilinx tools have held me back. I should say that I don't see much value in the windows GUI and run everything from batch files from a command line. What is important to me is that the mapper/router works very well. With time constraint driven routing, and minimal placement of large data path elements, the Xilinx tools produce FPGAs of excellent quality. These designs route in 60 minutes or less even on 90% full 4020s. I don't see this as being excessive. As far as NT-DOS is concerned, It is irritating, but not a real problem. I route in DOS, then reboot and run NT. With the route taking 10's of minutes, the minute it takes to reboot is not significant. One thing which is very irritating about the Xilinx software is that it is often bundled with Viewdraw. I won't comment futher. Aside from tools, an important issue is the architecture of the FPGAs. While I'm sure the Altera parts work well, they lack some Xilinx 4K features which we find useful for data processing tasks. Except for the clock distribution issues, emulating these features usually just requires more 4 luts in the Altera 10K architecture making them slower and less efficient than the 4LUT count would indicate . Keep in mind that while I am very familiar with XC4000 devices, I am only looking at the preliminary Altera data sheets off the web site. Features Xilinx 4K FPGAs have and Altera 10K FPGAs are missing: - The 4LUTs may be configured as synchronous SRAM (optionally dual ported) 16*1 in size. The 4LUT can also be configured as a DFF if necessary. - Configurable carry chains which can be used for more than adder carry chains (ie subtractors, OR chains, AND chains, Priority encoders and comparators). - I/O Pins which are decoupled from the array by routing. This allows the Xilinx FPGAs to be more efficient when multiple designs are to be loaded into a fixed pinout. - Tri state busses. These allow a basically a big free mux. - High quality, multiple clock distribution. - Distinct clock enables on flipflops (on the Altera parts the use of a clock enable turns the 4 LUT into a 3 LUT) - Input pin latches (can this be true? I must be missing something here!) Features Altera 10K FPGAs have and Xilinx 4K FPGAs are missing: - dedicated SRAM blocks 256*8 in size at the edge of the chip. - A cascade chain (In 4K, the cascade OR and AND functions can be had via the configurable carry chain) - on board PLLs (ahh). I am also told the 100K runs really hot (Altera says 17 Watts exclusive of I/O for the 10K100 at 60MHz but does not specify the configuration). As far as I can tell both Xilinx and Altera have 3.3V compatible I/O Architecturaly it is more probably appropriate to compare the Xilinx 5K family to the Altera 10K parts. That being said, Altera is shipping a 10K100 FPGA with 4992 4LUTs and DFFs while the roughly equivalent Xilinx 4044EX is not shipping or supported by the current software release. The Xilinx NT-M1 release which does support the EX parts may not ship until summer. For comparison, the well supported and currently shipping XC4020E-2 has 1,568 4LUTS and 784 3LUTS which are about as useful as 2352 4LUTS. This indicates it is about half the size of a FLEX 10K100. The low cost Xilinx XC5215 has 1936 4LUTS. I'm not trying to dump on Altera here (or Xilinx), just pointing out the differences I see between the two companies' products. - BradArticle: 5108
In article <32E7C653.3D49@ids.net>, Ray Andraka <randraka@ids.net> wrote: > Has any one used Altera's PCI development kit? If so, I'd like to hear > about your experience and opinions. Specifically, does the Altera kit > provide a turn-key PCI interface, or is there alot of development work > to make it play? If you're looking to take the free PCI dev kit and turn a quick PCI design, forget it. While the design looks ok and will work to understand how to do a PCI logic design, there are several holes in the logic states that you could drive a truck through. Be prepared to spend a few weeks or months fixing the bugs. Several of the bugs will not show up until you try platforms like dec Alpha. Surprisingly, the really big holes did not show up on Macintosh PCI platforms (where the design first came up). Only when we crossed checked various Intel platforms did the bottom fall out. That's what we did (simple target, no master). I plan to re-write the whole thing from scratch later now that I understand it better. One problem was with IDSEL and configuration cycles. PCI spec (and I missed it too first time around) says that IDSEL is only valid during a config cycle. IDSEL is not defined for other cycles. The Altera logic design depended on the state of IDSEL during other cycles. Sure enough Macintosh PCI always left IDSEL deasserted on non-config cycles. On the other platforms, someone seems to didling with it on non-config cycles. Whamm, put card in, no boot. If I had to do it today, I would pick one of the PCI interface chips from PXL or V3. They have matured to a stable point now. When we did the design, too many bugs. Also logic analyser is a must for debuging. --------------------------------------------------------------------- Scott D. Davilla Phone: 919 489-1757 (tel) 4pi Analysis, Inc. Fax: 919 489-1487 (fax) 3500 Westgate Drive, Suite 403 email: davilla@4pi.com Durham, North Carolina 27707-2534 web: http://www.4pi.comArticle: 5109
Dftxpert (dftxpert@aol.com) wrote:
: Recently our company had a demonstration of the products from Gatefield,
: a division of Zycad Corporation.
:
: We were very much impressed with the GF100K family of Gatefield's FPGA's
: that range in capacities from 9,000 to 100,000 Gates.
:
: How does this compare to Xilinx and Altera who offer less than Gatefield?
Altera does offer 100,000 gates (10k100).
--
Warning: Unsolicited advertisements sent to me will be returned to the sender,
10 times on first offense, 100 times on third offense, 10*10^n times
on n-th offense. You spammers had been warned.
Article: 5110In article <5c2jm2$rnk$1@info1.fnal.gov>, husby@fnal.gov says... > Ahmad Alsolaim aa939788@oak.cats.ohiou.edu wrote: > > I am a P.h.D student at OhioU, I have been assigned to writ a > > proposal for an FPGA development lab. And since I am new in this field, > > can any one mail me a list of the most important things that have to bee > > included in the proposal. we are going to use PC Pentium200 station and > > Viewlogic's Workview Office. > > If you're gonna use Workview Office, I suggest that you spend the extra bucks > and get the monitor-pad option. This is a protective pad that goes around > your monitor to prevent injury as you repeatedly beat your head against it. I agree. And when you're done paying for the monitor pad, make sure you hand ViewLogic your checkbook, also, per their "request"! If you're going for Xilinx design (and it sounds like you might be, although you never specified the requirements for the FPGA development lab), here are some alternative suggestions: 1. The Xilinx/Aldec development SW, which runs under NT. I haven't used it personally, but it looks like an affordable and potentially competent solution for frontend and backend tools. 2. OrCAD windows-based toolset, combined with Xilinx (and others') back-end tools. This is extremely high bang-for-buck, and provides some cross-technology freedom that the Xilinx toolsets don't offer. The Orcad toolset line includes simulator and synthesis products. I'm sure there are lots of folks participating in this news group who wouldn't be shy about expressing their opinions about their experiences with various toolsets. One thing you should keep in mind... In an academic environment (rather than a commercial/industrial operation), there should be an added emphasis on specifying tools that are easy to pick up and "run". You don't want the world's most exquisite toolset at the expense of an intimidating learning (or configuration) curve. Also, in an academic environment there is less emphasis of maintaining and migrating designs from one product to the next. Standardising on a single (and usually expensive) toolset that will be supported for many years just isn't as important in academia. Just my $.02 ... -- Bob Elkind **************************************************************** Bob Elkind mailto:eteam@aracnet.com 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ****** Video processing, R&D, ASIC, FPGA design consulting *****Article: 5111
I'm gathering some material about implementing division with FPGAs; in particular I'd like to use Xilinx XC40xx. Can anybody help me? I know there is an article regarding it on the "Journal of VLSI Signal Processing" (v 7 n 3 May 1994 p 271-285), but I can't find it. The authors of that article are M.E.Louie and M.D.Ercegovac (UCLA). If you think you've something of interesting for me, please e-mail it to me. I would appreciate any help you may be able to provide. Thanks in advance.Article: 5112
husby@fnal.gov (Don Husby) wrote: >Ahmad Alsolaim aa939788@oak.cats.ohiou.edu wrote: >> I am a P.h.D student at OhioU, I have been assigned to writ a >> proposal for an FPGA development lab. And since I am new in this field, >> can any one mail me a list of the most important things that have to bee >> included in the proposal. we are going to use PC Pentium200 station and >> Viewlogic's Workview Office. > >If you're gonna use Workview Office, I suggest that you spend the extra bucks >and get the monitor-pad option. This is a protective pad that goes around >your monitor to prevent injury as you repeatedly beat your head against it. > > <g> Do you know the part number of this item, I need it bad. ;-(Article: 5113
Nils.Koehler@t-online.de (Nils Koehler) writes: >Hello Max Plus 2 User >I have a Problem with the Software version 7.1 >My Problem ocured also with version 7.0 >The Problem is: If i compile a 10K design i get an internal error at 5% in the > SNF Extractor. >If i compile the design with a 10KA or MAX 7000 or MAX 8000 it works. >Only with 10K i have those problems. >I send you a small GDF File wit my Problem. >My System : Win 95 > Pentium 166 Mhz > 90 Mb Ram >If there is anybody out there who knows something about this let me know. A coworker had the same problem with a 7000S design. I think he worked around it by turning off the "Timing SNF Optimization" in one of the compiler option menus (I forget the menu name - it's the one where you can also control things like Fitter options and Smart Recompile). Of course, you could also just turn off the SNF extractor altogether (I think timing is still embedded in the EDIF output, but you need the SNF to run Timing Analyzer). -Paul -- Paul Secinaro (pss1@christa.unh.edu) Synthetic Vision and Pattern Analysis Laboratory UNH Dept. of Electrical and Computer EngineeringArticle: 5114
Nils Koehler wrote: > > Hello Max Plus 2 User > > I have a Problem with the Software version 7.1 > My Problem ocured also with version 7.0 > > The Problem is: If i compile a 10K design i get an internal error at 5% in the > SNF Extractor. > > If i compile the design with a 10KA or MAX 7000 or MAX 8000 it works. > Only with 10K i have those problems. > > I send you a small GDF File wit my Problem. > > My System : Win 95 > Pentium 166 Mhz > 90 Mb Ram > > If there is anybody out there who knows something about this let me know. > > Thanks a lot > > > ######################################################### > # # > # Nils Koehler # > # Fa. IBT Nachrichtentechnik GmbH # > # Tel. ++49 6074/8948-0 # > # Fax. ++49 6074/8948-90 # > # # > # mailto: Nils.Keohler@T-Online.de # > # # > ######################################################### Hello, I don't know if it helps, but sometimes I have similar problems (internal errors) with version 6.2 (we already have v7.1 but I didn't install it yet). These errors aren't device specific on my machine. My system is a P100, with 16MB RAM, Win3.1, 64 MB virtual RAM and S3 trio 64. Increasing the amount of the virtual RAM has helped (the internal errors occured least often). Onfortunetly it won't work under W95. Installing a new version of Win32s also helped. This won't help you neither. Choosing another video mode also helped (1280x1024x16 or 1024x768x16 instead of 1280x1024x256). Maybe you could try this in W95 too. Let me know, if you have solved the problem. Botond -- Kardos, Botond - at Innomed Medical Co. Ltd. in Hungary eMail: kardos@mail.matav.hu phone/fax: (36 1) 268-0934Article: 5115
I have done four PCI designs using FPGAs, only for Xilinx. Altera didn't have the internal tri-state bus at the time I started doing PCI designs...which is a real nice feature when you are running a 32 bit bus through the chip. The 'free' or canned designs I have seen are not that good. Most of the work isn't in the PCI state machines and config space (though this is a big job in it self...) it is in the back end interface, and making the 33MHz timing and the PCI setup and hold timing... Target designs are pretty easy. Using the 'canned' PCI interface chips out on the market is not necessarily that cost effective. Unless you can use their interface directly, you will obviously have to do some extra logic to make what their idea of a back end interface is to match what your idea of a back end interface is. The chips cost about the same as a 4013E-2/3 Xilinx (in volume) and you can fit a lot of back end logic in there. Doing a burst master is the toughest part of using an FPGA. You have to be able to respond very quickly to input signals, and this requires some tricky logic and some logic tricks...and very careful placement and routing. But...it is doable. Austin Franklin ..darkroom@ix.netcom.com.Article: 5116
Hi I have cadence 9502 and Xact 5.2.0. If I follow the design flow for xilinx in cadence then I can not simulate with back annotated delays. The reason appears to be that Xact produces XNF version 6 while cadence can only handle upto version 5. Is there a way I can force Xact to write out an older version of XNF? Alternativley if there is a way to convert version 6 to version 5 then I might be able to fool cadence Thanks in advance for your help JohnArticle: 5117
> out what kind of software would be required to read a pile of schematics > for an XC5206 design. It seems odd to me that you, or no one else could tell you what schematic tool was used to create these schematics? There aren't too many out there, and if you have familiarity with what is available (ie. viewdraw, orcad... etc.) then the file name, or directory structure should give you enough clues. Sorry, but I guess that's about a 10 minute answer for me....and maybe I assume that other prople contracting for work would know what tools are available and have some familiarity with them. I assume having a good knowledge of available tools is default for a contractor.... > All this, and then I have to get a Win95 (or 3.1x) computer since the > GUI version won't run on NT. I run the Xilinx tools under NT with no problems at all. The only tool that doesn't currently run is the floor planner. More experienced users use batch files to run the tools. This gives you control over exactly what happens, and what options are used. Also gives you reproducable results. > If anyone is getting started in the PLD > area and is making an Altera vs Xilinx decision, I recommend that they > include in their criteria ease of use of the tools and company support. > In my case, the www sites foretold a lot about the two organizations. If you are used to doing something one way, or lack the experience, you will not be efficient with a new set of tools. Some people prefer Unix, some prefer VMS, it's all in what you've been brought up using... I find today, and have found in the past, the Xilinx technical support to be excellent. Since I have been doing both Xilinx and Altera designs for 9 years now, when I call for support, it is usually for a real tough problem... Xilinx does resolve show stopper problems quite quickly. I also find their web site has just the info I need from a web site. It has the phone numbers of who I need to call, has the parts specs, and has a support data base I can search through to see if anyone solved/reported this problem before. It also contains updates to files I may need... As you said, Altera does have excellent support. I think the Xilinx support and web site are on par with Alteras'. I find the Xilinx tools to be a better set of tools for an experienced user. The Altera tools are more 'push button' but Xilinx gives you more and better tools to control the outcome of the design. Also I think the Xilinx FPGAs have better features than the Alteras. Austin Franklin ..darkroom@ix.netcom.com.Article: 5118
Steve Casselman wrote: > > Thanks: All other devices used in RCs before this were FPGAs, devices > never meant for reconfigurable computing. All reconfigurable computers > (including our own) were built upon those devices. FPGAs as such havesnip > The XC6200 has so many features that say "I am not a FPGA" that you can > not really pigeon hole it as "just another FPGA." It's not! So what is > it? We are calling it a Reconfigurable Processing Unit. I think this > distinction is the same as the difference between the microprocessor and > the microcontroller.clip > The "truth in advertising" is we feel XC6216 kicks off a whole new era > for reconfigurable computing let us know what you think! > > Steve Casselman, President > Virtual Computer Corp. > VCC's Website: http://www.vcc.com Steve - It's obvious that the XC6000 wins the reconfiguration part of the performance equation, but how about the computing side? It has been some months since I looked for info on the relative performance of, say, a 16-bit adder or counter implemented in a XC4000 vs. XC6000 device. Since you are now in a position of having worked with both, do you have any numbers? -- John L. Smith, Pr. Engr. | Sometimes we are inclined to class Univision Technologies, Inc. | those who are once-and-a-half witted 6 Fortune Dr. | with the half-witted, because we Billerica, MA 01821-3917 | appreciate only a third part of their wit. jsmith@univision.com | - Henry David ThoreauArticle: 5119
Vanni FADONE wrote: > > I'm gathering some material about implementing division with FPGAs; in > particular I'd like to use Xilinx XC40xx. > Can anybody help me? > I know there is an article regarding it on the "Journal of VLSI Signal > Processing" (v 7 n 3 May 1994 p 271-285), but I can't find it. The > authors of that article are M.E.Louie and M.D.Ercegovac (UCLA). > > If you think you've something of interesting for me, please e-mail it to > me. > I would appreciate any help you may be able to provide. > Thanks in advance. How fast does the division need to be? Of the top of my head I can think of two ways: Newton-Raphson (I don't think I spelled that right) and a Cordic algorithm. They are both iterative schemes that are well suited for hardware. I can look them up in my computer arithmetic book if yu are interested... JoseArticle: 5120
Rob Hurley (rob@doulos.co.uk) wrote: : ANNOUNCE: NEW MODEL AND TIP OF THE MONTH : This month's model is: : : Simple RAM model in Verilog : This month's tip is: : : Re-usable Functions : You can find both at 'THE WINNING EDGE' http://www.doulos.co.uk : You can also access previous Models and Tips of the Month from the : same site. During 1996 these included: : A to D converter : Design for Debug : How to avoid synthesising unwanted latches : FIR filter : .... and many more : During 1997 Doulos will continue to develop THE WINNING EDGE to : include more VHDL and Verilog tips, tricks, tutorials and models. : Our aim is to make THE WINNING EDGE one of the most useful High : Level Design sites out there. : ____________________________________________________________________ : Also *** NEW *** for this month are: : Free CBT software for Verilog : Additions to our Hardware Engineer’s Guide to VHDL series : _____________________________________________________________________ : DOULOS : Church Hatch Tel: +44 1425 471 223 : 22 Market Place Fax: +44 1425 471 573 : Ringwood BH24 1AW Email: webmaster@doulos.co.uk : UK : _____________________________________________________________________Article: 5121
Rob Hurley (rob@doulos.co.uk) wrote: : ANNOUNCE: NEW MODEL AND TIP OF THE MONTH : This month's model is: : : Simple RAM model in Verilog : This month's tip is: : : Re-usable Functions : You can find both at 'THE WINNING EDGE' http://www.doulos.co.uk : You can also access previous Models and Tips of the Month from the : same site. During 1996 these included: : A to D converter : Design for Debug : How to avoid synthesising unwanted latches : FIR filter : .... and many more : During 1997 Doulos will continue to develop THE WINNING EDGE to : include more VHDL and Verilog tips, tricks, tutorials and models. : Our aim is to make THE WINNING EDGE one of the most useful High : Level Design sites out there. : ____________________________________________________________________ : Also *** NEW *** for this month are: : Free CBT software for Verilog : Additions to our Hardware Engineer’s Guide to VHDL series : _____________________________________________________________________ : DOULOS : Church Hatch Tel: +44 1425 471 223 : 22 Market Place Fax: +44 1425 471 573 : Ringwood BH24 1AW Email: webmaster@doulos.co.uk : UK : _____________________________________________________________________Article: 5122
In article <t1y4tg9n1ey.fsf@i90s26.ira.uka.de>, Thomas Worsch <worsch@ira.uka.de> wrote: > > Question: How can one find out when the first byte can be written to > the FPGA for configuration? > > It seems that according to the description on page 4-74 in the XILINX > data book (version 1.02, June 96) RDY/BUSY cannot be used. > During the configuration process, asynchr. peripheral mode uses a conventional handshake protocol with write strobe as the input to the FPGA, and REDY/BUSYbar as the response. Timing is very forgiving: 60 ns data set-up before the end of write strobe, no hold-time requirement. So far, so good. Before the beginning of configuration, all outputs,( including READY ! ) are 3-stated with a weak pull-up. This makes the chip appear ready to receive a write strobe, when in reality it might not be, Solution: A 1 kilohm to 2 kilohm external resistor from READY to ground keeps that pin Low ( = BUSY ) until the chip is ready to receive a write strobe. The user can thus always trust the handshake. I meant to be complete in the data book description, but I missed this. Sorry. Peter Alfke, Xilinx Applications.Article: 5123
Did you consider Synario ??? To my experience, it's the one and only solution to be entirely focused on FPGA design. If you want to focus on FPGA design rather than on using a specific front end + mastering specific design flaws (ooops.. flows), different for each FPGA family, give Synario a chance ! Porting a design between architectures can be a snap ! Hope it helps, -- ////////////////////////////////////////////////////// Bert CUZEAU - ALSE France * FPGA-CPLD Design and Synario Expert * VHDL and Synario Trainings * Consultant http://ourworld.compuserve.com/homepages/alse Return address is invalid to defeat junk mail. Please reply to : alse@compuserve and add ".com". ////////////////////////////////////////////////////// Ahmad Alsolaim <aa939788@oak.cats.ohiou.edu> wrote in article <E4CJsF.4tM@boss.cs.ohiou.edu>... > Hello, > I am a P.h.D student at OhioU, I have been assigned to writ a > proposal for an FPGA development lab. And since I am new in this field, > can any one mail me a list of the most important things that have to bee > included in the proposal. we are going to use PC Pentium200 station and > Viewlogic's Workview Office. > Also what is the best (in terms of compatiblity with other vendors) > FPGAs testing borad. > > Thank you in advanced. > aalsolai@homer.ece.ohiou.edu > -- >Article: 5124
Anyone have any ideas on how to "manually" configure an FPGA outside of a development environment such as orcad/viewlogic/etc.? I already talked to Xilinx and they won't release that kind of data for their 4xxxEX series (or for the 3xxx or 4xxx series, for that matter), and the 6200 series they recommended has no such data in the data sheet as I was told. I understand their position on security, but that doesn't get me anywhere. Any solutions?
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