Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hello sir, When i'm doing floorplanning, without giving any constraints ,i'm getting error in mapping,which shows error as- a) Unable to obey design constraints (LOC = CLB_R14C34.S1) which require the combination of the following symbols into a single I/O component: PAD symbol "X<8>.PAD" (Pad Signal = X<8>) BUF symbol "U88" (Output Signal = n114)LUT symbol "U3/U8/U0" (Output Signal = U3/U8/temp1)LUT symbol "U3/U9/U0" (Output Signal = U3/U9/temp1)The symbol X<8>.PAD has a constraint (LOC=CLB_R14C34.S1) that specifies an illegal physical site for the component.Please correct the constraintvalue.Please correct the design constraints accordingly. b)FATAL_ERROR:Pack:pktbamfp.c:1002:1.14.14.2 - Problem with LOC prop 'CLBYR21C5.S1' on MFP constraint 'FG CLBYR21C5.S1 I0 Y<2> I1 X<2> I2 X<3> I3, Y<1> O U1/U3/temp1 ;' - No such site on the device.. Please help me to solve this problem. regards ChandrakiranArticle: 38576
i use xilinx foundation 3.1i when i download service pack8 3_3_08i_pc.exe Aldec_2001_3.exe FPGAExp35.exe i'm use OS windows Me it's can't implement it's show this error FATAL_ERROR:StaticFileParsers:Xml_Node.c:358:1.12.8.2 - Corrupt or > missing XmlArticle: 38577
I think in xilinx.com has an answer about your problem. I think you must download the SP7, install it and then install the SP8. Check it out in the web site for sure "dotty1319" <dotty1319@hotmail.com> wrote in message news:ac44422f.0201172155.36117cb0@posting.google.com... > i use xilinx foundation 3.1i > when i download service pack8 > 3_3_08i_pc.exe > Aldec_2001_3.exe > FPGAExp35.exe > i'm use OS windows Me > it's can't implement > it's show this error > FATAL_ERROR:StaticFileParsers:Xml_Node.c:358:1.12.8.2 - Corrupt or > > missing XmlArticle: 38578
Any of these delay line srpingey things available in surface mount? Ha only joking. Thanks to everyone for all the ideas and have a good 2002. regards Simon Fisher Peter Alfke <palfke@earthlink.net> wrote in message news:<3C47AB75.E1C9332F@earthlink.net>... > I was at Sweda cash registers, Swedish junior sister of Monroe, who loved > drums, so we first tried to use the delay line like a drum. But it was not > stable enough to pack it full, like a ring, as you do on a drum. So we > left a gap, and made sure the gap would neither grow nor shrink. It was a > stored instruction design, but the details are getting foggy... > Transistors were very expensive, and read-out was a real problem before > the advent of Nixie tubes. Makes you appreciate today's plethora of > solutions. > > Peter Alfke > > Eric Smith wrote: > > > Peter Alfke <peter.alfke@xilinx.com> writes: > > > Back in 1965 I was supposed to stuff much of the logic and all of the > > > memory for an electronic cash register into such a torsional delay > > > line. > > > > How do you stuff logic into the delay line? > > > > > We managed to squeeze in 15,000 bits and run that reliably, > > > > Quite impressive! What was the physical length of the delay line? > > > > I have a Monroe 990 calculator that stores only around 120 bits into a > > delay line made by NEC, and fails to do that reliably. I assume it was > > reliable back in 1971 though. > > > > The Friden seems to work reliably though. It was made in 1964, and > > stores around 280 bits. Actually more channel bits, because they > > use a strange encoding rather than straight binary.Article: 38579
who can introduce the some books,link,resource about verilog/vhdl codeing style ,experience?Article: 38580
Hallo, does anybody has experience with an DDR-Interface in FPGA. We have to use the Micron MT46V2M32 (64 Mbit, 512k x 32 bit x 4 banks) a 32 DataBit, 1 DQS signal interface component at a minimum of 133 MHz clock frequency for video application. We tried it with the new Altera APEXII EP2A15, but run into lot of trouble. Has anybody run such an DDR interface with Altera, Xilinx or other manufactorers? Thanks in advance for your help JuergenArticle: 38581
Doesn't altera provide a free DDR core on their web site? You could also look at the cores at www.opencores.org though I don't think I saw a DDR one. Paul "Juergen Buehler" <buehlerj@thmuli.com> wrote in message news:3C4803EE.43C4B0AC@thmuli.com... > Hallo, > > does anybody has experience with an DDR-Interface in FPGA. We have to > use the Micron MT46V2M32 (64 Mbit, 512k x 32 bit x 4 banks) a 32 > DataBit, 1 DQS signal interface component at a minimum of 133 MHz clock > frequency for video application. We tried it with the new Altera APEXII > EP2A15, but run into lot of trouble. > Has anybody run such an DDR interface with Altera, Xilinx or other > manufactorers? > > Thanks in advance for your help > > Juergen >Article: 38582
yuryws@optonline.com (Yury) wrote in message news:<fb9fd058.0201172014.12b797fa@posting.google.com>... > Implemented 1/2 Band 51-tap FIR using Coregen + Foundation. > Pre-synthesis simulation looks excellent, however when the filter is > loaded into Spartan-II the output looks like complete random junk. All > timing is met. > > Does anyone have a similar experience or an idea for a potential > problem area? > > Thanks. I have not used this Coregen IP, but you mentioned that the Pre-synthesis simulations look excellent. How about post PAR simulations? One can also do an inbetween post PAR simulation without the SDF if need be. The reason I mention this is maybe the constraints need a little bit more work. Are you sure the digital input data is frequency limited to within your digital filter's specifications? Are you using DLL's?, they have min/max frequency and jitter specifications. NewmanArticle: 38583
Benn wrote:
> who can introduce the some books,link,resource about verilog/vhdl codeing style ,experience?
HDL chip design by Douglas J. Smith has a pretty good comparison between VHDL and Verilog.
It has quite a few examples of the same logical circuit coded in both VHDL and Verilog, which
can give you a sense of the style used in each language. It doesn't go deep into either
language, but is a good starting point.
Andrew Pallek
Article: 38584Hi could you explain which kind of problems you have met? Robi Juergen Buehler wrote: > Hallo, > > does anybody has experience with an DDR-Interface in FPGA. We have to > use the Micron MT46V2M32 (64 Mbit, 512k x 32 bit x 4 banks) a 32 > DataBit, 1 DQS signal interface component at a minimum of 133 MHz clock > frequency for video application. We tried it with the new Altera APEXII > EP2A15, but run into lot of trouble. > Has anybody run such an DDR interface with Altera, Xilinx or other > manufactorers? > > Thanks in advance for your help > > JuergenArticle: 38585
Using Quartus 2 1.1SP2 on W2k In order to document some bits of my design I took the decision to start with block diagrams and then generate the VHDL for Leonardo or the Altera tools to work with. (the VHDL for top level simple blocks, not the core VHDL code). I find the block diagrams easier to use as documentation and this way have the virtue of staying in sync with the design. However I can't seem to rip a single bit from a bus to go to a single output pin as well as to its other destination. [In the old days I used to be able to instantiate a bus ripper symbol and rip a single bit but can't find an equivalent method now.] The instance I have is a megawizard-generated 24 bit counter. q[23..0] are fed to an AND gate instance with the other input connected to a single wire signal 'pass_it_through'. I have named this bus countval[23..0]. The output of the AND is called 'gated_count' and is generated OK. Now I want a single bit of q (say q[7]) to go to another output pin named 'pulsing_signal'. In the BDF I can't seem to get this to generate the correct VHDL. The 'pulsing_signal' output is named as an output port but has no logic associated with it. I can easily go into the VHDL and add the necessary link and it works fine, but I'd really like to be able to rip this single bit in the BDF to keep the design files in step. Any help appreciated. PaulArticle: 38586
Juergen, We have many successful designs that I have seen from our customers using HSTL, SSTL, and LVDCI at 133 MHz DDR in Virtex family devices. In Virtex II, the IOB has the dedicated DDR FF which is optimized for inputs and outputs. The DCM removes all clock skew, and provides duty cycle corrected clocks (better timing margins). Signal integrity on your board, avoidance of cross talk induced delay variations in your bus, are all issues that will break any design (Altera or Xilinx). Oh, and bypassing must be excellent, or else you give up even more in having ground bounce that not only ruins the noise margin, but adds jitter. Look at the app notes: http://www.support.xilinx.com/xapp/xapp253.pdf http://www.support.xilinx.com/xapp/xapp214.pdf http://www.support.xilinx.com/xapp/xapp200.pdf .... and more. Austin Juergen Buehler wrote: > Hallo, > > does anybody has experience with an DDR-Interface in FPGA. We have to > use the Micron MT46V2M32 (64 Mbit, 512k x 32 bit x 4 banks) a 32 > DataBit, 1 DQS signal interface component at a minimum of 133 MHz clock > frequency for video application. We tried it with the new Altera APEXII > EP2A15, but run into lot of trouble. > Has anybody run such an DDR interface with Altera, Xilinx or other > manufactorers? > > Thanks in advance for your help > > JuergenArticle: 38587
The FPGA array card aim is to support many designs (each potentially completely different) and to operate at very high bit rates.Article: 38588
Hi Paul, The free DDR core is only for a 20k Device. The problem when using the APEXII is that there is a difference between the documentation (marketing stuff !!!) and the technique. A lot of things which are described in the documentation are not functional as they are described. For example the plls, ddr-lpms and the STTL2 output standart. At opencores there are no DDR-RAM Interfaces described. The problem is not the DDR controller, the problem is the realisation of the hardware interface in the FPGA. There we miss a lot of information about a successful implementation Jürgen Paul Baxter wrote: > Doesn't altera provide a free DDR core on their web site? > > You could also look at the cores at www.opencores.org though I don't think I > saw a DDR one. > > Paul > > "Juergen Buehler" <buehlerj@thmuli.com> wrote in message > news:3C4803EE.43C4B0AC@thmuli.com... > > Hallo, > > > > does anybody has experience with an DDR-Interface in FPGA. We have to > > use the Micron MT46V2M32 (64 Mbit, 512k x 32 bit x 4 banks) a 32 > > DataBit, 1 DQS signal interface component at a minimum of 133 MHz clock > > frequency for video application. We tried it with the new Altera APEXII > > EP2A15, but run into lot of trouble. > > Has anybody run such an DDR interface with Altera, Xilinx or other > > manufactorers? > > > > Thanks in advance for your help > > > > Juergen > >Article: 38589
I'm thinking about having several Virtex-II's talking to each other across a backplane. They will probably be 300+ LVDS signal pairs at 400MHz+. Is there any commercial passive backplanes that can do the job?Article: 38590
This is a multi-part message in MIME format. --------------3CCCC635B35B44EAC2969386 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Antonio wrote: > Good Morning, > Following there's the code of the implementation of my project using > clock enable structure, about this I don't know what to do regarding > the following points, can you help me in this ?? > > a) Anno:197 - NGDAnno found 12 physical component(s) for which 100 > percent > back-annotation is not possible. Simulation models for these > components will > be constructed from the NCD. Sounds like you are doing a logical annotation (Correlate Simulation Data to the Design in the GUI, using the ngm file with ngdanno in command-line). To understand the message, you must understand this mode. Defaultly, when creating a HDL simulation netlist, the Xilinx software will create the netlist from the physical database so that it is more of a what you see is what you get type of netlist. If however, you select to use a logical annotation, the back annotation software (ngdanno) will start with the physical design and attempt to replace signals and structures that were in the input netlist that may have been mergerd, optimized or changed in other ways during the mapping and place and route process. These "changed" signals and components are stored in a file called the NGM file which anno uses to attempt to restore these pieces of the design so that the back-end view more closely resembles what you input to the tools even though it may not be physically implemented that way in the design. This annotation is not suppoesed to effect the functionality or timing properties of the netlist. What the warning is attempting to tell you is that it found 12 components in the ngm file in which it can not reconstruct in the file for one reason or another. This should not have an effect on the end netlist in terms of functionality or timing however it is saying it could not match everything it knows possible to match for logical annotation to 100% correlation. Generally this can be safely ignored. > b)Ngd:333 - NOTE: This design contains the undriven net "GSR" which > you > could drive during simulation to get valid results. > Ngd:333 - NOTE: This design contains the undriven net "GTS" which > you > could drive during simulation to get valid results. GSR and GTS signals are the Global Set Reset net and the Global Tri-State net. These are signals placed in teh simulation to control the global reset and global tri-state functions that happen in all FPGAs during configuration. The GSR signal should always be pulsed before the beginning of simulation in order to ensure a properly initialized design. If you are using VHDL, this is generally done for you by the use of a component in the netlist called the ROC (Reset On Configuartion). It will defaultly pulse the GSR signal for 100 ns at the beginning of the simulation. F9or Verilog users, this must be driven manually from the testbench. As for the GTS signal, you can leave that un-dirven if you like howveer if you wish to mimic global tri-state in a board-level simulation, this signal could be useful in that case. I do not think most people use this signal in most simulation scenarios. More information of GTS and GSR can be found in the Synthesis and Simulation Design Guide in the Xilinx, docs: http://toolbox.xilinx.com/docsan/xilinx4/index.htm > c)NetListWriters:306 - Signal bus U1/to_add_a( 6 downto 0 ) on block > Polyphase_x4 is not reconstructed, because there are some missing > bus > signals. > NetListWriters:306 - Signal bus U1/U1/to_add_g( 9 downto 5 ) on > block > Polyphase_x4 is not reconstructed, because there are some missing > bus > signals. What this is telling you is that some bits of a "known" bus are missing and therefore can not re-create the bus for the simulation netlist. It will instead declare them as individual bits. The reson for this can be that some signals got re-named or perhaps got optimized out due to not being properly connected in some fashion. This may or may not be a problem for you but generally is not a problem as long as the front-end simulation runs as expected, and the synthesis tool did not do anything to modify that behavior. I would simulate the design and if this area of the circuit appears to be functioning, then I would assume this not to be aproblem. If howveer, this section of the circuit is not functioning, it gives you a clue as to where to start looking. -- Brian > Loading device for application ngdanno from file 'v1000.nph' in > environment > C:/Xilinx. > Building NGA image... > Annotating NGA image... > Distributing delays... > Anno:197 - NGDAnno found 12 physical component(s) for which 100 > percent > back-annotation is not possible. Simulation models for these > components will > be constructed from the NCD. Rerun NGDAnno with the -report option > for > additional details, including any net and instance names which are > lost in > this process. > Creating Guaranteed setup and hold checks... > Guaranteed Setup and Hold Checks were created for 1 input IOB(s). > Resolving logical and physical hierarchies... > Anno:178 - 2 hierarchical blocks were flattened during > back-annotation. > Rerun NGDAnno with the -report option to see a list of these > blocks, as well > as additional information about nets and instances that may not > have their > original names. > Running NGD DRC... > Ngd:333 - NOTE: This design contains the undriven net "GSR" which you > could drive during simulation to get valid results. > Ngd:333 - NOTE: This design contains the undriven net "GTS" which you > could drive during simulation to get valid results. > Writing .nga file "Polyphase_x4.nga"... > 172 logical models annotated > 12 physical models annotated > Executing C:\Xilinx\bin\nt\ngd2vhdl.exe -w "Polyphase_x4.nga" > "C:\Tesi\Aggiunte_dal_6_1_2002\Aldec\SRRCx4_Implementations\SRRCx4_newCoeffs_ClkEnable_13_01_2002\implement\ver1\rev1\time_sim.vhd" > -xon true > > C:\Tesi\Aggiunte_dal_6_1_2002\Aldec\SRRCx4_Implementations\SRRCx4_newCoeffs_ClkEnable_13_01_2002\implement\ver1\rev1>set > XILINX=C:\Xilinx > > C:\Tesi\Aggiunte_dal_6_1_2002\Aldec\SRRCx4_Implementations\SRRCx4_newCoeffs_ClkEnable_13_01_2002\implement\ver1\rev1>set > PATH=C:\Xilinx\bin\nt > Release 4.1.03i - ngd2vhdl E.33 > Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved. > ngd2vhdl: Reading design Polyphase_x4.nga ... > ngd2vhdl: Specializing design ... > ngd2vhdl: Flattening design ... > ngd2vhdl: Flattening design completed. > ngd2vhdl: Specializing design completed. > > ngd2vhdl: Processing design ... > ngd2vhdl: Preping physical only global signals ... > ngd2vhdl: Preping design's networks ... > ngd2vhdl: Preping design's macros ... > NetListWriters:306 - Signal bus U1/to_add_a( 6 downto 0 ) on block > Polyphase_x4 is not reconstructed, because there are some missing > bus > signals. > NetListWriters:306 - Signal bus U1/U1/to_add_g( 9 downto 5 ) on block > Polyphase_x4 is not reconstructed, because there are some missing > bus > signals. > ngd2vhdl: Preping design completed. > > Thanks > > AntonioArticle: 38591
Okay, that's good for modeling. Will the free web-based tools tools from Xilinx, Altera and Cypress synthesize a 128x32 ROM by fitting it into a RAM block? It seems like a simple thing, but I would expect them to try to use logic blocks. BTW, what's a .PLA file? I saw a small ROM defined using it. It was for the synthesis model. It went something like this: # .design ROM .inputnames addr[0] addr[1] addr[2] addr[3] .outputnames data[0] data[1] data[2] data[3] data[4] data[5] data[6] data[7] data[8] data[9] data[10] data[11] data[12] data[13] data[14] data[15] 0000 0010110100000000 0001 0000011000001000 ... "Speedy Zero Two" <david@manorsway.freeserve.co.uk> wrote in message news:<a27eqb$k$1@newsg2.svr.pol.co.uk>... > Brad, > > ROM's are just simple case statements with the address as selects and data > as outputs like, > > module (address,data) > > input address; > output data; > > case (address) > 0: data = 0; > 1: data =1; > endcase > > endmodule > > hope this helps, > Dave > > "Brad Eckert" <brad@tinyboot.com> wrote in message > news:4da09e32.0201170728.4206ba97@posting.google.com... > > I want to generate a 128x32 ROM for Spartan II using CoreGen. Will > > CoreGen work with Xilinx Webpack tools? If not, could someone post the > > code for a blank ROM that I could fill in with my own data? FWIW, I'm > > using Verilog. > > > > -- > > Brad EckertArticle: 38592
I don't understand how this delay wire worked... the transducer twisted the wire to create torsional pulses? How long was a pulse? How could you possible fit thousands of pulses in one wire and not have them die out? When the pulses came out the end, were they amplified and recirculated into the ring? And then how did you find a particular byte? Was there some sort of framing? There was a time before Nixie tubes? "Peter Alfke" <palfke@earthlink.net> wrote in message news:3C47AB75.E1C9332F@earthlink.net... > I was at Sweda cash registers, Swedish junior sister of Monroe, who loved > drums, so we first tried to use the delay line like a drum. But it was not > stable enough to pack it full, like a ring, as you do on a drum. So we > left a gap, and made sure the gap would neither grow nor shrink. It was a > stored instruction design, but the details are getting foggy... > Transistors were very expensive, and read-out was a real problem before > the advent of Nixie tubes. Makes you appreciate today's plethora of > solutions. > > Peter Alfke > > Eric Smith wrote: > > > Peter Alfke <peter.alfke@xilinx.com> writes: > > > Back in 1965 I was supposed to stuff much of the logic and all of the > > > memory for an electronic cash register into such a torsional delay > > > line. > > > > How do you stuff logic into the delay line? > > > > > We managed to squeeze in 15,000 bits and run that reliably, > > > > Quite impressive! What was the physical length of the delay line? > > > > I have a Monroe 990 calculator that stores only around 120 bits into a > > delay line made by NEC, and fails to do that reliably. I assume it was > > reliable back in 1971 though. > > > > The Friden seems to work reliably though. It was made in 1964, and > > stores around 280 bits. Actually more channel bits, because they > > use a strange encoding rather than straight binary. >Article: 38593
Steve Holroyd wrote: > > I am currently task of recommending the largest, fastest and most > memory FPGA that's readily available the first half of this year for a > FPGA Array Card. > > The choices have been narrowed down to two families Altera's APEX-II > (EP2A70) and XILINX Virtex-II (XC2V6000). > > Which can operate at the highest speed? Take some sample designs, make them fit, then check static timing for speed. If all else is equal go with the best sales and distribution support. --Mike TreselerArticle: 38594
I have a question here on Altera's LPM_ROM, I have stored some data in the *.mif file and I want to send out to a register. Meaning, from the LPM_ROM and go through a 8-bit registers. However, I got the error message displayed after trying to compile it in MaxPlux2 => "TRI or OPNDRN buffer something, something, and can only drive logic something is only connected to BDIR." Can anyone who is familiar with Altera's LPMs teach me how to set the setting for the LPM_ROM. For you information, my WidthADD is 3 and Width is8 bit. I am using INCLOCK,OUTCLOCK,Memenab. With Address Control and OutData Registered. Please reply is anyone has any knownledge about how to overcome this matter. Thank you. Here is my code: use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity Rom3in1 is port ( RESET : in STD_LOGIC; INCLOCK : in STD_LOGIC; OUTCLOCK : in STD_LOGIC; MEMENAB : in STD_LOGIC; QR : out STD_LOGIC_VECTOR(7 DOWNTO 0); CLK : in STD_LOGIC; LOAD : in STD_LOGIC; ENABLE : in STD_LOGIC ); end Rom3in1; architecture Rom3in1_arch of Rom3in1 is SIGNAL S1: STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL S2: STD_LOGIC_VECTOR(7 DOWNTO 0); -- VHDL Module Generator component declarations component LPM_ROM generic ( Note: note := "ROM"; LPM_WIDTH: integer := 8; LPM_TYPE: string := "LPM_ROM"; LPM_WIDTHAD: integer := 3; LPM_FILE: string := "ROM.MIF"; LPM_ADDRESS_CONTROL: string := "REGISTERED"; LPM_OUTDATA: string := "REGISTERED"; LPM_HINT: string := "UNUSED" ); port ( ADDRESS : in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0); INCLOCK : in STD_LOGIC; OUTCLOCK : in STD_LOGIC; MEMENAB : in STD_LOGIC; Q : out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0) ); end component; component COUNTUP port ( CLK : in STD_LOGIC; RESET : in STD_LOGIC; ENABLE : in STD_LOGIC; COUNTOUT : out STD_LOGIC_VECTOR(2 DOWNTO 0) ); end component; component REG8_3 port ( CLK : in STD_LOGIC; D : in STD_LOGIC_VECTOR(7 DOWNTO 0); QR : out STD_LOGIC_VECTOR(7 DOWNTO 0) ); end component; begin -- VHDL Module Generator component instantiations U_REG8_3: REG8_3 port map (CLK, S2, QR); -- VHDL Module Generator component instantiations U_COUNTUP: COUNTUP port map (CLK, RESET, ENABLE, S1); -- VHDL Module Generator component instantiations U_LPM_ROM: LPM_ROM port map (S1, INCLOCK, OUTCLOCK, MEMENAB, S2); end Rom3in1_arch;Article: 38595
"Kevin Neilson" <kevin_neilson@removethis-yahoo.com> schrieb im Newsbeitrag news:gXY18.4397$HM2.40256@rwcrnsc52.ops.asp.att.net... > > There was a time before Nixie tubes? Yes, just a couple of years after the extinction of the dinosaurs ;-)) -- MfG FalkArticle: 38596
"Brad Eckert" <brad@tinyboot.com> schrieb im Newsbeitrag news:4da09e32.0201180903.7e4cf3f5@posting.google.com... > Okay, that's good for modeling. Will the free web-based tools tools > from Xilinx, Altera and Cypress synthesize a 128x32 ROM by fitting it Webpack (with XST as VHDL compiler): NO. -- MfG FalkArticle: 38597
newman5382@aol.com (newman) wrote in message news:<e6038423.0201180501.c52e394@posting.google.com>... > yuryws@optonline.com (Yury) wrote in message news:<fb9fd058.0201172014.12b797fa@posting.google.com>... > > Implemented 1/2 Band 51-tap FIR using Coregen + Foundation. > > Pre-synthesis simulation looks excellent, however when the filter is > > loaded into Spartan-II the output looks like complete random junk. All > > timing is met. > > > > Does anyone have a similar experience or an idea for a potential > > problem area? > > > > Thanks. > > I have not used this Coregen IP, but you mentioned that the > Pre-synthesis simulations look excellent. How about post PAR > simulations? One can also do an inbetween post PAR simulation without > the SDF if need be. The reason I mention this is maybe the > constraints need a little bit more work. > > Are you sure the digital input data is frequency limited to within > your > digital filter's specifications? > > Are you using DLL's?, they have min/max frequency and jitter > specifications. > > Newman I stimulate the pre-synthesis design with a certain input data stream. I use the same stream as an input to a tool called Elanix (used for signal processing). The pre-synthesis output of Xilinx and the output of Elanix agree clock for clock for 64K samples (which indicates to me that the design is correct). I am starting to suspect the descrepancy between the Coregen model of the FIR and its behavioral VHDL description provided by the same Coregen. I have to do the post routing functional and/or timing simulation, but I have not gotten to it yet. DLLs are rock solid, their jitter is minimal (could not affetct the spectrum). The frequency content of the input data is irrelevant, since I compare the output of the Xilinx filter to that of an independent filter simulator. Even if the data is out of band the output smaples still should agree. ThanksArticle: 38598
Kevin Neilson wrote:
> I don't understand how this delay wire worked... the transducer twisted the
> wire to create torsional pulses? How long was a pulse? How could you
> possible fit thousands of pulses in one wire and not have them die out?
I never used one, but I do remember seeing them in circuits
>
>
> When the pulses came out the end, were they amplified and recirculated into
> the ring? And then how did you find a particular byte? Was there some sort
> of framing?
>
> There was a time before Nixie tubes?
Yes, I had a frequency counter years ago that had bars with numbered windows.
Behind each was a neon bulb which would light up the correct digit. An
additional neon bulb lit up behind the range (Hz, kHz), and there was one
between each column to act as a decimal point. The display for a 59.703 Hz
input would look something like this:
9
Hz
7
5
3
* 0
Believe me, Nixie tubes were a big improvement. Durn thing weighed about 40
pounds, was a bit bigger than my PC and dimmed the lights when it turned on.
IIRC, it had 52 tubes in it, and it only measure up into the 100KHz or so
range. It is amazing how far we've come in less than 40 years!
>
>
> "Peter Alfke" <palfke@earthlink.net> wrote in message
> news:3C47AB75.E1C9332F@earthlink.net...
> > I was at Sweda cash registers, Swedish junior sister of Monroe, who loved
> > drums, so we first tried to use the delay line like a drum. But it was not
> > stable enough to pack it full, like a ring, as you do on a drum. So we
> > left a gap, and made sure the gap would neither grow nor shrink. It was a
> > stored instruction design, but the details are getting foggy...
> > Transistors were very expensive, and read-out was a real problem before
> > the advent of Nixie tubes. Makes you appreciate today's plethora of
> > solutions.
> >
> > Peter Alfke
> >
> > Eric Smith wrote:
> >
> > > Peter Alfke <peter.alfke@xilinx.com> writes:
> > > > Back in 1965 I was supposed to stuff much of the logic and all of the
> > > > memory for an electronic cash register into such a torsional delay
> > > > line.
> > >
> > > How do you stuff logic into the delay line?
> > >
> > > > We managed to squeeze in 15,000 bits and run that reliably,
> > >
> > > Quite impressive! What was the physical length of the delay line?
> > >
> > > I have a Monroe 990 calculator that stores only around 120 bits into a
> > > delay line made by NEC, and fails to do that reliably. I assume it was
> > > reliable back in 1971 though.
> > >
> > > The Friden seems to work reliably though. It was made in 1964, and
> > > stores around 280 bits. Actually more channel bits, because they
> > > use a strange encoding rather than straight binary.
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 38599Rick Filipkiewicz wrote: > Austin Lesea wrote: > > > > > The FPGA editor is not the real view of the chip (obviously). I do agree that it > > is all you need to construct a really high performance working design (we use it > > all of the time to verify features functions and specifications). FPGA companies make their money selling the parts and time-to-market...perhaps some revenue from the development tools, but mostly the parts. Whatever sells parts will be vigorously pursued and supported. Hand-tweak tools are not this. Synthesis-path tools are. It is a better play for them to push the synthesis tools than the hand-editing because, for the same performance, the synthesized design will take more silicon. This isn't necessarily selfish on their part, either, because the synthesis also typically achieves better time-to-market than the hand-edit. The objection can be raised that a good engineer can do a hand-tweak solution as fast a syntehsized one, but lets be fair...the caliber of engineer that can do a good hand-tweaked design is higher than most...definitely NOT the caliber that generates the most revenue for FPGA companies. They have to make the average joe designer productive in order to thrive. -- William Vollrath Senior Design Engineer LSI Logic, Inc. San Diego Design Center 16855 West Bernardo Drive, Suite #200 San Diego, CA 92127 Phone: 858-385-5072 Fax: 858-385-5001 email: william.vollrath@lsil.com
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z