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Hi
I am currently writing a MPEG-1 layer 1 audio decoder in VHDL.
I would like to implement the device on an Altera ACEX1K100 device that has
100 000 gates.
I can't decide whether to use fixed or floating point numbers. I managed to
download a FPU core from opencores.org, but it is written in verilog and I
would prefer something in VHDL. It also does not specify the number of gates
that it uses.
The calculations that I need to perform are not that complex.
The sample values in the MP3 file are in a 2's complement integer format.
The first thing that needs to be calculated is the requantized value:
s"= (2^nb / (2^nb -1))* ( s"' + 2-nb+1 )
where: s"' is the fractional number (from the MP3 file in a 2's
complement integer format),
s" the requantized value,
nb the number of bits allocated to samples in the subband.
The 2^nb calculation is easy as it just involves a shift.
The problem that I have is that the result of this formula is not an
integer.
This result is then scaled by multiplying it by a scalefactor, the value of
scale factor is also a real number that ranges between 2.00000000000000 and
0.00000120155435.
s'= factor * s".
where: s' is the rescaled value.
This is then used in a number of calculations involving mainly addition and
one cos (I can use a look up table for this) calculation.
Eventually just before the PCM result is produced there is another scaling
process using values between about 1.144989014 & -1.138763428
Is it difficult to do this sort of thing in fixed point arithmetic? How do I
go about doing this, i.e. what is the best way to represent real numbers in
a fixed point environment?
Any help in tackling this problem will be greatly appreciated.
Thanks
Andrew
Article: 34876Hi, I'm trying to do my first examples with FPGA's and I am running into some problems with a Xilinx VirtexE in a demo board. I want to make a counter and to display the count in a 7-segment display of the board. The clock for this counter schould be a press-button of the board. The problem is that the button is physically connected to the pin P95 of th FPGA and the Xilinx tool (ISE 3.1) doesn't allow me to place this input signal in this pin. If I constrain this signal to this pin I get the following error: ERROR:MapLib:93 - Illegal LOC on symbol "clk.PAD" (pad signal=clk) or BUFGP symbol "clk_BUFGP" (output signal=clk_BUFGP), IPAD-IBUFG should only be LOCed to GCLKIOB site. I guess that it is not possible to chose whatever pin for a clock signal, but since this button is physicaly conected to this pin, i can not change it. How could I overcome this? I looked in the documentation trying to find out which pins can be used as clock signals, but I didn't find it. The ISE 3.1 tutorial from Xilinx don't say anything about it neither. Where could I find it? Thanks in advance, Paul.Article: 34878
It's OK I found a solution, easier than I first thought. I used a counter (clocked truth_table) that was clocked 20 times (10Hz clock), on the 20th clock the signal delay was set to 0. I then adjusted the logic equations so that wherever there was a (switch) it was changed to (switch & !delay). Also I used the asynchronus reset via the !switch. delay.ar = !switch; // Resets the counter when the switch is off. sorry to post unnecessary topics but as soon as the new spec came in I was really lost in how it could be achieved, my initial post was planned as a backup incase I couldn't get anywhere! MattArticle: 34879
We've just started using the Xilinx Webpack ISE software, I find the XST synthesis reasonably fast, although I got a warning in Modelsim today whilst doing a Post-Synthesis simulation that it's performance would be 'adversly affected' because my design used over 700 (approx. cant remember!) statements, and it was significantly slower than usual? Is this the same in the bought version, have I only got a cut-down version for free? MattArticle: 34880
"Andrew Gray" <andrewgray@iafrica.com> wrote: >Hi > >I am currently writing a MPEG-1 layer 1 audio decoder in VHDL. > >I would like to implement the device on an Altera ACEX1K100 device that has >100 000 gates. > >I can't decide whether to use fixed or floating point numbers. ... Floating point would be most probably too big and too slow. The solution I'd suggest is to do a fractional implementation. I don't think audio sampling requires the full dynamic range of floating point so you should be able to use a fractional integer implementation. Just add a couple of bits for extra margin after deciding what your required dynamic range is. Muzaffer DSP implementations using FPGA http://www.dspia.comArticle: 34881
dottavio@ised.it (Antonio) wrote in message news:<fb35ea96.0109102259.2bd641a1@posting.google.com>...
> Good Morning
> I'm designing a QPSK Modulator using an NCO, do you know where I can
> found some documentation about a schema of it with no multiplier and
> no NCO, someone tried to explain it to me, but until now I didn't
> understand how it works and so I can't produce a valid schema for it.
> Thanks in any case ...
The NCO generates a sin/cos pair to multiply with the incoming complex
symbols. If the carrier frequency is chosen correctly (for example
select a carrier that is n*Fsymbol/4) the sin/cos pair is just (+-1)
[sin(0), cos(0)] = [0, 1]
[sin(pi/2), cos(pi/2)] = [1, 0]
and so on..
Each of the four possible values for the carrier phasor results in
either sin=0 or cos=0. The actual implementation for a 1/4*Fbaud
modulator looks like this:
a[k] ---------->[X]---->A[k]
^ \
| \
+1,-1,+1,-1, .. -+ >---> Output stream A[0]B[0]A[1]B[1] ..
| /
V /
b[k] ---------->[X]---->B[k]
Article: 34882Paulo Valentim wrote: > Can any one explain me how to interpret this timing report generated by > LeonardoSpectrum. > > My doubt is : because I specified a clock of 40MHz, I don't understand why > it says that I can use up to 68.5 MHz (I think) but with a negative slack. > > ============================================== > **************************************** > Clock Frequency Report > **************************************** > > Clock : Frequency > ------------------------------------ > CLK : 68.5 MHz > > Critical path #1, (path slack = -5.1): This is a static timing report based on an average placement. Your design exceeds your requirements at this point, but you won't know for sure until you run the vendor specific static timer after you do an actual placement. The 68.5 MHz is the highest clock frequency that will still guarantee register to register setup/hold times for this average placement. Slack time has to do with input delays not register to register margins. --Mike TreselerArticle: 34883
M Pedley wrote: > It's OK I found a solution, easier than I first thought. > > I used a counter (clocked truth_table) that was clocked 20 times (10Hz > clock), on the 20th clock the signal delay was set to 0. I then > adjusted the logic equations so that wherever there was a (switch) it > was changed to (switch & !delay). Also I used the asynchronus reset > via the !switch. > > delay.ar = !switch; // Resets the counter when the switch is off. > > sorry to post unnecessary topics but as soon as the new spec came in I > was really lost in how it could be achieved, my initial post was > planned as a backup incase I couldn't get anywhere! > > Matt Matt, Now you have found a solution in ABEL I'd strongly suggest you move on to Verilog/VHDL as your design language if you possible can. Its much better supported & you have a whole NG - comp.lang.verilog/vhdl - to trawl for ideas & answers. ABEL was good in its day but the world moves on ...Article: 34884
Rick Filipkiewicz wrote: > > M Pedley wrote: > > > It's OK I found a solution, easier than I first thought. > > > > I used a counter (clocked truth_table) that was clocked 20 times (10Hz > > clock), on the 20th clock the signal delay was set to 0. I then > > adjusted the logic equations so that wherever there was a (switch) it > > was changed to (switch & !delay). Also I used the asynchronus reset > > via the !switch. > > > > delay.ar = !switch; // Resets the counter when the switch is off. > > > > sorry to post unnecessary topics but as soon as the new spec came in I > > was really lost in how it could be achieved, my initial post was > > planned as a backup incase I couldn't get anywhere! > > > > Matt > > Matt, > > Now you have found a solution in ABEL I'd strongly suggest you move on to > Verilog/VHDL as your design language if you possible can. Its much better > supported & you have a whole NG - comp.lang.verilog/vhdl - to trawl for > ideas & answers. > > ABEL was good in its day but the world moves on ... PLD HDL languages have similarities with Microcontroller languages. ABEL/CUPL are at the assembler end of the scale ( but rather smarter than assembler, more like High Level Assembler ), and Verilog/VHDL are more similar to C/Ada. Anyone that advocates using only ASM, or only C, is restricting their tool set and/or target devices. We do a lot of coding in CUPL ( similar to ABEL ), and from the output examples I have seen from VHDL code, it can be markedly less efficent, and more tool-bug prone. We achieve packing and strucures that are unsupported via VHDL, and would be possible, but close to unreadable in schematic. That said, these are SPLD/CPLD designs, and I would not use CUPL for a soft-core microcontroller, for example. I also know designers who trialed VHDL, and moved to AHDL ( Altera's HDL, an ABEL derivative ), because it was more productive. Jim G.Article: 34885
"Andrew Gray" <andrewgray@iafrica.com> writes: > Hi > > I am currently writing a MPEG-1 layer 1 audio decoder in VHDL. > > I would like to implement the device on an Altera ACEX1K100 device that has > 100 000 gates. > > I can't decide whether to use fixed or floating point numbers. I managed to > download a FPU core from opencores.org, but it is written in verilog and I > would prefer something in VHDL. It also does not specify the number of gates > that it uses. > Andrew, take a look at MAD: http://www.mars.org/home/rob/proj/mpeg/ It does not use floating point operations yet it produces good quality sound. I know that it is used on machines based on the StrongARM uP, which lacks a FP unit. Best, -ArrigoArticle: 34886
Hi,
I'm using RAM description in my design which maps on the BlockRAM in Xilinx
Spartan-II. Is there any way how to initialize this RAM with my own values?
I'm using WebPACK 3.3.
Thanks
Jan
___________________________
j.pech@sh.cvut.cz
+420 (723) 760802
ICQ: 56431283
Article: 34887Jan Pech wrote: > Hi, > I'm using RAM description in my design which maps on the BlockRAM in Xilinx > Spartan-II. Is there any way how to initialize this RAM with my own values? > I'm using WebPACK 3.3. > > Thanks > Jan > > ___________________________ > j.pech@sh.cvut.cz > +420 (723) 760802 > ICQ: 56431283 There is a thing called ``INIT'' you can apply through the user constraints file (UCF). To get a description download the 3.3i `Libraries Reference Guide' from the Xilinx site. Its decribed in the ``Attributes, Constraints, and Carry logic'' section. The other possibility is to use JBits to hack the bitstream.Article: 34888
That's right. The Modelsim XE software is limited in the number of lines of code you can simulate. If you exceed that limit you can still simulate but its about 50 times slower. If you buy PE for $5000 you will have no line limitations. -- Pete Dudley Arroyo Grande Systems "M Pedley" <Pedley@talk21.com> wrote in message news:b34821cd.0109120935.43de1a06@posting.google.com... > We've just started using the Xilinx Webpack ISE software, I find the > XST synthesis reasonably fast, although I got a warning in Modelsim > today whilst doing a Post-Synthesis simulation that it's performance > would be 'adversly affected' because my design used over 700 (approx. > cant remember!) statements, and it was significantly slower than > usual? Is this the same in the bought version, have I only got a > cut-down version for free? > > MattArticle: 34889
Apparently unused Price for quick turnover Tony Stein Alex VaArticle: 34890
Not practical for lots of data. I don't have the books with me, but in essence you need to generate the BRAMs withe CoreGen, then wite a program to hack your init stuff into something like a .coe file(s). This will then get you everything you want through both simulation and synthesis. Health warning - this is from memory - look it up in the help files. "Rick Filipkiewicz" <rick@algor.co.uk> wrote in message news:3B9FEA30.4E6811BF@algor.co.uk... > > > Jan Pech wrote: > > > Hi, > > I'm using RAM description in my design which maps on the BlockRAM in Xilinx > > Spartan-II. Is there any way how to initialize this RAM with my own values? > > I'm using WebPACK 3.3. > > > > Thanks > > Jan > > > > ___________________________ > > j.pech@sh.cvut.cz > > +420 (723) 760802 > > ICQ: 56431283 > > There is a thing called ``INIT'' you can apply through the user constraints > file (UCF). To get a description download the 3.3i `Libraries Reference Guide' > from the Xilinx site. Its decribed in the ``Attributes, Constraints, and Carry > logic'' section. > > The other possibility is to use JBits to hack the bitstream.Article: 34891
I have try it in MAXPLUS, it works very well. On Tue, 22 May 2001 07:19:49 -0700, Martin <martin.t@yours.com> wrote: >Hi, > >Does anybody know what can be wrong with that code ? > >--- Code starts here --- > >entity DownCounter is >generic( PresetValue: integer := 1023 ); >port( Reset: in std_logic; Clk: in std_logic; Zero: out std_logic ); >end DownCounter; > >architecture Behaviour of DownCounter is >begin >Controller: process( Reset, Clk ) > variable state: integer range 0 to PresetValue; >begin > if( Reset = '1' ) then > state := PresetValue; > elsif( Clk'event and Clk = '0' ) then > if( state = 0 ) then > state := PresetValue; > else > state := state - 1; > end if; > end if; > > if( state = 0 ) then > Zero <= '1'; > else > Zero <= '0'; > end if; >end process Controller; >end Behaviour; > >--- End of code ---- > >I use the Synplify 6.1.3 to synthesis and simulation after that operation is OK. The problem is in simulation after the Place&Route for Xilinx Spartan2 150k + Service Pack 7, which gives all 'X' signals. What can be wrong ? > >Regards, >MartinArticle: 34892
Hi, can anybody help me? How to convert variable to std_logic_vector, integer to std_logic_vector. .......Article: 34893
Wrong group. Try comp.lang.vhdl
OK. Just this once...
------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
function i2slv ( N,L: integer ) return std_logic_vector is
variable vec: std_logic_vector(L-1 downto 0);
begin
vec := std_logic_vector(to_signed(n,L));
return vec;
end;
------------------------------------------
"cnspy" <cnspy@sohu.com> wrote in message
news:7f40qt0m4qtbpeo0qkbphtbecc3fpvlks2@4ax.com...
> Hi, can anybody help me?
> How to convert variable to std_logic_vector, integer to
> std_logic_vector. .......
Article: 34894Hi, I only have a 20MHz clock of my chip. Now I want to write some codes to control the eeprom. The /OE and /WR signals should be 20MHz too. But it should have some delay(12---18ns) between them. What should I do.Article: 34895
Attempting to make fixed asynchronous delays in an FPGA is evil. Banish the thought. Straight answer: Instead you need to use your master clock in one of three ways. 1) Accept that it will take multiple clock cycles to complete an access to your EEPROM. On each of the two or three clocks needed, you change the state of one of the control signals at a time according to your EEPROM data sheet. 2) Get fancy and use a negative (falling) edge triggered flipflop to generate one of the intermediate signals approximately halfway through your clock cycle. This can have repurcussions on the amount of time the Xilinx tools can take to deliver a timing analysis, and lays you open to sensitivity to the duty cycle of your master clock. 3) Actually clock your FPGA at 40MHz and use two clocks to perform the operations that must look like they are taking place at 20MHz, and one 40MHz clock to do the intermediate signal generation where necessary. Suspicious answer: Depending on the kind of EEPROM you are using, the relationship between nOE and nWE might not be as important as you believe. Reread the EEPROM datasheet carefully to see if nWE might override nOE. If the EEPROM is using bidirectional data, you also need to keep an eye on how you are going to avoid contention on who is allowed to do the driving at any given time. -- Posted using Nographer - News in your Browser http://www.nographer.com - free, open source, and smartArticle: 34896
cnspy wrote: > > Hi, can anybody help me? > How to convert variable to std_logic_vector, integer to > std_logic_vector. ....... Checkout VHDL FAQ http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#integer_bit_vector SrinivasanArticle: 34897
Hi Jan, > Is there any way how to initialize this RAM with my own values? yes, this is easily possible. By using the INIT_xx attributes, you may specify initial values in hex. The VHDL code snipped below demonstrates this, the code was tested with WebPACK 3.3. Hope this helps, best regards Felix _____ Dipl.-Ing. Felix Bertram Trenz Electronic Duenner Kirchweg 77 D - 32257 Buende Tel.: +49 (0) 5223 49 39 755 Fax.: +49 (0) 5223 48 945 Mailto:f.bertram@trenz-electronic.de http://www.trenz-electronic.de ---------------------------------------------------------------------------- ---- library IEEE; use IEEE.STD_LOGIC_1164.all; library UNISIM; use UNISIM.vcomponents.all; entity dpram256x32 is port ( clka: IN std_logic; addra: IN std_logic_VECTOR(7 downto 0); dia: IN std_logic_VECTOR(31 downto 0); ena: IN std_logic; wea: IN std_logic; -- clkb: IN std_logic; addrb: IN std_logic_VECTOR(7 downto 0); dob: OUT std_logic_VECTOR(31 downto 0); enb: IN std_logic); end dpram256x32; ---------------------------------------------------------------------------- ---- architecture bhv of dpram256x32 is attribute INIT_00: string; attribute INIT_01: string; attribute INIT_02: string; attribute INIT_03: string; attribute INIT_04: string; attribute INIT_05: string; attribute INIT_06: string; attribute INIT_07: string; attribute INIT_08: string; attribute INIT_09: string; attribute INIT_0A: string; attribute INIT_0B: string; attribute INIT_0C: string; attribute INIT_0D: string; attribute INIT_0E: string; attribute INIT_0F: string; attribute INIT_00 of U1: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_01 of U1: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_02 of U1: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_03 of U1: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_04 of U1: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_05 of U1: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_06 of U1: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_07 of U1: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_08 of U1: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_09 of U1: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_0A of U1: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_0B of U1: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_0C of U1: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_0D of U1: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_0E of U1: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_0F of U1: label is "0000000000000000000000000000000000000000000000000000000000000000"; constant zeroC: STD_LOGIC:= '0'; signal zero: STD_LOGIC; signal zerobus: STD_LOGIC_VECTOR(15 downto 0); begin zero <= zeroC; zerobus<= (others=> zeroC); U1: RAMB4_S16_S16 port map( CLKA=> clka, RSTA=> zero, ADDRA=> addra, DIA=> dia(15 downto 0), DOA=> open, ENA=> ena, WEA=> wea, CLKB=> clkb, RSTB=> zero, ADDRB=> addrb, DIB=> zerobus, DOB=> dob(15 downto 0), ENB=> enb, WEB=> zero); end bhv; ---------------------------------------------------------------------------- ---- -- end of fileArticle: 34898
Thanks I am busy looking at MAD. Does anyone know how the representation of numbers is done? There is some type of scaling done, for example: 1.33333333333333 is represented as 0x15555555 and 1.06666666666667 is represented as 0x11111111 and 1.00003051850948 is represented as 0x10002000 Thanks Andrew "Arrigo Benedetti" <arrigo@vision.caltech.edu> wrote in message news:q03d5sawjv.fsf@vision.caltech.edu... > "Andrew Gray" <andrewgray@iafrica.com> writes: > > > Hi > > > > I am currently writing a MPEG-1 layer 1 audio decoder in VHDL. > > > > I would like to implement the device on an Altera ACEX1K100 device that has > > 100 000 gates. > > > > I can't decide whether to use fixed or floating point numbers. I managed to > > download a FPU core from opencores.org, but it is written in verilog and I > > would prefer something in VHDL. It also does not specify the number of gates > > that it uses. > > > > Andrew, take a look at MAD: > > http://www.mars.org/home/rob/proj/mpeg/ > > It does not use floating point operations yet it produces good quality > sound. I know that it is used on machines based on the StrongARM > uP, which lacks a FP unit. > > Best, > -ArrigoArticle: 34899
Examine mad-0.13.0b\libmad\fixed.h, where you will see the following comment: Some kind of GPLed effort to produce a VHDL version of the guts of libmad would be a very honourable endeavour. /* * Fixed-point format: 0xABBBBBBB * A == whole part (sign + 3 bits) * B == fractional part (28 bits) * * Values are signed two's complement, so the effective range is: * 0x80000000 to 0x7fffffff * -8.0 to +7.9999999962747097015380859375 * * The smallest representable value is: * 0x00000001 == 0.0000000037252902984619140625 (i.e. about 3.725e-9) * * 28 bits of fractional accuracy represent about * 8.6 digits of decimal accuracy. * * Fixed-point numbers can be added or subtracted as normal * integers, but multiplication requires shifting the 64-bit result * from 56 fractional bits back to 28 (and rounding.) * * Changing the definition of MAD_F_FRACBITS is only partially * supported, and must be done with care. */ -- Posted using Nographer - News in your Browser http://www.nographer.com - free, open source, and smart
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