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That's why I asked. The errata sheet says that "the variable shift mode of the DCM
Fine Phase Shift feature is not available in these devices". Your post asked if
anyone needed variable phase shift. Thanks for the clarification.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 35026
Right. I missed the fact he was looking at 10x18 not 18x18. I think he'll still
need to use the pipeline register mode and/or put registers before and after the
multiplier though.
Austin Lesea wrote:
> Ray,
>
> For 10X18, he should be able to hit the desired speed without hand placing....
>
> Austin
>
> Ray Andraka wrote:
>
> > To get the 125 MHz, you'll need to use the pipeline registers. With 3.1 that
> > means using FPGA editor. You'll also need to precede and follow the multiplier
> > immediately with CLB registers. You may find you need to place those added
> > registers by hand so that they are in the rignt places to get on the direct
> > connects to the multiplier.
> >
> > pete dudley wrote:
> >
> > > Xilinx FAE Jason Moore helped me on this one. You can directly instantiate a
> > > MULT18X18S to get the Synchronous multiplier. The core generator does not
> > > give you that primitive. Speed files are still bouncing around on the
> > > Tmultck parameter but they should run 125MHz especially since I only need
> > > 10x18 out of them.
> > >
> > > --
> > > Pete Dudley
> > >
> > > Arroyo Grande Systems
> > >
> > > "pete dudley" <padudle@spinn.net> wrote in message
> > > news:tpqon9s22vare9@corp.supernews.com...
> > > > Hello All,
> > > >
> > > > Does anyone know whether there is really an internal pipeline register
> > > > inside the Virtex II embedded multiplier?
> > > >
> > > > I have an application that is very multiplier intensive and I need to run
> > > at
> > > > 125MHz. Without internal pipelining it is just about impossible to meet
> > > this
> > > > clock rate. I have been told there is a register inside those multipliers
> > > > but that they are not supported in the 3.1i tools. I received my 4.1i
> > > tools
> > > > today and tried to turn on the pipeline register by specifying maximum
> > > > pipelining in the core generator but the timing report still indicates no
> > > > internal pipelining.
> > > >
> > > > When I look at the multiplier blocks using FPGA Editor I can see that it
> > > has
> > > > a clock input. What's the story?
> > > >
> > > > Thanks,
> > > >
> > > > --
> > > > Pete Dudley
> > > >
> > > > Arroyo Grande Systems
> > > >
> > > >
> > > >
> >
> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 35027Look it up in Synplicity help, but what you need is something like this: attribute syn_noclockbuf : boolean; attribute syn_noclockbuf of ClkA : signal is true; attribute syn_noclockbuf of ClkB : signal is true; "Richard Wilkinson" <richard.wilkinson@csr.com> wrote in message news:587eaa3a.0109180331.71484f12@posting.google.com... > Hi All, > > I am having a problem with Synplify inferring BUFG cells when it has > actually run out of BUFGs to add. In this case, I am using Synplify > 6.1.3 and have instantiated a BUFGDLL and a single BUFG. Obviously > this takes up 2 of the 4 BUFGs in the Virtex2E that I'm using, but > then Synplify infers 3 more BUFGs as it decides that I have only > instantiated 1 BUFG in my code. > > I have tried usign Synplify 6.2.4 but that actually synthesises some > of my logic incorrectly. > > Is this BUFG problem a bug with Synplify 6.1.3 or can Synplify just > not count to 4 properly? > > Has anyone else had this problem? > > Cheers, > > RichArticle: 35028
Hi,
you can inferred it in your code :
Declaration :
----- Component IBUFG -----
component IBUFG
-- synopsys
--
generic(TimingChecksOn: Boolean := ChecksTiming); -- For Timing
Simulation
-- synopsys
--
port(
O : out STD_ULOGIC;
I : in STD_ULOGIC);
end component;
Mapping :
-- BUFG Mapping : UBUFG1
UBUFG1 : BUFG
port map (
I => CLK_IN,
O => CLK_OUT
);
I have already use this, it's a part of a real design, it works fine
Arnaud.
"Michael Strayer" <michael.strayer@sri.com> a écrit dans le message news:
9nr5gl$m0l$1@unix.sri.com...
> Hello,
> I'm trying to use Xilinx's Webpack software to implement
> a design on a Spartan II. Part the the design is a bitclock
> generator that divides the system clock down to two other
> freq's. When I try to use these clocks in other parts of the
> design Webpack complains that I am routing clocks using
> non-dedicated resources.
>
> I've read the section in the online help about assigning
> signals to global clock buffers using the attribute statement
> but when I try this I get a message stating the BUFG is an unknown
> attribute.
>
> How do I go about assigning an internally generated signal to
> a global clock net??
>
> Thanks
> Mike Strayer
>
>
>
Article: 35029On 18 Sep 2001 04:32:00 -0700, richard.wilkinson@csr.com (Richard Wilkinson) wrote: >Hi All, > >I am having a problem with Synplify inferring BUFG cells when it has >actually run out of BUFGs to add. In this case, I am using Synplify >6.1.3 and have instantiated a BUFGDLL and a single BUFG. Obviously >this takes up 2 of the 4 BUFGs in the Virtex2E that I'm using, but >then Synplify infers 3 more BUFGs as it decides that I have only >instantiated 1 BUFG in my code. > >I have tried usign Synplify 6.2.4 but that actually synthesises some >of my logic incorrectly. > >Is this BUFG problem a bug with Synplify 6.1.3 or can Synplify just >not count to 4 properly? > >Has anyone else had this problem? Try: attribute syn_noclockbuf of clk_sig : signal is true; Regards, Allan.Article: 35030
Dear All : Does anyone knows how to increase the routing delay for a particular net in XILINX FPGA editor ? There is a constraint for max routing delay, but no constraint for min routing delay. Thanks very much for your help ! Best regards, Lin CHArticle: 35031
Hi Chris, Are you looking to retarget the Spartan to an ASIC yourself, or use an ASIC house to do a conversion from the netlist? It's worth remembering that if you use a vendor to convert the FPGA to ASIC for you, if the FPGA price comes down over the next couple of years, most likely the ASIC pricing will come down accordingly and remain much cheaper than the FPGA. In my experience, at 100k, the pricing that you get from the FPGA vendors is not much better than for say 5 - 10k volumes, so I don't think you will get a cheap price from them. I've used a couple of conversion vendors before, Flextronics Semiconductor in the UK seem to be the biggest players and will turn around a quote pretty quickly, so I suggest you contact them. Hope this helps! "rAinStorms" <cburton@ihug.co.nz> wrote in message news:9ns9ai$6q4$1@lust.ihug.co.nz... > Hi There, > > I am trying to put together a proposal for ASIC development using an > EP20K200 or similar style device as the development prototyping platform. > This is part of Alteras Apex II range.... 100k gates plus 53kbits SRAM in a > 144pin TQFP. > > However the actual vendor or family is not that important, as long as it's > similar in spac. > > Looking at the volume pricing changes in FPGA technology over the last five > years I am concerned that in my 50-100k / year volume requirements that in > 18-24 months the price of these devices will come down to levels where doing > an ASIC is pointless for this type of device. > > Can anyone out there give me any feedback pertaining to forward pricing > models they may have seen from FPGA vendors out there .... you can strip > company names or whatever if needed. I am looking for an idea of how the > price of a device with the capability I indicated will change over the next > 2 years. Note that the devices are I/O ring limitted right now ... and only > need approx 90 I/O in a 144 Pin TQFP or 1mm BGA style device. > > Any help appreciated! > > Chris > >Article: 35032
Please be advised that the deadline for paper submission to FPGA'2002
is now less than two weeks away. We are planning an exciting technical
and social program for this event, including a trip to the
Monterey Aquarium. Please consider submitting a paper in the area of
field-programmable gate arrays or reconfigurable computing to the
symposium. A full list of topic areas and submission directions can be
found at the symposium web site.
http://www.ecs.umass.edu/ece/fpga2002
---------------------------------------------------------------------
FPGA 2002: Call for Papers
Tenth ACM International Symposium on Field-Programmable Gate Arrays
Monterey Beach Hotel
Monterey, California
February 24-26, 2002
Submissions due: September 28, 2001
web site: http://www.ecs.umass.edu/ece/fpga2002
Authors are invited to submit English language PDF of their paper
(12 pages maximum) and panel proposals by September 28, 2001 by
E-mail to fpga2002@xilinx.com. Notification of acceptance will
be sent by November 21, 2001.
Address questions to:
Steve Trimberger, Program Chair, FPGA 2002
Email: fpga2002@xilinx.com
Article: 35033Minimum propagation delays can end up much shorter than the "worst case" numbers used by the Timing Analyzer. A minimum routing delay of 5nS, for instance, that's valid for all parts and at cold temperatures and high voltages might produce 10nS, 15nS... even more delay than you'd expect in a slower batch at higher temperature and lower voltage. If you want to *match* delays, there's a constraint to keep the skew between signals to a minimum. If you want to have a signal moved by a half cycle, quarter cycle or such consider using the DLLs to provide a clock that's some multiple of 90 degrees out of phase to resynchronise your "delayed" signal to the specified point in time. If you can use a Virtex-II device, the constraints on the phase delay are entirely up to you. The DCM can provide a fixed phase shift per your specifications. You just need to apply good design techniques to guarantee the system flow properly. Chih-Hsun Lin wrote: > Dear All : > Does anyone knows how to increase the routing delay for a particular net > in XILINX FPGA editor ? There is a constraint for max routing delay, but > no constraint for min routing delay. > > Thanks very much for your help ! > > Best regards, > Lin CHArticle: 35034
[ Sorry for the length. Should be an easy question nevertheless. ]
Hi,
I'm having problems mixing and matching VHDL and EDIF source files in
FPGA Compiler II. Basically, I want to instantiate a RAM block that
has been generated by the Xilinx CoreGen tool in a VHDL description.
I can't get it to work, and from the documentation that I could find,
it should just work, without any tricks. I suspect there is something
wrong with buses, since single-bit signals connect fine, while buses
don't.
This is my first encounter with stuff like this, so I'm probably just
being dense.
I managed to instantiate a RAMB8_S8 primitive just fine, but no luck
with the EDIF netlist from the Core Generator.
Going back a step, I tried to incrementally synthesize a toy design
from the inside out, in two steps, which didn't work either. (Even if
this is not helpful to get the generated cores to work, I nevertheless
want to do incremental synthesis anyway, so I'd like to concentrate on
this toy design first.) Maybe someone here can help me find my way
out of the forest...
What I did was this. I wrote a small VHDL description of a two input
OR gate:
-- File inner.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity inner is
port (
input : in std_logic_vector (1 downto 0);
output : out std_logic);
end inner;
architecture rtl of inner is
begin -- rtl
output <= input(0) or input(1);
end rtl;
Then I created a new FPGA Compiler II project, added "inner.vhdl" to
it, analyzed the sources, created an implementation for the "inner"
component, optimized it, and exported a netlist, "inner.edf" (see end
of article). For "Bus style", I chose EXPAND.
Next, I wrote a VHDL description that was going to use the inner
block:
-- File outer.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity outer is
end outer;
architecture rtl of outer is
component inner
port (
input : in std_logic_vector (1 downto 0);
output : out std_logic);
end component;
signal stimuli : std_logic_vector (1 downto 0);
signal result : std_logic;
begin -- rtl
stimuli <= ('0', '1');
comp: inner
port map (
input => stimuli,
output => result);
end rtl;
I created a second FPGA Compiler II project, and added outer.vhdl to
it. I also added "inner.edf", the netlist exported above. The files
could be analyzed all right. When I created an implementation for the
"outer" component of the "outer.vhdl" file, I got the following
warnings:
Messages for outer
Warnings
========
FPGA-LINK-7 (1 Occurrence)
Warning: The pin 'input' of 'outer/comp' has no corresponding
port on the design 'inner'. Not linked.
FPGA-LINK-2 (1 Occurrence)
Warning: Cannot link cell 'outer/comp' to its reference design
'inner'.
As you can see, the "output" was connected, but the "input" was not.
I assume this has something to do with buses, but I don't know how to
diagnose this further.
I got the same kind of warnings when trying to merge the CoreGen
generated EDIF into a thin VHDL wrapper (that did some muxing of the
data buses). All single bit signals were connected, I think, but the
buses were not.
What's going on? I'm grateful for any hints.
Here is "inner.edf", just in case:
(edif inner
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap
(keywordLevel 0)
)
(status
(written
(timeStamp 2001 9 18 17 53 49)
(program "FPGA Compiler II"
(version "3.6.0.6613")
)
(author "mvo")
)
)
(external VIRTEXE
(edifLevel 0)
(technology
(numberDefinition)
)
(cell IBUF
(cellType GENERIC)
(view Netlist_representation
(viewType NETLIST)
(interface
(port O
(direction OUTPUT)
)
(port I
(direction INPUT)
)
)
)
)
(cell LUT2
(cellType GENERIC)
(view Netlist_representation
(viewType NETLIST)
(interface
(port I0
(direction INPUT)
)
(port I1
(direction INPUT)
)
(port O
(direction OUTPUT)
)
)
)
)
(cell OBUF_S_12
(cellType GENERIC)
(view Netlist_representation
(viewType NETLIST)
(interface
(port O
(direction OUTPUT)
)
(port I
(direction INPUT)
)
)
)
)
)
(library DESIGNS
(edifLevel 0)
(technology
(numberDefinition)
)
(cell inner
(cellType GENERIC)
(view Netlist_representation
(viewType NETLIST)
(interface
(port
(rename input_1 "input<1>")
(direction INPUT)
)
(port
(rename input_0 "input<0>")
(direction INPUT)
)
(port output
(direction OUTPUT)
)
)
(contents
(instance
(rename C_input_1 "C_input<1>")
(viewRef Netlist_representation
(cellRef IBUF
(libraryRef VIRTEXE)
)
)
)
(instance
(rename C_input_0 "C_input<0>")
(viewRef Netlist_representation
(cellRef IBUF
(libraryRef VIRTEXE)
)
)
)
(instance C_output
(viewRef Netlist_representation
(cellRef OBUF_S_12
(libraryRef VIRTEXE)
)
)
)
(instance C3
(viewRef Netlist_representation
(cellRef LUT2
(libraryRef VIRTEXE)
)
)
(property lut_function
(string "(I0 + I1)")
)
(property INIT
(string "E")
)
(property EQN
(string "(I0 + I1)")
)
)
(net
(rename N_input_1 "N_input<1>")
(joined
(portRef O
(instanceRef C_input_1)
)
(portRef I1
(instanceRef C3)
)
)
)
(net
(rename N_input_0 "N_input<0>")
(joined
(portRef O
(instanceRef C_input_0)
)
(portRef I0
(instanceRef C3)
)
)
)
(net N_output
(joined
(portRef I
(instanceRef C_output)
)
(portRef O
(instanceRef C3)
)
)
)
(net
(rename input_1 "input<1>")
(joined
(portRef I
(instanceRef C_input_1)
)
(portRef input_1)
)
)
(net
(rename input_0 "input<0>")
(joined
(portRef I
(instanceRef C_input_0)
)
(portRef input_0)
)
)
(net output
(joined
(portRef O
(instanceRef C_output)
)
(portRef output)
)
)
)
)
)
)
(design inner
(cellRef inner
(libraryRef DESIGNS)
)
(property PART
(string "V1000E-BG560-6")
)
)
)
--
Marius Vollmer AG Datentechnik / E-Technik
Tel: +49-231-755-3036 Universität Dortmund
Fax: +49-231-755-3251 Otto-Hahn-Str.4
http://www-dt.e-technik.uni-dortmund.de 44221 Dortmund, Germany
Article: 35036I am looking for sample or reference designs, written in C, to benchmark the Celoxica tools against the same or similar designs done in an HDL. Anyone have any suggestions or ideas? Know of any free cores out there that are done in C? C code for DES or SHA would be great. I know Celoxica has done DES in C, but I am looking for something I can get my hands on. Thanks! Tom --- Tom Curran tomcurran@rcsis_dot_comArticle: 35037
emanuel stiebler wrote: > Rick Filipkiewicz wrote: > > > > One of the little problems might be needing a $12 EEPROM for a $30 FPGA > > [24-off prices from the NuHorizons site]. If Xilinx could apply to the serial > > PROMs the same bang/buck technology that's moved us from the 3K series to > > Virtex-2 ... > > I really agree. That's the most annoying part about the xilinx FPGAs. > Like DEC alpha running on core memory ;-) > > cheers ... or running your family car on perfume.Article: 35038
Antonio wrote:
> Hy Ray,
> again some question, some mounth ago, I ask to you about what's better
> for a Cordic NCO, to start with I = 1 and Q = 0 or to start with I =
> 0.60725 and Q = 0 , you suggest me this second option, I implement
> both and in the first case I have SFDR = 65dBc and in the second case
> instead I've SFDR = 58dBc but I can also avoid using the two
> multipliers to reduce the result, You suggest me to use the second
> configuration with 15 bits then truncated to 12 but I'm implementing
> an Unrolled Cordic, this means that I've to use all adders at 15 bits
> inputs instead of 12 and just truncate at the output of the COrdic ??
Yes. The first couple iterations always have zero in the lsbs, so they
can be optimized out.
Is the CORDIC related to your QPSK modulator? If so, and you design the
modulator such that the
sample rate and IF frequency are related, you can reduce the logic
considerably since there is a very
limited set of rotation angles to deal with. This reduces to multiplying
by -1,1,or 0 if the sample freq is
exactly 4x the local osc. freq. If you need to tune it, then the CORDIC
makes sense, as it allows the
Fo to be unrelated to Fs. You may need to do some systems level design
before you dive into the
hardware design.
>
>
> Thanks ...
>
> Antonio D'Ottavio
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 35039How do I prevent Synplify from optimizing away my attempts to replicate logic? For the following code, synplify will merge the two instances of Shift into the same net: wire [1:0] Shift /* synthesis syn_keep=1 */; assign Shift[0]= Sending & !Stall | !Ready; // assign Shift[1]= Sending & !Stall | !Ready; // Replicated Also, is there some way to get synplify to print a message when it encounters an attribute? Otherwise, there's no way to tell if the attribute has an error that causes it to not be recognized as an attribute.Article: 35040
hitajian wrote: > > 1.Does anybody who is using HDL Design Series developed by Mentor > Graphics face the following case? I encounter it recently. > I once tried to call megafunction wizard in HDS directly. However, An alternative to wizards is synthesis. The counter and compare functions you mention can also be inferred from a few lines of hdl code by synplify or leo. --Mike TreselerArticle: 35041
Don Husby wrote: > How do I prevent Synplify from optimizing away my > attempts to replicate logic? > > For the following code, synplify will merge the two instances > of Shift into the same net: > > wire [1:0] Shift /* synthesis syn_keep=1 */; > assign Shift[0]= Sending & !Stall | !Ready; // > assign Shift[1]= Sending & !Stall | !Ready; // Replicated > I assume you're doing this for fanout reasons so it might work to have a single wire definition and then use the syn_maxfan attribute either at HDL [it its allowable] or in a .sdc constraints file. > > Also, is there some way to get synplify to print a message when > it encounters an attribute? Otherwise, there's no way to tell > if the attribute has an error that causes it to not be recognized > as an attribute. Some, but not all, messages about unrecognised attributes/directives appear in the .srr synth report file. This is a real killer issue. Mounting one of my pet hobby horses I'd say that the use of a synth tool specific comment based ``pragma'' syntax is *brain dead*. Consider this in the case of Synplify: wire foo/* synthesis syn_xxx */; won't be recognised for some attributes because there's no space before the first `/'. It just becomes an ordinary comment & gets thrown away. I think the lack of a formalised, standardised, error checked, attribute/directive syntax to be one of the Verilog synth tools weakest points. VHDL has the syntax but I think the ``ignore it'' attitude to errors is present there as well. Even something as simple as adding ``synthesis'' as a keyword and then doing something like synthesis foo a=b, c=d, ..., y=z; would be a start.Article: 35043
There may be an 'official' way, but I have always ended up instantiating the LUT. Which is not too difficult in VHDL but, AFAIK, tricky in Verilog. "Don Husby" <husby_d@yahoo.com> wrote in message news:35802095.0109181335.38d1e3a1@posting.google.com... > How do I prevent Synplify from optimizing away my > attempts to replicate logic? > > For the following code, synplify will merge the two instances > of Shift into the same net: > > wire [1:0] Shift /* synthesis syn_keep=1 */; > assign Shift[0]= Sending & !Stall | !Ready; // > assign Shift[1]= Sending & !Stall | !Ready; // Replicated > > Also, is there some way to get synplify to print a message when > it encounters an attribute? Otherwise, there's no way to tell > if the attribute has an error that causes it to not be recognized > as an attribute.Article: 35044
"Marius Vollmer" <marius.vollmer@uni-dortmund.de> wrote > I'm having problems mixing and matching VHDL and EDIF source files in > FPGA Compiler II. Basically, I want to instantiate a RAM block that > has been generated by the Xilinx CoreGen tool in a VHDL description. > I can't get it to work, and from the documentation that I could find, > it should just work, without any tricks. I suspect there is something > wrong with buses, since single-bit signals connect fine, while buses > don't. Try checking outer.edf to see if the bus representation maps. From memory, I cannot recall the exact syntax. But your inner.edf includes this: > (port > (rename input_0 "input<0>") > (direction INPUT) > ) so outer.edn should also go the "input<0>" route. If it uses "input[0]" or whatever, the files will not mate. There should be a switch in the synth to control 'bus style'. << rest of post snipped >>Article: 35045
Do you have "resource sharing" disabled? Also, if you are trying to reduce fanout, just use the "syn_maxfan" directive and Synplify will replicate for you. -Kevin "Don Husby" <husby_d@yahoo.com> wrote in message news:35802095.0109181335.38d1e3a1@posting.google.com... > How do I prevent Synplify from optimizing away my > attempts to replicate logic? > > For the following code, synplify will merge the two instances > of Shift into the same net: > > wire [1:0] Shift /* synthesis syn_keep=1 */; > assign Shift[0]= Sending & !Stall | !Ready; // > assign Shift[1]= Sending & !Stall | !Ready; // Replicated > > Also, is there some way to get synplify to print a message when > it encounters an attribute? Otherwise, there's no way to tell > if the attribute has an error that causes it to not be recognized > as an attribute.Article: 35047
I would want to finish my QPSK modulator including the NCO because I
spend really many time on it and I like to bring it to the end, I
think this could be useful also for other applications.
In any case I think to not be again ready to produce the simplified
QPSK modulator, cause I have again the following doubts :
1) I'm producing a QPSK modulator using a 165MHz clock to give out of
the NCO a 41.25MHz sine and cosine always clocked at 165MHz. In the
simplified schema I've to take away the NCO and substitute it with a
black box that produce a sequence 1 , 0 , -1 , 0 , .... on the cosine
branch and a sequence 0 , 1 , 0 , -1 on the sine branch, but these
sequences are clocked at 165MHz or 41.25MHz ??
2) I know it could be possible to take away the two multipliers and
just work on the final adder to add or subtract depending on the
sequence, but I always need a black box that send the information to
add or subtract and this must be clocked at 165MHz, is this right ??
3) All these zero in the sequence could be used to interpolate 2 ,
this means that the output of the black box sending signals to the
adder/subtractor must be clocked at 165/2= 82.5MHz while the output
coming from the SRRC also must arrive at the same rate ??
really thanks in any case ...
Antonio D'Ottavio
Article: 35048I want to produce 21 coefficients for a SquareRootRaisedCosine filter that interpolate 3, until now I used Matlab and it's function rcosine but it automatically produce a 19 coefficient filter and I don't like to add two zeroes to produce the filter I need, can you explain how I can design this filter ??? Really Thanks in any case ... Antonio D'OttavioArticle: 35049
Hi : Thanks very much for your answer. Actually, my case is that two async signals come out from the same CLB to 2 output pads. I want the routing delay for those two signals shall be similar. The usual routing medthod is to get minimum delay. In order to match the routing delay, I think the easy way shall be increase routing dealy for one signal to match the other. However, I did not find a way to do it easily in FPGA editor. Best regards, Lin CH
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