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Rick Filipkiewicz <rick@algor.co.uk> wrote: :> I need to use more than 4 clocks in my design. The synthesis tool :> (Foundation series) complains about the resource (clock) while I try for :> implementing my design since there are 4 dedicated clock inputs ONLY :> (Virtex-E , V1000). : : By default most synth tools automatically detect clock nets and assign : whatever global buffers are available to them. In your case you have to : decide which clocks are less important and turn this off. I'm back to college so I don't have a SynPro license anymore to test the syn_noclockbuf however that's not exactly the behavior I understood. On most parts, you can think of the dedicated input pads and the global buffer as different things. In many cases you want to use a dedicated GCLKIOB pad for a conventional clock or reset signal. In other cases you will use a normal pad, do some more asic-minded gating, then run the "rightmost" actual clock network into a BUFG for good distribution. In the latter case you could use a BUFG but not the dedicated input. With Synplicity there are at least two important constratints, xc_padtype and syn_noclockbuf. A signal will be defined as a clock if it is autodetected or listed in the SCOPE definitions. On most designs though, the xc_padtype will be most important so you can specify which ones get the dedicated input pins. There are relatively few times I can think of for syn_noclockbuf since you almost always want to use the good resources if they're available. The original poster's error actually sounds to me like too many GCLKIOBs are being used which I frequently saw when using dc_shell. The solution there might be to define -no_clock everything then define -clock the signals that you want as GCLKIOBs. Neither FPGA Express nor Synplicity gave me that too-many-used problem; the only time I had to constrain was when I wanted specific signals to use the resource instead. It helps to mention what synth tool is being used to make an EDIF, I didn't see that in the original post. -- O..O Arcade machine collection: (----) http://www.science.wayne.edu/~joey/arcade/ ( >__< ) IRC - EFNet #rgvac: demigod2k ^^ ~~ ^^Article: 34676
Harry Chung wrote: > I try to configurate a FPGA by a XC18V04 and I would like to download the bitstream file to the Prom by a universal programmer. Then, what kind of file should I provide to the programmer, *.mcs, *.exo or *.hex? > Moreover, if I power on the system, what is the typical time required for a complete configuration of FPGA by prom? Or how long should DONE become HIGH? The manufacturer should know about things like this, don't you think? Read your programmer documentation and look at this page for information about your FPGA. http://www.xilinx.com/partinfo/databook.htm /TorbjörnArticle: 34677
Check out this XCELL journal note by Peter Alfke. http://www.xilinx.com/xcell/xl33/xl33_30.pdf "Sriram S" <aadityas@hotpop.com> wrote in message news:78d34a9b.0109012328.1ce1a21@posting.google.com... > Hi friends, > > Without using a DLL/PLL how can i multiply a clock by 1.5. > > I belive a Lookup Table method can be used. But this is not an optimal method. > Please give more ideas on this....... > > > Kind regards > sriramArticle: 34678
Segmented interconnect permits a short local connections without having to drive a signal across the whole chip. Each segment drives less inputs, so the loading is also less. As a result, the segmented routing can be significantly faster than a more globally routed architecture. The segmentation also means that less routing resource is needed because use of part of a run does not block off the run all the way across the chip. Segmented routing does, however, mean that signals that need to travel a significant distance must pass through multiple switchnodes, each of which adds a delay to the route. The higher performance available with segmented route is quickly degraded without careful placement to ensure critical paths use the shortes possible routes. Globally routed devices generally have a quite uniform delay for any destination on a run, so placement becomes considerably less critical on those devices, but since even local routes drive the long lines, the performance is relatively limited. This is why you see long routes in the segmented route architectures such as Xilinx. Likewise, the newer Altera families are getting more of a hierarchical structure to their routing (local routes between LABs) to help bring up performance. The effect of the segmented vs global routing on pin placement is a secondary effect. Russell Shaw wrote: > Hi all, > > What advantages/disadvantages do segmented-interconnect fpgas have over > continuous interconnect cplds? > > Is there more flexibility in placing pins with segmentation? > > A vs X: > > http://www.altera.com/literature/pib/pib18_01.pdf > > -- > ___ ___ > / /\ / /\ > / /__\ Russell Shaw, B.Eng, M.Eng(Research) / /\/\ > /__/ / Victoria, Australia, Down-Under /__/\/\/ > \ \ / http://home.iprimus.com.au/rjshaw \ \/\/ > \__\/ \__\/ -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 34679
Hello again, Thanks to everyone for your responses. Because my application is totally fixed, coefficients and all, I thought OTP might be a good solution however the main requirement driving me to OTP is the need for a 20 year shelf life. Considering your responses about doing dsp without distributed arithmetic and prototyping with OTP chips I went back to the Xilinx web page and took a look at their OTP serial proms. They say right on the front page, "Guaranteed 20 year life data retention". A 30 millisecond configuration time is probably acceptable and I don't have to learn a new tool set. I checked prices at http://www.insight-electronics.com/order/index.html and it looks like the XC2S30-5VQ100C Spartan II is about $10 and the XC17S30AVO8C OTP serial prom is $3. Life is good. -- Pete Dudley Arroyo Grande SystemsArticle: 34680
Hi all, Can anyone help? I am looking for documentation on how the ICR JTAG register is accessed in Altera APEX 20K devices, and how you use it to upload (say) a .sof or .pof file to the device. There doesn't appear to be any information on configuring the device this way on Altera's website and I have tried a search on the net to no avail. The other JTAG registers all seem to be well documented and I have written a little program to clock data in and out IDCODE and BYPASS registers, which seems to work fine. However, the Apex datasheet stops short of describing the ICR. I don't even know how many bits wide it is. Does anyone have any information about Altera JTAG programming? I would rather not have to port the JAM player utility, as I only want to download files to this one device (and don't really want to mess about making JAM files). Unfortunately, the board I have only has a JTAG connection, otherwise I would (naturally) go for PS mode configuration. A JAM source file for the APEX chip might be helpful. Does anyone know where I could get one? Thanks in a advance, NeilArticle: 34681
pete dudley wrote: > > Hello again, > > Thanks to everyone for your responses. > > Because my application is totally fixed, coefficients and all, I thought OTP > might be a good solution however the main requirement driving me to OTP is > the need for a 20 year shelf life. Considering your responses about doing > dsp without distributed arithmetic and prototyping with OTP chips I went > back to the Xilinx web page and took a look at their OTP serial proms. They > say right on the front page, "Guaranteed 20 year life data retention". A 30 > millisecond configuration time is probably acceptable and I don't have to > learn a new tool set. > > I checked prices at http://www.insight-electronics.com/order/index.html and > it looks like the XC2S30-5VQ100C Spartan II is about $10 and the > XC17S30AVO8C OTP serial prom is $3. > > Life is good. People still run PDP-8's that date from the the late 60's. That is over 30 years running! Ben. -- Standard Disclaimer : 97% speculation 2% bad grammar 1% facts. "Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk Now with schematics.Article: 34682
Hi everybody,
Has anyone tried to use one of the available 8 global lines (in
APEX20K1000E by Altera) for an internally generated signal? Also the
same question for an input signal coming into the chip through a
non-dedicated (general purpose) pin?
What constraint(s) should I apply on the signal at the RTL/synthesis
or/and P&R level to get it done correctly? (P&R tool is Quartus II, ver
1.1)
Any help is appreciated...
Thanks
Ozkan
Article: 34683Evry now and again I find it necessary to use a multicycle contraint to get a design through timing. Clearly this can only be done after convincing myself that the code really does allow it. The problem is that some small code change could suddenly render the m-c illegitimate so I consider m-cs to be inherently fragile. Generally I only use them as scaffolding and hope to get rid of them in the end through low cunning & pipelining. I'd like to find some automatic way of relating the code to the constraint so that if the code changes but the constraint doesn't the synth or build process errors out.. Has anybody done this sort of thing or have any ideas how I might go about it ?Article: 34684
Neil Stainton <neil_manc@yahoo.com> wrote in message news:3b93bdd2$1@news.star.co.uk... > Hi all, > > Can anyone help? I am looking for documentation on how the ICR JTAG register > is accessed in Altera APEX 20K devices, and how you use it to upload (say) a > .sof or .pof file to the device. There doesn't appear to be any information > on configuring the device this way on Altera's website and I have tried a > search on the net to no avail. > > The other JTAG registers all seem to be well documented and I have written a > little program to clock data in and out IDCODE and BYPASS registers, which > seems to work fine. However, the Apex datasheet stops short of describing > the ICR. I don't even know how many bits wide it is. > > Does anyone have any information about Altera JTAG programming? I would > rather not have to port the JAM player utility, as I only want to download > files to this one device (and don't really want to mess about making JAM > files). Unfortunately, the board I have only has a JTAG connection, > otherwise I would (naturally) go for PS mode configuration. > > A JAM source file for the APEX chip might be helpful. Does anyone know where > I could get one? > > Thanks in a advance, > > Neil > Near as I can figure, Altera's "preferred" way for someone to program a part would be to use a stand-alone JAM player on a Windows machine and just play out the jam file that Quartus II or MaxPlus II creates. You can get a Windows JAM player at http://www.jamisp.com (There's also 'C' source code for an 8051 JAM player). If you don't have a PC handy for this purpose, you may have some luck talking to your local Altera FAE, explaining your need, and getting more information that way. To get a JAM source file for an APEX chip, you can use any .POF or .SOF file that you already have and use the convert utility in MaxPlus II or Quartus II to generate a JAM file. -Pete-Article: 34685
Ozkan Dikmen <dikmen@eng.umd.edu> wrote in message news:3B93F7D3.F6513C0@eng.umd.edu... > Hi everybody, > Has anyone tried to use one of the available 8 global lines (in > APEX20K1000E by Altera) for an internally generated signal? Also the > same question for an input signal coming into the chip through a > non-dedicated (general purpose) pin? > What constraint(s) should I apply on the signal at the RTL/synthesis > or/and P&R level to get it done correctly? (P&R tool is Quartus II, ver > 1.1) > > Any help is appreciated... > > Thanks > > Ozkan > The synthesis construct depends upon your synthesis tool. Let me know what you're using for synthesis and I should be able to help you specify a global resource. To do this at the P&R level (Quartus II), go to the assignment organizer and select the signal you wish to have on a Global resource (Edit specific entity and node settings for...). Select Options for Individual Nodes Only and then set Global Signal to "On". Note that Global "On" will always put the signal onto a global net (as long as there is a global net available) and global "Off" will never put a signal on the global nets. Signals that don't have an "On" or "Off" setting will be placed on the global nets gnerally according to the fan-out of the signal. I hope this helps. -Pete-Article: 34686
On Tue, 04 Sep 2001 00:33:55 +0100, Rick Filipkiewicz
<rick@algor.co.uk> wrote:
>Evry now and again I find it necessary to use a multicycle contraint to
>get a design through timing. Clearly this can only be done after
>convincing myself that the code really does allow it. The problem is
>that some small code change could suddenly render the m-c illegitimate
>so I consider m-cs to be inherently fragile. Generally I only use them
>as scaffolding and hope to get rid of them in the end through low
>cunning & pipelining.
>
>I'd like to find some automatic way of relating the code to the
>constraint so that if the code changes but the constraint doesn't the
>synth or build process errors out..
>
>Has anybody done this sort of thing or have any ideas how I might go
>about it ?
Hi Rick,
Here's how I do it.
I add a behavioural delay when I drive the signal at the start of the
mc path.
sig <= other_sig after x ns;
I choose 'x' to be just under half a clock period less than the
intended multicycle time spec.
The synthesiser will ignore the after.
I also add a big comment saying what I'm doing, in case someone else
has to modify the code.
(I know that this method won't please some people, but hey, it works
for me.)
Regards,
Allan.
Article: 34687Russell Shaw <rjshaw@iprimus.com.au> wrote in message news:3B930207.41DEB05C@iprimus.com.au... > Hi all, > > What advantages/disadvantages do segmented-interconnect fpgas have over > continuous interconnect cplds? > > Is there more flexibility in placing pins with segmentation? > > A vs X: > > http://www.altera.com/literature/pib/pib18_01.pdf > > -- > ___ ___ > / /\ / /\ > / /__\ Russell Shaw, B.Eng, M.Eng(Research) / /\/\ > /__/ / Victoria, Australia, Down-Under /__/\/\/ > \ \ / http://home.iprimus.com.au/rjshaw \ \/\/ > \__\/ \__\/ Ray Andraka did a good job describing the differences. One thing I would like to point out is that the Altera document you're pointing to is six (!) years old. Like Mr. Andraka points out, newer Altera families have a heirarchy of interconnect. APEX 20KE devices have LAB interconnects span 10 logic elements (LUT/FF cells), MegaLAB interconnects span 16 or 24 LABs, and several other levels of interconnect that are shorter than all-the-way-across-the-device. To see even a different implementation of interconnect, take a look at Altera's Mercury devices. In those the I/O pads are dispersed throughout the die rather than just around the edges, giving you the ability to use local interconnect on I/O signals, even from nodes burried in the middle of the device. I would suggest that the Altera document you point to doesn't mean much with respect to the more current familes of programmable logic devices. BTW, I think that this idea of interconnect hierarchy is applicable to Xilinx devices too - maybe someone who understands the Virtex II architecture better that I could address what having more slices per CLB means with respect to local interconnect within a CLB vs. interconnect between CLBs. -Pete-Article: 34688
Hi I downloaded a floating point arithmetic core from opencores.org. The core is written in verilog. I have never used verilog before, how can I implement it into a VHDL design. Do I incorporate it as a component and then use port mapping as in VHDL? Does anyone have any examples on how to do this? Thanks Andrew :-)Article: 34689
Allan Herriman wrote:
> On Tue, 04 Sep 2001 00:33:55 +0100, Rick Filipkiewicz
> <rick@algor.co.uk> wrote:
>
> >Evry now and again I find it necessary to use a multicycle contraint to
> >get a design through timing. Clearly this can only be done after
> >convincing myself that the code really does allow it. The problem is
> >that some small code change could suddenly render the m-c illegitimate
> >so I consider m-cs to be inherently fragile. Generally I only use them
> >as scaffolding and hope to get rid of them in the end through low
> >cunning & pipelining.
> >
> >I'd like to find some automatic way of relating the code to the
> >constraint so that if the code changes but the constraint doesn't the
> >synth or build process errors out..
> >
> >Has anybody done this sort of thing or have any ideas how I might go
> >about it ?
>
> Hi Rick,
>
> Here's how I do it.
>
> I add a behavioural delay when I drive the signal at the start of the
> mc path.
>
> sig <= other_sig after x ns;
>
> I choose 'x' to be just under half a clock period less than the
> intended multicycle time spec.
> The synthesiser will ignore the after.
>
> I also add a big comment saying what I'm doing, in case someone else
> has to modify the code.
>
> (I know that this method won't please some people, but hey, it works
> for me.)
>
> Regards,
> Allan.
Allan,
Looks nice as a form of protection but its going to need some work for
signals buried deep inside some state machine. However even there I think it
will work if I get can rid of any unnecessary assignments i.e. things like:
statex:
...
foo <= 0;
....
where foo is already 0. To reverse this I could, by fiat, say that if this
trick doesn't work for any particular signal then that signal is not allowed
an m-c.
If I were to parameterise it I could also make it dependant in simulation
clock speed.
A, possibly absurd, idea I had was to pack such signal definitions into
their own module which would be made read-only by default ...
Maybe what's needed here is a free Verilog parser I can hack about with
(icarus ?).
Article: 34690On Tue, 04 Sep 2001 07:50:33 +0100, Rick Filipkiewicz <rick@algor.co.uk> wrote: > > >Allan Herriman wrote: > >> On Tue, 04 Sep 2001 00:33:55 +0100, Rick Filipkiewicz >> <rick@algor.co.uk> wrote: >> >> >Evry now and again I find it necessary to use a multicycle contraint to >> >get a design through timing. Clearly this can only be done after >> >convincing myself that the code really does allow it. The problem is >> >that some small code change could suddenly render the m-c illegitimate >> >so I consider m-cs to be inherently fragile. Generally I only use them >> >as scaffolding and hope to get rid of them in the end through low >> >cunning & pipelining. >> > >> >I'd like to find some automatic way of relating the code to the >> >constraint so that if the code changes but the constraint doesn't the >> >synth or build process errors out.. >> > >> >Has anybody done this sort of thing or have any ideas how I might go >> >about it ? >> >> Hi Rick, >> >> Here's how I do it. >> >> I add a behavioural delay when I drive the signal at the start of the >> mc path. >> >> sig <= other_sig after x ns; >> >> I choose 'x' to be just under half a clock period less than the >> intended multicycle time spec. >> The synthesiser will ignore the after. >> >> I also add a big comment saying what I'm doing, in case someone else >> has to modify the code. >> >> (I know that this method won't please some people, but hey, it works >> for me.) >> >> Regards, >> Allan. > >Allan, > >Looks nice as a form of protection but its going to need some work for >signals buried deep inside some state machine. However even there I think it >will work if I get can rid of any unnecessary assignments i.e. things like: > >statex: > ... > foo <= 0; > .... > >where foo is already 0. To reverse this I could, by fiat, say that if this >trick doesn't work for any particular signal then that signal is not allowed >an m-c. > >If I were to parameterise it I could also make it dependant in simulation >clock speed. > >A, possibly absurd, idea I had was to pack such signal definitions into >their own module which would be made read-only by default ... > >Maybe what's needed here is a free Verilog parser I can hack about with >(icarus ?). Hi Rick, My apologies for posting VHDL at you when you are a Verilog guy. I should point out that it's important to test with this behavioural delay set to zero, as only simulating with the delay set to some nominal value can hide other problems. As you say, this works much better if the assignment is made in only one place. Regards, Allan.Article: 34692
Hi, Can anyone tell me the quickest way to make an output on the Spartan XL (3.3V) open collector. I read in the documentation that you can use a tri-state buffer, but the method doesn't make sense to me. It says tie the tri-state pin to the output, and tie the input to ground. If the input pin is to ground, where doesn my input signal go? To the tri-state pin? Anyway, there must be another way to configure the pin to opn-collector... I just can't find it as of yet. Thanks AdrianArticle: 34693
There is a tri-stateable buffer in the output cell (IOB)
It has three signals: "in", "out", "tri-state control".
The "in" pin is driven by FPGA stuff
The "tri-state control" pin is driven by FPGA stuff
The "out" pin connect to an external pin of the FPGA
You have a signal that you want to go off-chip, as an open collector
siglal (when logic low, drives low, when logic high, does not drive, and
relies on an external pullup circuit (resistor for example) to establish a
logic high.
Connect your output signal to the "tri-state control" pin of the output buffer
Connect the "in" pin of the output buffer to ground (0, low)
The "out" pin of the output buffer is already connected to the package pin.
When your output signal is low, in enables the buffer, so it drives the "out"
pin low, because the "in" pin is low.
When your output signal is high, the buffer is tri-stated, and the output level
is determined by external factors.
The on-chip pullup resistors are not appropriate for open-collector type
pullup. You need an external resistor with a value probably below 2000 ohms.
("tri-state" is a registered trade mark of National Semiconductor )
Philip
On Tue, 4 Sep 2001 09:45:08 +0200, "Noddy" <g9731642@campus.ru.ac.za> wrote:
>Hi,
>
>Can anyone tell me the quickest way to make an output on the Spartan XL
>(3.3V) open collector. I read in the documentation that you can use a
>tri-state buffer, but the method doesn't make sense to me. It says tie the
>tri-state pin to the output, and tie the input to ground. If the input pin
>is to ground, where doesn my input signal go? To the tri-state pin?
>
>Anyway, there must be another way to configure the pin to opn-collector... I
>just can't find it as of yet.
>
>Thanks
>Adrian
>
>
Philip Freidin
Fliptronics
Article: 34694T<= input signal I<= gnd O<= output That way When the input signal is active (obuft is active low input, obufe is active high input) the outputdrives to ground, when inactive it is hi-Z. Noddy wrote: > Hi, > > Can anyone tell me the quickest way to make an output on the Spartan XL > (3.3V) open collector. I read in the documentation that you can use a > tri-state buffer, but the method doesn't make sense to me. It says tie the > tri-state pin to the output, and tie the input to ground. If the input pin > is to ground, where doesn my input signal go? To the tri-state pin? > > Anyway, there must be another way to configure the pin to opn-collector... I > just can't find it as of yet. > > Thanks > Adrian -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 34695
Hi everybody.
I search a DAC model core. There is the DAC XILINX model but I would like
an other model.
Thank you.
Best regards.
Olivier.
PS : Is there a AY-3-8192 or similarly model in FPGA ?
Article: 34696
opende2001@aol.com (Opende2001) wrote in message news:<20010815095730.27208.00000830@mb-fr.aol.com>...
> Hello
>
> I want to design my own sound chip using Fpga. The aim is to build a chip able
> to play in hardware standard sound format as MP3, WAV... and emulate AY and SID
> format. Is there some people interrested to help me in this project ?
Hi.
It's very interresting because ... I search too many help to design a
AY-3-8192 by using FPGA.
I have many informations about AY-3-8192 and I search any informations
about
DAC to build it in FPGA.
My email is seilebost@aol.com
I enjoy to help you.
BEST REGARDS.
Seilebost.
PS : My site : passionoric.ifrance.com. I design a retro-computer
compatible
ORIC ATMOS, an old 8 bit.
Article: 34697I'm testing as well - so please ignore me too!! "Rick Filipkiewicz" <rick@algor.co.uk> wrote in message news:3B85617C.E0BA6B4@algor.co.uk... > > ---------------------------------------------------------------------------- ---- > Ignore - testing attach. >Article: 34698
Petter Gustad <newsmailcomp1@gustad.com> wrote: > Thats the response I got from Xilinx too. I'm awaiting the CD from my > local distributor... > BTW: Why don't they provide the device libraries on the web... It seems the device upgrade CD contains more than the libraries.. it contains a customised service pack 6. After installing the XC2V support you will need to reinstall service pack 8. PAR behaves differently for XC2V designs (different placer steps in particularly). Mincut placer, constructive placer, optimizing placer etc, rather than just two stages for XCV(E). Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 34699
Hello I have the foundation 3 as my design tools before and I've made a lot of schematics with the environment provided in foundation. However, there is a brand new ISE 4 foundation. I know ISE always integrating vhdl files, and the schematics in ISE is not the same as the foundation. If I want to switch those schematic projects to ISE 4.0, any methods? Terrence Mak
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