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You can't really depend on the ISA bus signals being synchronous with sysclk. You don't need BALE. You should use IOW to clock in the data and address, then transfer that latched address and data to your local clock domain using sound async transfer techniques. For reads, sync up IOR to advance your local counter on the end of a read access. IOW should go into the FPGA via a global clock pin if possible. DIVERSEG wrote: > I have always tried to stick to sync designs. > However lately I have ran into a problem. > While designing some isa cards I read somewhere that I did not need to use BALE > to latch my address lines. > > Is this acceptable? > > Also I am decoding using a state machine in a FPGA with Sysclk as the clock for > transitions in my state machine. > > Last week I changed CPU and the new CPU card does not drive Sysclk. > Now my boards do not work. I called the board designer and de says that sysclk > now a days is not sync with the I/O signals anyway? > > Who do i believe? > > Is async acceptable? > > Are the address lines stable so BALE is not nescessary? > > Any comments suggestions? > > Xilinx foundation users is it possible to take the VHDL created by the state > diagram editor and make the state machine async and dependant on the input > signal transitions to go from one state to another? > > Steven Collins > Macha International, Inc. > 713-723-5040x13 > scollins@macha.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 34626
I guess my question is, I thought Savant was a Unix based application, How do you run it on windows? Eric Smith wrote: > Dave Colson <dscolson@rcn.com> writes: > > Could you describe you method for running savant with the Web Pack? > > I would be interested. > > I just ran Savant normally. There's no integration with WebPack.Article: 34627
What do you mean by "wobbly?" Is there a hump or two after the rise and fall that you don't think is square? Is the duty cycle running between 30% and 70%? Is the time interval from 1.4V crossing low-to-high and 1.4V crossing high-to-low producing times from 39 to 41 nS? Do you see "hash" on the logic high signal? Noddy wrote: > Hi, > I am using the Spartan XCS10XL just as a clock signal (using as an encode > signal for an A/D). Anyway, I'm reading the clock signal into the FPGA on a > global clock buffer, put it into a toggle to halve the frequency(from 50 to > 25MHz), and then output it again on a standard output pad. However, at 25MHz > I would expect the signal from the toggle to be pretty close to square, but > my signal still looks very wobbly. > > Can anyone give any suggestions? > > AdrianArticle: 34628
I have such experienced last month, maybe you could try Hardware Debugger which is more user friendly I think. Or a package maybe outdated in your Xilinx software(eg. fundation), you may check the support page in xilinx web. "Justin Oo" <JOo@lbl.gov> ????? news:ad213de0.0108211650.4f99ec73@posting.google.com... > hi, > i am having trouble using JTAG...i have Virtex XCV300 board (VW-300 > Virtual Workbench from VCC)...and when i try to download my design > .bit file thru JTAG onto the board...the JTAG PROGRAMMER crashed on > me. I put the JTAG chains which i believe for my board is as follow: > > -------------- --------------- > TDI--| XCV300_BG352 |----| XC9536 |-----| > | mydesign.bit | | JED/BIT File? | | > |--------------| |---------------| | > | > | > TDO -------------------------------------------| > > so where "JED/BIT File?", i try to specify the XC9536.bsd file...but > as soon as i do that...the JTAG Programmer crashes... > > "The instruction at "0x5f40129c" referenced memory at "0x00000004". > The memory could not be read." > > any idea how i can get around it? i tried BYPASSING that XC9536 as > well...but if i do that i get the message that says " The JTAG chain > has one or more devices that are of an undefined type." any input is > very much appreciated! Thanks! > > -- > " Great minds discuss ideas; > Average minds discuss events; > Small minds discuss people. " > ~ JustinArticle: 34629
Hi, where I can get the JBit SDK? Terrence "Dereck" <dereckaf@yahoo.com> ????? news:ee722b5.-1@WebX.sUN8CHnE... > 1. Is the lastest version of JBits 2.0.1 > 2. Does the lastest version or the version above support programming of > the Pads, does it have IOB support. > I require this to test the CLBS on the Periphery. > > My advisor did not recommend the use of the latest version of Jbits which > I had contacted you for instead he wants to use the JBits 2.0.1. > Please let me know if its a good idea. Incase the new version has fixed > some critical bugs. > > 3. I guess JBits can be used only with a existing bitstream. Now we don't > have Virtex hardware with us. Can you tell me where can I get a input > bitstream for XCV 800 and other Virtex parts. > I need this to test my tool which is essentially a Interconnect Test tool. > > Thank you, > Dereck FernandesArticle: 34630
What's the load on the signal? Noddy wrote: > > Hi, > I am using the Spartan XCS10XL just as a clock signal (using as an encode > signal for an A/D). Anyway, I'm reading the clock signal into the FPGA on a > global clock buffer, put it into a toggle to halve the frequency(from 50 to > 25MHz), and then output it again on a standard output pad. However, at 25MHz > I would expect the signal from the toggle to be pretty close to square, but > my signal still looks very wobbly. > > Can anyone give any suggestions? > > AdrianArticle: 34631
Perhaps you should use a local clock of some reasonable speed to synchronize the ISA signals and run your state machine? --a DIVERSEG wrote: > > I have always tried to stick to sync designs. > However lately I have ran into a problem. > While designing some isa cards I read somewhere that I did not need to use BALE > to latch my address lines. > > Is this acceptable? > > Also I am decoding using a state machine in a FPGA with Sysclk as the clock for > transitions in my state machine. > > Last week I changed CPU and the new CPU card does not drive Sysclk. > Now my boards do not work. I called the board designer and de says that sysclk > now a days is not sync with the I/O signals anyway? > > Who do i believe? > > Is async acceptable? > > Are the address lines stable so BALE is not nescessary? > > Any comments suggestions? > > Xilinx foundation users is it possible to take the VHDL created by the state > diagram editor and make the state machine async and dependant on the input > signal transitions to go from one state to another? > > Steven Collins > Macha International, Inc. > 713-723-5040x13 > scollins@macha.comArticle: 34632
Abhimanyu Rastogi wrote: > > Hello, > > I have been working on this project of mine using Altera's AHDL tools and > now when I all the code is done, i wanted to simulate it to see what i get > as my result. > > I don't why i am getting 2 different results :- > 1) when i use Functional SNF extractor I get my output exactly as i wanted. > And after simulating thru functional snf i simulate it again without it with > just normal simulation features (compiler netlist extractor, database > builder, logic synth, partitioner, fitter (not quartus fitting), assembler) > to get a TFF file which i include in a dll. this thing work fine but i when > i chk for my clock output on the test pin i don't get any signal ... why is > that?? > 2) when i use Timing SNF extractor i don't get my ouput correctly... like > some are delayed and thus throws out wrong information on simulation. > > Now is there any way so that i don't get all these problems with timing.... > i'm using FLEX 8000 series chip... i'll even attach the tdf anf scf file for > ur convenience. Um, I don't mean to be harsh, but the whole point of the functional vs timing SNF extractors is that the former will not have any delay information, and the latter will. If your design is functionally correct, AND you've fully specified static timing constraints, you should be fine. Of course, you have to be completely clear on what your FPGA talks to. -andyArticle: 34633
Austin Franklin wrote: > Yes, but no corporate environments I've ever worked in use Linux. Then look around. Many engineering departments support it either officially or unofficially. But don't look in the marketing department. They're still making powerpoint slides to impress each other at outlook-scheduled meetings. --Mike TreselerArticle: 34634
Dereck wrote: > 3. I guess JBits can be used only with a existing bitstream. Now we don't > have Virtex hardware with us. Can you tell me where can I get a input > bitstream for XCV 800 and other Virtex parts. Uh, oh. You need to have the Xilinx tools, which generate the bitstream. That means you also have to have a design that you implement in the FPGA. What DON'T you know about FPGAs? How much information has your advisor actually given you? Sounds like he's keeping you in the dark. -andyArticle: 34635
Nisreen Taiyeby wrote: > > I am working with virtexE speed grade 8, xilinx alliance series with service pack 8. > > When I generate the sdf file for timing simulation, the setup times for flops placed in the IOB is given as 271 ps which happens to be the setup for CLB flops too. > > But the latest datasheets on VietexE device gives the IOB setup of 1.3 ns. > > That means that my timing simulation is faulty. Sounds like the flops are not in the IOB. Check the FPGA Editor to be sure. You'll have to set the magic option in the mapper to enable pushing flops into the IOB. I think it's map -pr b There's also an option in the GUI somewhere. --aArticle: 34636
jaideep wrote: > > Hello, > We are working on schematic entry for the Virtex II device > XC2V3000-4BF957, but finding it difficult to enter manually. > It is time consuming to create this symbol as there are over > 900 pins. > If someone has this symbol, we would appreciate very much > if they can pass on the symbol.We are using an older version > of Orcad which doesn't have the CIS feature, hence this > request. Do yourself a large favor...don't make one huge symbol. Break it up into smaller symbols that represent the functionality of the pins. When you place the symbols on the schematic, you'll have U1:A, U1:B, etc. For instance, one section could be SDRAM interface, another could be PCI interface, a third could be coffee-maker interface. You get the idea. --aArticle: 34637
Dave Colson <dscolson@rcn.com> writes: > I guess my question is, I thought Savant was a Unix based application, > How do you run it on windows? I don't. I run it on Linux.Article: 34638
Dereck wrote: > 3. I guess JBits can be used only with a existing bitstream. Now we don't > have Virtex hardware with us. Can you tell me where can I get a input > bitstream for XCV 800 and other Virtex parts. "Andy Peters <andy [@] exponentmedia" <".> com"> writes: > Uh, oh. You need to have the Xilinx tools, which generate the > bitstream. That means you also have to have a design that you implement > in the FPGA. What DON'T you know about FPGAs? Actually, to use JBits you don't have to have the normal Xilinx tools (or WebPack) at all. You can get a raw bitstream for a part (such as the XCV800) by readback of a real part after reset. And you don't have to have a starting design done with the traditional tools. You can do it all in JBits. Whether a person would *want* to design things this way is another matter. Some people really like it, but most people prefer traditional HDLs or schematic entry.Article: 34639
I had assumed he had some local clock. If none, he can use the sysclk (if it is there at all), however, he cannot depend on the IOW or other signals being synchronous with that nominally 14.3 MHz clock...it isn't in most systems. If there is a question as to whether that clock even exists, or if you need a higher clock rate locally, put an oscillator on the board. Last I dealt with ISA (a few years ago now), one could still depend on having a sysclock, even though it was not often used. With the latest boards with barely feigned ISA support, this may no longer be true. "Andy Peters > Perhaps you should use a local clock of some reasonable speed to > synchronize the ISA signals and run your state machine? > > --a > > DIVERSEG wrote: > > > > I have always tried to stick to sync designs. > > However lately I have ran into a problem. > > While designing some isa cards I read somewhere that I did not need to use BALE > > to latch my address lines. > > > > Is this acceptable? > > > > Also I am decoding using a state machine in a FPGA with Sysclk as the clock for > > transitions in my state machine. > > > > Last week I changed CPU and the new CPU card does not drive Sysclk. > > Now my boards do not work. I called the board designer and de says that sysclk > > now a days is not sync with the I/O signals anyway? > > > > Who do i believe? > > > > Is async acceptable? > > > > Are the address lines stable so BALE is not nescessary? > > > > Any comments suggestions? > > > > Xilinx foundation users is it possible to take the VHDL created by the state > > diagram editor and make the state machine async and dependant on the input > > signal transitions to go from one state to another? > > > > Steven Collins > > Macha International, Inc. > > 713-723-5040x13 > > scollins@macha.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 34640
So how do you use it with WebPack? Isn't WebPack Windows only? Or did I miss something? Eric Smith wrote: > Dave Colson <dscolson@rcn.com> writes: > > I guess my question is, I thought Savant was a Unix based application, > > How do you run it on windows? > > I don't. I run it on Linux.Article: 34641
Did not get the original post, so answerign to follow up. "Terrence Mak" <stmak@cuhk.edu.hk> writes: > Hi, where I can get the JBit SDK? Send a mail to jbits@xilinx.com. They will mail you an FTP URL and password. There is no download site. > "Dereck" <dereckaf@yahoo.com> ????? news:ee722b5.-1@WebX.sUN8CHnE... > > 1. Is the lastest version of JBits 2.0.1 2.7 > > 2. Does the lastest version or the version above support programming of > > the Pads, does it have IOB support. Yes. > > My advisor did not recommend the use of the latest version of Jbits which > > I had contacted you for instead he wants to use the JBits 2.0.1. > > Please let me know if its a good idea. Incase the new version has fixed > > some critical bugs. What bugs? I started with 2.4, now 2.5, and never found any bug (apart from the install programs, which suck, 2.6 will not even run under Linux). Just one weakness in the JRoute routing algorithm (reported to Xilinx about 1 week ago, so surely not yet resolved). > > 3. I guess JBits can be used only with a existing bitstream. Yes. > > have Virtex hardware with us. Can you tell me where can I get a input > > bitstream for XCV 800 and other Virtex parts. Null bitstreams for XCV300, XCV800 and XCV1000 are supplied with JBits. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual RobberyArticle: 34642
Original post did not arrive, so answering to followup. "Tim" <tim@rockylogic.com.nospam.com> writes: > "Dereck" <dereckaf@yahoo.com> wrote in message news:ee722b3.-1@WebX.sUN8CHnE... > > 1. Does the routing in the Tile for XC4000 and XCV800 widely differ. I Totally. 2 entirely different designs. Even the amount of LUT/FFs per tile are different (XC4000 2, XCV 4). > > saw a Jbits code for XC4000 which allows you to set the routing: > > jbits.set(row,col,Y.HORIZ_SINGLE1,Y.ON) > > Is this the same in XCV 800. Same syntax, but totally different constants. Also JBits has the JRoute router to automatically connect without looking at individual PIPs. > Virtex is much simpler and much more powerful. That also. The more I work with Virtex, the more I like this chip. > > 2. I am basically trying to understand how the routing looks in XCV800, In > > the databook for XC4000 you have a figure that gives detail of the > > Programmable Interconnect (Figure 27 Page 6-30). > > Do you have a similiar page for XCV 800 or is it the same. I once sketched out part (hex and long line smissing) of the Virtex/XCV routing based on the JBits documentation: http://neil.franklin.ch/Projects/PDP-10/Virtex-CLB-PIPs > > 3. I need to know how many single,double,long lines are present in each > > tile. > > The basics are in the data sheet and visible in FPGA_editor. More > info comes with JBits. Single: 24 Double: none Hex: I can't remember, possibly 18 long lines: 6 IIRC -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Intellectual Property is Intellectual RobberyArticle: 34643
Kolja Sulimma wrote: > > > Like who? And what engineering tools run on it? (Linux) > > The whole Magma Asic Tool chain: www.magma-da.com > > > Does Xilinx run on Linux? > > There is Alliance for Linux. I am not sure how hard it is to get the Xilinx > support running. > > > Does, Viewlogic run on Linux? > > Does PADS run on Linux? > > Eagle does. Target also... > There are certainly good reasons to support either windows or unixes. > What I really do not understand is why many Unix based tool chains do not > support Linux. > A command line tool should be posix compliant and run more or less immediatly > under another linux flavor. And porting the Tclk/Tk interfaces of Cadence or the > like should not be that hard either. > > Kolja Sulimma With Linux people don't want to pay the BIG $$$ that Unix based software can charge. Ben. -- Standard Disclaimer : 97% speculation 2% bad grammar 1% facts. "Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk Now with schematics.Article: 34644
Dave Colson <dscolson@rcn.com> writes: > I guess my question is, I thought Savant was a Unix based application, > How do you run it on windows? I wrote: > I don't. I run it on Linux. Dave Colson <dscolson@rcn.com> writes: > So how do you use it with WebPack? Isn't WebPack > Windows only? Or did I miss something? Yes, WebPack is Windows only. I run WebPack on Windows, and Savant on Linux. As I said before, there is no integration between the two. I use them as two separate tools. I simulate my design with Savant, and synthesize with WebPack. I keep my sources on the Linux box, and use Samba to make them available to the Windows box. When I'm using my laptop, I run Windows under VMware.Article: 34645
Santiago de Pablo <sanpab@eis.uva.es> wrote in message news:3B8F5CD7.ED4ADAEE@eis.uva.es... > David Wright escribió: > > > > The "free" Xilinix Webpack should be classified as a Demo and not a real > > system to do even realistic small designs. > > > > By the time you install the design and even a small test vector, you easily > > exceed the 500-line ModelSim Starter Design Limit. There are even > > limitations on Test Bench and probably other portions of the package. > > I agree with the Bencher limitations: are stupid, because you can > generate > two or three vectors and then use notepad to copy-paste-modify. > > But I don't agree with the ModelSim (HDL only simulator) 500-line > limitation: > is more than enough to test modules separately, and there is no > slow-down if > you use *.do files. > > Please, check "http://www.dte.eis.uva.es/OpenProjects/OpenDSP/index.htm" > and > see how a complete DSP has been synthetized and simulated using WebPack. > > > Xilinx needs to stop misleading its customers and tell them what they really > > need to know: > > At least, it's (now) better than Altera's free tools. > > Enjoy, Santiago. That Altera comment is somewhat of a pot-shot. Given the degree of passion that can be invoked when comparing Altera and Xilinx, it usually is better to back up your opinions with some useful facts. I know there are a lot of people out there who would like to know the advantages and disadvantages of the free tool suites, and your comment really doesn't help much. I'm not going to speak to the Xilinx offering (having never used WebPack, that wouldn't be appropriate), but I will offer a pointer to Altera's description of their tools (http://www.altera.com/literature/sg/dtsg.pdf) and point out that the literature indicates that a free version of Altera's Quartus II tool is to be made available any day now. Maybe someone else will serve up a pointer to literature on the free Xilinx tools, and we can have a productive comparison/contrast discussion. Then again, maybe we don't want to get into another one of these X vs. A discussions right now after all. -Pete-Article: 34646
Hi all ! I need to use more than 4 clocks in my design. The synthesis tool (Foundation series) complains about the resource (clock) while I try for implementing my design since there are 4 dedicated clock inputs ONLY (Virtex-E , V1000). I would greatly appreciate if anyone can advise me how to solve this problem and how to connect a clock to a non-clock pad so that I can get rid of the extra clock(s). Thanks in advance, -- KhanArticle: 34647
> > Yes, but no corporate environments I've ever worked in use Linux. > > Then look around. Well, I have "looked around", that's why I made that statement, and my statement was correct. > Many engineering departments support it > either officially or unofficially. Like who? And what engineering tools run on it? Does Synplicity run on Linux? Does Xilinx run on Linux? Does, Viewlogic run on Linux? Does PADS run on Linux? Does AutoCAD run on Linux? When they all do, and they are fully supported, then I'll consider switching...that is if Linux will also run my film scanner, flatbed scanner, label maker, 2160DPI B&W digital photo printer...PROM programmer, Digital Video editing system...PhotoShip...as well as run on my notebooks (fully) ...and the list goes on. Linux is good, I have nothing against it...but support for it is far far far less than is for Windows. I need to spend my time doing engineering, not fussing with tools on unsupported platforms (or fussing with tools that don't give me the results I need).Article: 34648
Funny, Today before I read the response I used a local clock of sufficient speed to run my state machine. I thru out the BALE(I have read this is not usefull anymore, I am not sure why!). I used ADDRESS and AEN='0' and (iow='0' or ior='0') Beauitful !! Worked like a champ. I even tried other cpu boards works on all i tried so far!Article: 34649
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Compare FPGA features and resources
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